Abstract: Techniques to more readily identify issues that arise in connection with memory systems and streamline the analysis process. A detailed activity log is generate with corresponding start and stop traffic events to facilitate identification of problems in memory devices. Each event registered in the log includes numerous items of information. The information facilitates identifying the origin of a particular problem including when and where it occurred, thus making failure analysis (FA) both easier and faster.

Abstract: A non-transitory computer-readable storage medium storing a program that causes a computer to execute a process, the process includes acquiring first multiple tasks; dividing each task in the first multiple tasks in accordance with a cache size; classifying second multiple tasks in accordance with a range of data to be referred to at a time of execution of each task in the second multiple tasks that have been obtained by the dividing; and determining an execution order of tasks in a group for each group that has been obtained by the classifying.

Abstract: A processor with reduced interrupt latency is disclosed. An apparatus includes a processor core and a cache subsystem having a cache controller and a cache. The processor core is configured to submit, to the cache controller, requests for access to the cache, wherein a given request for access to the cache specifies whether the given request is abandonable or non-abandonable in an event of an interrupt request. In response to a particular interrupt request, the processor core may provide an indication to cause the cache controller to abandon requests for access to the cache identified as abandonable. After receiving an acknowledgement from the cache controller that the abandonable requests have been abandoned, the processor core may begin execution of an interrupt handler in order to service the interrupt request.

Abstract: A packet backpressure detection method and apparatus are provided. The method includes: a device which having a Peripheral Component Interconnect Express (PCIe) port storing a plurality of packets for transmission in a packet queue and storing a packet that is to be transmitted next in a first buffer, where the queue comprises a plurality of packets that are to be transmitted via the PCIe port; and the queue is stored in a second buffer; recording a storage duration of each packet stored in the first buffer, and accumulating the storage duration of each packet stored in the first buffer; removing the packet from the first buffer after the packet is transmitted via the PCIe port; and generating an indication of packet pressure at the PCIe port based on the accumulated storage duration.

Abstract: Countermeasures against fault injection attacks of a cryptographic integrated circuit, and more specifically laser fault injection attacks are provided. The invention consists in generating sequences of bits belonging to a set of allowed sequences, and storing these sequences on a set of Flip-Flops. Then the sequences stored on the Flip-Flops are checked and, if they do not belong to the allowed sequence, this is the sign that a fault injection attack occurred and caused a bit flip in one of the flip-flops. An alarm signal is then generated.

Abstract: A storage system and method for time-duration-based efficient block management and memory access are provided. In one embodiment, a controller of the storage system is configured to receive time stamps from a host for each of a plurality of blocks in the memory; determine a time duration for programming each of the plurality of blocks based on the time stamps; and differentiate the plurality of blocks based on the time durations. Other embodiments are provided.

Abstract: Disclosed is a power supply enable circuit. The power supply enable circuit includes a multi-input NAND gate, input terminals of the multi-input NAND gate respectively connected to a plurality of activation signal sources; and a delay circuit, an input terminal of the delay circuit electrically connected to a shared activation signal source of the plurality of activation signal sources. An output terminal of the delay circuit is electrically connected to an enable input terminal of a power supply circuit after performing a logical AND with an output terminal of the multi-input NAND gate.

Abstract: Provided are a connection management mechanism and a connection management method with which computer bus connections can be managed such that failures and freezes do not occur in a computer system when delays and packet losses occur. A connection management unit, which is used in computer bus communication in which packets are transmitted between a request source and a request destination, has a dummy return packet generation/transmission function wherein a dummy return packet is generated and is transmitted to the request source when a delay or loss occurs in a return packet transmitted from the request destination, and/or a filter function wherein, after transmission of the dummy return packet, a legitimate return packet arriving from the request destination is discarded.

Abstract: An integrated-circuit device comprises a source register in a reset domain, a destination circuit outside the reset domain, and a reset checking circuit. The checking circuit comprises a buffer outside the reset domain for receiving data values output by the source register, a reset detector, and reset checking logic. The checking logic detects a new data value output by the source register, checks whether a reset of the reset domain has been detected, and contingently outputs a control signal for controlling whether the destination circuit receives the new data value from the buffer. The reset detector signals whether a reset has been detected by using a feedback path to hold a predetermined value in a resettable latch until the latch receives a reset signal, and to hold a different value in the latch after receiving a reset signal.

Abstract: A device, includes an instruction buffer. The instruction buffer is configured to store instructions related to at least a portion of a data stream to be analyzed by a state machine engine as the device. The state machine engine includes configurable elements configured to analyze the at least a portion of a data stream and to selectively output the result of the analysis. Additionally, the instruction buffer is configured to receive the indications as part of a direct memory access (DMA) transfer.

Abstract: A database query message may be received at a database system via a network. The database query message may include one or more parameters for retrieving data from a database based on a designated database record insertion timestamp. A database query may be executed against the database system to retrieve one or more database records based on a database record insertion timestamp range determined based on the designated database record insertion timestamp and including a plurality of database record insertion timestamp values.

Abstract: A data processing system for providing a distributed timer implements receiving a first timer message associated with a first computing device requesting creation of a first timer having a first duration and a first timer identifier; responsive to the first timer message creating a first timer, and inserting a first timer queue entry into a first timer queue associated with a first timer wait interval; receiving a plurality of second timer messages to reset the first timer; inserting a plurality of second timer queue entries into the first timer queue based on the plurality of second timer messages; and processing timer queue entries in the first timer queue responsive to the first timer wait interval having passed.

Abstract: An object of the present disclosure is to determine whether or not communication between ECUs after update of a software program is expected communication. A vehicular communication system includes: a storage unit which stores a first piece of information indicating data scheduled to be transmitted and received on a bus connecting a plurality of ECUs so that the ECUs can communicate with one another; an acquiring unit which acquires a second piece of information indicating data being transmitted and received on the bus when a software program of at least one of the plurality of ECUs is updated; and a determining unit which determines whether or not expected communication is being executed on the bus based on the first piece of information and the second piece of information.

Abstract: A computing system and platform includes an event subsample processor and a risk item subsample processor to generate approximations when undertaking processing to model complex events in order to minimize CPU, memory and storage overhead. The event subsample processor approximates values associated with events based on a measure of the importance of select events; the risk item subsample processor groups similar event/risk item pairs and approximates values using representatives from each group.

Abstract: An image forming apparatus includes a display unit with a power saving function, where the display unit is turned off after a predetermined period of time has elapsed to save power. If however, the display unit is displaying a code used by external devices to establish communication with the image forming apparatus, the power saving function is disabled during the time period the code is being displayed.

Abstract: Embodiments of the present disclosure disclose a method and an apparatus for testing a code file. A preferred embodiment of the method comprises: compiling a to-be-tested code file to obtain an intermediate code file; instrumenting a code block identifier of each code block in the intermediate code file to the intermediate code file; determining an identifier of a jump relationship between two code blocks that have the jump relationship in the intermediate code file; performing dynamic testing to the instrumented intermediate code file based on respective code block identifiers and respective identifiers of jump relationships. This embodiment enhances bug detection capabilities for testing a code file.

Abstract: Exposing a leap second to a plurality of applications includes identifying that a positive leap second should be added to the end of a chosen date. Based on the occurrence of the positive leap second, a first conversion component is exposed to a first application. The first conversion component presents, over a period of two seconds of actual time, a last second of the chosen date as if it is one second of system time. Based on the occurrence of the positive leap second, and based on a second application opting in to leap seconds, a second conversion component is exposed to the second application. The second conversion component presents an extra 61st second of system time at the end of a last minute of the chosen date.

Abstract: There is provided a transmission apparatus including a clock signal generator that generates a clock signal and a transmitter that operates on the basis of the clock signal and transmits data in which the clock signal is embedded or a synchronization signal for maintaining CDR synchronization, in which during a period of data transmission, the clock signal generator generates a first clock signal for data transmission and the transmitter transmits data in which the first clock signal is embedded on the basis of the first clock signal, and during a pause period of data transmission, the clock signal generator generates a second clock signal having a frequency lower than that of the first clock signal and the transmitter transmits the synchronization signal on the basis of the second clock signal.

Abstract: Timer management techniques are described. An example processing device includes a memory configured to store successive wheels available to be included in traversal paths for timers running on the device, each wheel representing a queue of timers, each wheel having a different, corresponding time delay (TO) value for queuing a timer, and processing circuitry in communication with the memory. The processing circuitry is configured to determine, in response to a request for a timer, a total traversal time for the timer, to select, from the stored wheels, a subset of wheels such that a sum of the respective TO values of the selected subset is within a predetermined margin of error with respect to the total traversal time for the timer, and to sequence the selected subset of wheels based on the respective TO values of the selected subset of wheels to form a traversal path for the timer.

Abstract: A convenience gaming system is provided. The convenience gaming system allows users to access applications via gaming communication devices coupled to a communication network. At least a portion of the network may be wireless. The gaming applications include gambling, financial, entertainment service, and other types of transactions. The system may include a user location determination feature to prevent users from conducting transactions from unauthorized areas.

Abstract: In one or more embodiments, one or more systems, methods, and/or processes may start a single threaded power on self test process without a periodic handler to communicate with a watchdog timer of an information handling system; may initialize the watchdog timer with an amount of time; may store the amount of time and watchdog timer access interface information via a memory medium of the information handling system; may, after storing the amount of time and the watchdog timer access interface information, boot an operating system; may provide information indicating a location of the amount of time and the watchdog timer access interface information to the operating system; and may periodically reset the watchdog timer via a device driver of the operating system.

Abstract: A system, method and method for verifying a location of a mobile device by providing instructions to a user of the mobile device to physically manipulate the mobile device, and determining whether the mobile device was, in fact, physically manipulated according to the instructions.

Abstract: The present invention provides a sensing circuit, for sensing a working status of a real-time clock (RTC) module, comprising a comparator module, coupled to the real-time clock module, for receiving an initial voltage of the real-time clock module, and comparing the initial voltage with a threshold voltage, to generate a comparison result; and a storage module, coupled to the comparator module, for storing the comparison result and delivering the comparison result to a host circuit; wherein the host circuit determines whether the working status of the real-time clock module is normal or abnormal according to the comparison result.

Abstract: A differential message security policy includes receiving information regarding activities of a user, determining a security risk for the user based on the activities of the user, and setting a security policy for the user based on the security risk. The security policy of the user may be modified based on a change in the security risk of the user or the security risk of the user exceeding a predetermined level. The security risk may be determined based on an aggregated scoring system that uses security variables related to the activities of the user.

Abstract: Exposing a leap second to a plurality of applications includes identifying a system setting enabling leap second support and that a positive leap second should be added to the end of a chosen date. Based on the system setting enabling leap second support and based on the occurrence of the positive leap second, a first conversion component is exposed to a first application. The first conversion component presents, over a period of two seconds of actual time, a last second of the chosen date as if it is one second of system time. Based on the system setting enabling leap second support, based on the occurrence of the positive leap second, and based on a second application opting in to leap seconds, a second conversion component is exposed to the second application. The second conversion component presents an extra 61st second of system time at the end of a last minute of the chosen date.

Abstract: A hardware thread scheduler (HTS) is provided for a multiprocessor system. The HTS is configured to schedule processing of multiple threads of execution by resolving data dependencies between producer modules and consumer modules for each thread. Pattern adaptors may be provided in the scheduler that allows mixing of multiple data patterns across blocks of data. Transaction aggregators may be provided that allow re-using the same image data by multiple threads of execution while the image date remains in a given data buffer. Bandwidth control may be provided using programmable delays on initiation of thread execution. Failure and hang detection may be provided using multiple watchdog timers.

Abstract: At least one processor core has debug and non-debug modes of operation. Debug control circuitry controls operation of the at least one processor core when in the debug mode. On power up of a given processor core, the core checks a debug status value stored in a debug status storage element. When the debug status value has a first value, a debug connect sequence of messages is exchanged with the debug control circuitry over a debug interface to determine whether the given processor core should operate in the debug mode or the non-debug mode, and the debug status value is set to a second value when it is determined that the given processor core should operate in the non-debug mode. When the debug status value has the second value, the given processor core omits initiating the debug connect sequence and determines that it should operate in the non-debug mode.

Abstract: A noise cancelling circuit includes: a first parallel-serial conversion circuit which converts inputted 2N-bit parallel data into serial data; an inverting circuit which inverts one of odd-numbered bits and even-numbered bits included in the inputted 2N-bit parallel data; a second parallel-serial conversion circuit which converts, into serial data, parallel data outputted by the inverting circuit and parallel data of the other one of the odd-numbered bits and the even-numbered bits included in the inputted 2N-bit parallel data which were not inverted; a first buffer which receives output data of the first parallel-serial conversion circuit; and a second buffer which receives output data of the second parallel-serial conversion circuit.

Abstract: A cryptographic application-specific integrated circuit (ASIC) and method for autonomously storing context data into a one-time programmable memory in isolation are presented. The stored data describes product environmental history following manufacture, which may assist in assessing of a request for a refund or replacement of a defective product, such as an ASIC. The data may be cryptographically protected for retrieval and validation only by a manufacturer or authorized vendor. In another embodiment, communications between individual integrated circuits in a product may be secured by storing encryption keys as the context data, and exchanging the context data. The context data may be stored during manufacture, or thereafter.

Abstract: An apparatus and method for mapping timer channels to protection groups. One embodiment of the method can be implemented in a microcontroller unit (MCU) that comprises a central processing unit (CPU) coupled to a plurality of timer channels and a plurality of programmable group output disable (PTGOD) circuits. The CPU can select a first group of the timer channels to respond to an assertion of a first output disable signal from a first of the PTGOD circuits. Each timer channel of the first group can disable an output signal in response to receiving the assertion of the first output disable signal.

Abstract: The disclosure generally relates to dynamic clock and voltage scaling (DCVS) based on program phase. For example, during each program phase, a first hardware counter may count each cycle where a dispatch stall occurs and an oldest instruction in a load queue is a last-level cache miss, a second hardware counter may count total cycles, and a third hardware counter may count committed instructions. Accordingly, a software/firmware mechanism may read the various hardware counters once the committed instruction counter reaches a threshold value and divide a value of the first hardware counter by a value of the second hardware counter to measure a stall fraction during a current program execution phase. The measured stall fraction can then be used to predict a stall fraction in a next program execution phase such that optimal voltage and frequency settings can be applied in the next phase based on the predicted stall fraction.

Abstract: Methods, systems and computer program products for measuring hardware performance are provided. Aspects include receiving an indication of a start to a hardware operation. A number of clock cycles are counted from the start of a hardware operation to the completion of the hardware operation. A first region comprising a first set of bit location is defined. A second and third region is defined each including a set of bit locations. Based on the first set of bit locations being equal to zero, a granularity flag is set to zero in the sample buffer and the second and third set of bit locations are written to the sample buffer. And based on the first set of bit locations being greater than zero, the granularity flag in the sample buffer is set to one and the first and second set of bit locations are written to the sample buffer.

Abstract: A method and information handling system (IHS) converts a globally unique identifier to an electronic data interchange document identifier. The method includes receiving a globally unique identifier and converting the globally unique identifier into 128 binary bits. The 128 binary bits are selectively separated to form groups of bits that translate to integers. Each integer is replaced with an assigned alphanumeric character selected from an alphanumeric character map to form an encoded alphanumeric string of characters for use as an electronic data interchange document identifier.

Abstract: A system provides virtual per-processor timers based on a timer such as a platform timer. To virtualize a timer to be used by each processor independently, a data structure is maintained in memory for the timer. The data structure has an entry for each interrupt to be produced for each processor using the timer, specifying the processor and the due time, with the entries sorted by due time. If the virtualized timer is a platform timer that maintains context during power transitions, a processor can switch to the virtual per-processor timer upon a context-losing power transition.

Abstract: Techniques are disclosed for coalescing timer ticks generated by timers used to service guest operating systems executing in virtual machines. By coalescing timer ticks a logical processor can enter a low power mode thereby reducing power consumed by the system.

Abstract: In order to increase test coverage of integrated circuits with multiple clock domains, during a capture portion of a scan test, the functional clock signals, associated with a respective one of the clock domains are synchronized to ensure back and forth capture between the faster and slower clock domain. Each of the plurality of clock signals is generated such that an active edge of each faster clock signal occurs one clock period of the faster clock signal before an active edge of each slower clock signal.

Abstract: Provided are approaches for software defect reporting. Specifically, one approach provides identifying a software defect; generating a software defect report, wherein the software defect report is generated in real-time as the software defect is identified during testing of the test case, wherein the software defect report is submitted by a testing entity to a software developer responsible for creating a software product having the software defect, and wherein the defect report contains information to identify the location of the software defect in the application code of the software product; determining if the software defect report information is complete; and if the software defect report information is not complete, the updating the defect report information, determining if the software defect is reproducible, and recreating the software defect in the case that the software defect is reproducible.

Abstract: For generating timer data, a processor identifies a timer command from a command signal from an input device. The processor further identifies a timer interval and timer characteristics from the timer command. In addition, the processor generates timer data comprising a timer tag from the timer characteristics and the timer interval.

Abstract: A device, includes an instruction buffer. The instruction buffer is configured to store instructions related to at least a portion of a data stream to be analyzed by a state machine engine as the device. The state machine engine includes configurable elements configured to analyze the at least a portion of a data stream and to selectively output the result of the analysis. Additionally, the instruction buffer is configured to receive the indications as part of a direct memory access (DMA) transfer.

Abstract: The disclosure provides a method, a checking device and a system for determining security of a processor. The method comprises: setting an initial running state of the checking device according to initial running state information of the processor during the target running process, and taking input information of the processor during the target running process as input information of the checking device; causing the checking device to execute a task of the target running process in a manner conforming to predefined behavior to obtain at least one of output information and final running state information of the checking device, wherein the predefined behavior is a standard of hardware behavior of the processor; and determining whether the processor is secure during the target running process according to at least one of the output information and the final running state information of the checking device when the checking device completes the task of the target running process.

Abstract: A technique for providing environmental impact information associated with code includes determining, based on execution of the code on a computer system, an environmental impact of a code execution sequence included in the code. A section of the code that is associated with the code execution sequence is then annotated with environmental impact information associated with the environmental impact of the code execution sequence.

Abstract: An apparatus and method for a power-efficient framework to maintain data synchronization of a mobile personal computer (MPC) are described. In one embodiment, the method includes the detection of a data synchronization wakeup event while the MPC is operating according to a sleep state. Subsequent to wakeup event, at least one system resource is disabled to provide a minimum number of system resources required to re-establish a network connection. In one embodiment, user data from a network server is synchronized on the MPC without user intervention; the mobile platform system resumes operation according to the sleep state. In one embodiment, a wakeup alarm is programmed according to a user history profile regarding received e-mails. In a further embodiment, data synchronizing involves disabling a display, and throttling the system processor to operate at a reduced frequency. Other embodiments are described and claimed.

Abstract: A fault-tolerant distributed real-time computer system for controlling a physical system, in particular a machine or a motor vehicle, wherein the components of the computer system have access to a global time of known precision, and wherein the node computers and intelligent sensors and the intelligent actuators exchange time-triggered messages and event-triggered messages periodically via the distributor units, and wherein the functions of the user software are contained in real-time software components—RTSC—and the periodic time-triggered data transfer between the RTSC is specified by a time-triggered data flow diagram, and wherein the assignment of the RTSC to a TTVM of a node computer and specific parameters of the TTVM are contained in active local allocation plans for each RTSC, and wherein the time plans for the time-triggered communication in this distributor unit are contained in active local allocation plans for each distributor unit, and wherein a global allocation plan consists of the totality of

Abstract: An interrupt interface of a central processing unit (CPU) comprises a bus with a plurality of interfaces to various components of the CPU. These components can include a memory that includes instructions to execute operations of a processor component, a plurality of virtual machines (VMs) and a virtual machine monitor (VMM)/hypervisor configured to execute the plurality of VMs. The processor can receive interrupt requests (interrupt) as service requests in parallel, which can be executed by the VMM or any one or more of the plurality of VMs to execute VM applications on a dedicated instance of a guest operating system for a task. The processor can further determine whether to grant an interrupt request to the VMM and the VMs based on predetermined criteria, including a current task priority, a pending interrupt priority, or an interrupt enable, associated with the current status of each of the component.

Abstract: In one embodiment, a method includes continuously receiving time-series data for end-user transactions occurring on one or more monitored systems. The method further includes continuously processing and storing the time-series data in a plurality of virtual machines. In addition, the method includes, responsive to a determined time-series-data burst, spawning one or more temporary virtual machines. Moreover, the method includes, during the determined time-series-data burst, continuously processing and storing the time-series data in the plurality of virtual machines and in the one or more temporary virtual machines. The method also includes, responsive to a determined conclusion of the determined time-series-data burst, causing the one or more temporary virtual machines to transition to a passive state in which the one or more temporary virtual machines cease processing and storing new time-series data but make previously-stored time-series data available for access.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for a watermark-based message queue. One of the methods includes receiving a first connection request for messages associated with a user device. A first connection session is established with the user device. A message queue of messages associated with the user device is identified, each message in the message queue is associated with a respective timestamp, and the message queue is associated with a current watermark that identifies a first timestamp. An oldest message in the message queue at the time the first connection session was established is identified. An updated watermark that identifies a second timestamp associated with the oldest message is associated with the message queue. One or more messages that have a timestamp newer than or equal to the first timestamp identified by the current watermark is provided to the user device.

Abstract: A system and method for securely recording voice communications, comprising an authentication server, further comprising at least a software components operating on a network-capable computing device, and a database, wherein an authentication server verifies the validity of voice communications and a database stores voice communication recordings.

Abstract: A more efficient mobile device can be achieved via an optimization process based on display screen dormancy. Application data transmissions can be throttled based on a screen-on or screen-off status of a mobile device. Furthermore, an application management platform can be used to prioritize application data transmissions based on data associated with each application's packet transmissions.

Abstract: A method for firmware debug trace capture includes creating a hand-off block (“HOB”), capturing first debug trace statements during a boot sequence of a computer and writing the first debug trace statements to the HOB. A trace memory buffer can be created and the first debug trace statements can be copied from the HOB to the trace memory buffer. Second debug trace statements are captured during the boot sequence and appended to the trace memory buffer. In some configurations, the first debug trace statements can be written to the HOB during the pre-Extensible Firmware Interface initialization (“PEI”) phase of the boot sequence and the second debug trace statements can be written to the trace memory buffer during the driver execution (“DXE”) phase of the boot sequence.

Abstract: The present invention addresses the deficiencies of the art in respect to data security control and provides a method, system and computer program product for securing confidential data through transient on-demand data security control. In one embodiment of the invention, a method of securing confidential data can be provided. The method can include decrypting confidential data in a document, determining a subset of the confidential data specified by an author of the document, rendering a view of the confidential data including the subset, and, in response to detecting when an authorized viewer of the document no longer views the document, concealing the subset of the confidential data while maintaining a view of the confidential data not included in the subset.