Abstract: A method for determining a sense boundary of a sense amplifier includes: writing the same data into the memory cells controlled by at least a pair of first word line on the left side and second word line on the right side corresponding to the sense amplifier; activating the first word line and precharging bit lines corresponding to the first word line; reading the data in the memory cells controlled by the corresponding second word line after a preset row precharge time; and determining a corresponding critical row precharge time as a row precharge time boundary value when the sense amplifier does not correctly read the data in the memory cells controlled by the second word line.

Abstract: Systems and methods of fallback electronic communications are disclosed. A system is configured to receive a communication campaign including data identifying at least one communication channel and implement a fallback state machine having a first composite state corresponding to the at least one communication channel. An initial electronic communication is transmitted via the at least one communication channel and an initial timer having a first predetermined timeout period is implemented. When a confirmation is received prior to expiration of the initial timer, the fallback state machine transitions to a complete state. When the confirmation is not received prior to expiration of the initial timer, a first composite fallback state corresponding to a first set of fallback communication channels is implemented and a first fallback electronic communication is transmitted via the first set of fallback communication channels.

Abstract: Embodiments protect computer applications from code injection attacks. An example embodiment includes a runtime memory protection (RMP) user endpoint agent and an RMP kernel driver component. The RMP user endpoint agent receives, from the RMP kernel driver component, representations of events occurring with respect to memory locations associated with a computer application and processes the received representations to determine if a given event includes at least one of a memory permissions change request, a memory write request, and a thread create request. If the given event is determined to include at least one of a memory permissions change request, a memory write request, and a thread create request, the RMP user endpoint agent declares a code injection attack and sends an alarm indication to the RMP kernel driver component. In response to receiving the alarm indication, the RMP kernel driver component implements a protection action.

Abstract: A device, includes an instruction buffer. The instruction buffer is configured to store instructions related to at least a portion of a data stream to be analyzed by a state machine engine as the device. The state machine engine includes configurable elements configured to analyze the at least a portion of a data stream and to selectively output the result of the analysis. Additionally, the instruction buffer is configured to receive the indications as part of a direct memory access (DMA) transfer.

Abstract: A multi-tile processing unit in which the tiles in the processing unit may be divided between two or more different external sync groups for performing barrier synchronisations. In this way, different sets of tiles of the same processing unit each sync with different sets of tiles external to that processing unit.

Abstract: A message broker resource monitoring service obtains message broker resource parameter data of a resource, based on communications of a message broker. Based on the resource parameter data and historical data, the message broker resource monitoring service obtains a predicted message delivery time value, which can be in association with confidence. If the predicted message delivery time value satisfies a resource deletion criterion, e.g., the predicted message delivery time value, with sufficient confidence, exceeds a threshold value, the message broker resource monitoring service triggers an action to delete the resource. To obtain the predicted value, a regression such as symmetric conformal quantile regression can be applied to the parameter data, e.g., to obtain a predicted message delivery time/latency value.

Abstract: A voltage regulator is embedded in a circuit intermediate a first node (coupled to a battery) and a second node (supplying power to an external memory). The voltage regulator is activatable in a first mode of operation for startup during which an voltage is applied to the second node that increases towards a supply threshold. In response to the voltage at the second node reaching the supply threshold, the voltage regulator transitions to a second mode of operation where a programmable regulated voltage (higher than the supply threshold) is applied to the second node. In response to receipt of a low-power operation request, a first high-drive regulator circuitry is deactivated and a second low-power regulator circuitry is activated to provide a third mode of operation at low power.

Abstract: A computing device selects new test configurations for testing software. (A) First test configurations are generated using a random seed value. (B) Software under test is executed with the first test configurations to generate a test result for each. (C) Second test configurations are generated from the first test configurations and the test results generated for each. (D) The software under test is executed with the second test configurations to generate the test result for each. (E) When a restart is triggered based on a distance metric value computed between the second test configurations, a next random seed value is selected as the random seed value and (A) through (E) are repeated. (F) When the restart is not triggered, (C) through (F) are repeated until a stop criterion is satisfied. (G) When the stop criterion is satisfied, the test result is output for each test configuration.

Abstract: A method for managing a remote service standby time of a connected car includes: notifying, by a connected car service (CCS) center which provides a remote service on a connected car, a customer terminal that a remote service standby mode needs to be ended; setting the remote service standby mode through a CCS application installed in the customer terminal; checking, by a CCS terminal installed in the connected car, whether a time to start the end of the remote service standby mode in accordance of the setting of the remote service standby mode has come; and, when the time to start the end of the remote service standby mode has come, requesting, by the CCS terminal, a shut-down of a modem installed in the connected car, and can efficiently manage the remote service standby time of the connected car.

Abstract: A media stream sending method, apparatus, and system includes a proxy server that receives a first live broadcast room request message and a second live broadcast room request message that are sent by a same proxy client; the proxy server receives a first live media stream that is sent by a media server to a first client and a second live media stream that is sent by the media server to a second client; and when a role of the first client is a master user and a role of the second client is a slave user, the proxy server sends the first live media stream to the proxy client such that the proxy client sends the first live media stream to the first client and the second client.

Abstract: A plurality of scanned backup snapshots are generated. A backup snapshot among a plurality of backup snapshots is selected. At least a portion of the selected backup snapshot is restored in a temporary environment to create a restored instance of at least the portion of the selected backup snapshot. A vulnerability scan of the restored instance of at least the portion of the selected backup snapshot is performed. One or more vulnerabilities of the scanned portion of the selected backup snapshot are tracked. A request associated with identifying a scanned backup snapshot to restore from the plurality of scanned backup snapshots is received. In response to the request, at least a predetermined identification of the one or more vulnerabilities of the selected backup snapshot is provided.

Abstract: The present invention provides a DP-out adapter including a decoder, a clock signal generating circuit, a DP signal generating circuit and a symbol counter value comparator. The decoder is configured to decode a USB signal to generate a plurality of packets. The clock signal generating circuit is configured to generate a clock signal. The DP signal generating circuit is configured to generate a DP signal according to the packets, and output the DP signal according to the clock signal. The symbol counter value comparator is configured to generate a first counter value according to a number of symbols corresponding to the plurality of packets, and use the clock signal to count to obtain a second counter value, and compare the first counter value and the second counter value to generate a control signal to the clock signal generating circuit to adjust a frequency of the clock signal.

Abstract: Metadata sizes for data objects in cloud storage systems can be reduced. For example, a computing system can receive, at a client device of a cloud storage system, a first object identifier associated with a data object in the cloud storage system. The computing system can use a reduction function to generate a second object identifier associated with the data object. The second object identifier can have a smaller byte size than the first object identifier. The computing system can transmit, to a server of the cloud storage system, the second object identifier to be stored in metadata associated with the data object in the cloud storage system.

Abstract: A system for composing browser-based applications is enhanced with cross-tab communication capability. At design time, responsive to a configuration instruction from a user, the system configures a user interface (UI) event for a browser-based application such that the UI event is publishable across all open browser tabs at application runtime. Responsive to a publication instruction from the user, the system configures a first application page to generate the UI event at application runtime in response to a trigger and to publish the UI event to browser local storage. Responsive to a subscription instruction from the user, the system configures a second application page to periodically poll the browser local storage for the user interface event at application runtime and, in response to the UI event published by the first application page to the browser local storage, process the UI event and automatically immediately update the second application page.

Abstract: An information processing apparatus, an information processing system, and an information processing method.

Abstract: C-state transitions due to software timer interrupts can be minimized. A timer interrupt synchronizer can be deployed on a computing device to function as an intermediary between software components that rely on timer interrupts and a timer interrupt architecture of the computing device. When the software components request timer interrupts, the timer interrupt synchronizer can ensure that timer interrupts having the same frequency can be synchronized to occur at the same time. As a result of this synchronization, a CPU can experience fewer C-state transitions due to the timer interrupts.

Abstract: Described are mechanisms and methods for applying Machine Learning (ML) techniques for power management at different levels of a power management stack. An apparatus may comprise a first circuitry, a second circuitry, and a third circuitry. The first circuitry may have a plurality of memory registers. The second circuitry may be operable to establish values for a plurality of features based on samples of values of the plurality of memory registers taken at one or more times within a range of time of predetermined length. The third circuitry may be operable to compare the plurality of features against a plurality of learned parameters for a reference workload.

Abstract: A method and system for analysis of a facility may include providing an emulation host system, first generating a golden circuit model on the emulation host system, first inserting a first hardware trojan model, first emulating operation of the golden circuit model, and second emulating operation of the first hardware trojan model. A facility may include a trojan instrument facility having a trojan detection instrument comparing logic circuit output against a threshold for detecting hardware trojan activity, and outputting alert data, and in relation to opening one of a plurality of scannable access points, a scannable register is inserted into an active scan chain with an associated instrument interface.

Abstract: The present disclosure relates to a method comprising receiving edges conveyed by a serial bus and separated by multiples of a same duration, determining a measurement value of a ratio between a cycle time of a clock and the duration, and sending bits on the serial bus using the measurement value.

Abstract: A communication control device configured to access an information processing apparatus in which data is stored. The device and method acquires an operational condition of an information processing apparatus, and notifies the information processing apparatus of a security command for causing the information processing apparatus to execute a security process on the data in an event that an operational condition is activated and, in an event that the operational condition is a standby mode, a hibernate mode, or a shutdown mode, notifies the information processing apparatus of an activation command for activating the information processing apparatus, and notifies of a security command for causing the information processing apparatus to execute a security process on the data.

Abstract: A network system includes at least one transmission path and a plurality of terminal devices each connected to the transmission path. Each of the terminal devices includes a transceiver, a startup processing unit, and a switching unit. The transceiver is configured to operate either one of a first standby unit and a second standby unit according to a switching instruction. The switching unit is configured to output the switching instruction to the transceiver to operate the second standby unit when a transmission path empty period lasts for a predetermined preparation time or more after a non-designation period has lasted for a predetermined operation determination time or more.

Abstract: A system and method for securely recording voice communications, comprising a network-connected computer server and an authentication system which verifies the validity of voice communications.

Abstract: Techniques to more readily identify issues that arise in connection with memory systems and streamline the analysis process. A detailed activity log is generate with corresponding start and stop traffic events to facilitate identification of problems in memory devices. Each event registered in the log includes numerous items of information. The information facilitates identifying the origin of a particular problem including when and where it occurred, thus making failure analysis (FA) both easier and faster.

Abstract: A processor with reduced interrupt latency is disclosed. An apparatus includes a processor core and a cache subsystem having a cache controller and a cache. The processor core is configured to submit, to the cache controller, requests for access to the cache, wherein a given request for access to the cache specifies whether the given request is abandonable or non-abandonable in an event of an interrupt request. In response to a particular interrupt request, the processor core may provide an indication to cause the cache controller to abandon requests for access to the cache identified as abandonable. After receiving an acknowledgement from the cache controller that the abandonable requests have been abandoned, the processor core may begin execution of an interrupt handler in order to service the interrupt request.

Abstract: A non-transitory computer-readable storage medium storing a program that causes a computer to execute a process, the process includes acquiring first multiple tasks; dividing each task in the first multiple tasks in accordance with a cache size; classifying second multiple tasks in accordance with a range of data to be referred to at a time of execution of each task in the second multiple tasks that have been obtained by the dividing; and determining an execution order of tasks in a group for each group that has been obtained by the classifying.

Abstract: A packet backpressure detection method and apparatus are provided. The method includes: a device which having a Peripheral Component Interconnect Express (PCIe) port storing a plurality of packets for transmission in a packet queue and storing a packet that is to be transmitted next in a first buffer, where the queue comprises a plurality of packets that are to be transmitted via the PCIe port; and the queue is stored in a second buffer; recording a storage duration of each packet stored in the first buffer, and accumulating the storage duration of each packet stored in the first buffer; removing the packet from the first buffer after the packet is transmitted via the PCIe port; and generating an indication of packet pressure at the PCIe port based on the accumulated storage duration.

Abstract: Countermeasures against fault injection attacks of a cryptographic integrated circuit, and more specifically laser fault injection attacks are provided. The invention consists in generating sequences of bits belonging to a set of allowed sequences, and storing these sequences on a set of Flip-Flops. Then the sequences stored on the Flip-Flops are checked and, if they do not belong to the allowed sequence, this is the sign that a fault injection attack occurred and caused a bit flip in one of the flip-flops. An alarm signal is then generated.

Abstract: A storage system and method for time-duration-based efficient block management and memory access are provided. In one embodiment, a controller of the storage system is configured to receive time stamps from a host for each of a plurality of blocks in the memory; determine a time duration for programming each of the plurality of blocks based on the time stamps; and differentiate the plurality of blocks based on the time durations. Other embodiments are provided.

Abstract: Disclosed is a power supply enable circuit. The power supply enable circuit includes a multi-input NAND gate, input terminals of the multi-input NAND gate respectively connected to a plurality of activation signal sources; and a delay circuit, an input terminal of the delay circuit electrically connected to a shared activation signal source of the plurality of activation signal sources. An output terminal of the delay circuit is electrically connected to an enable input terminal of a power supply circuit after performing a logical AND with an output terminal of the multi-input NAND gate.

Abstract: Provided are a connection management mechanism and a connection management method with which computer bus connections can be managed such that failures and freezes do not occur in a computer system when delays and packet losses occur. A connection management unit, which is used in computer bus communication in which packets are transmitted between a request source and a request destination, has a dummy return packet generation/transmission function wherein a dummy return packet is generated and is transmitted to the request source when a delay or loss occurs in a return packet transmitted from the request destination, and/or a filter function wherein, after transmission of the dummy return packet, a legitimate return packet arriving from the request destination is discarded.

Abstract: An integrated-circuit device comprises a source register in a reset domain, a destination circuit outside the reset domain, and a reset checking circuit. The checking circuit comprises a buffer outside the reset domain for receiving data values output by the source register, a reset detector, and reset checking logic. The checking logic detects a new data value output by the source register, checks whether a reset of the reset domain has been detected, and contingently outputs a control signal for controlling whether the destination circuit receives the new data value from the buffer. The reset detector signals whether a reset has been detected by using a feedback path to hold a predetermined value in a resettable latch until the latch receives a reset signal, and to hold a different value in the latch after receiving a reset signal.

Abstract: A device, includes an instruction buffer. The instruction buffer is configured to store instructions related to at least a portion of a data stream to be analyzed by a state machine engine as the device. The state machine engine includes configurable elements configured to analyze the at least a portion of a data stream and to selectively output the result of the analysis. Additionally, the instruction buffer is configured to receive the indications as part of a direct memory access (DMA) transfer.

Abstract: A database query message may be received at a database system via a network. The database query message may include one or more parameters for retrieving data from a database based on a designated database record insertion timestamp. A database query may be executed against the database system to retrieve one or more database records based on a database record insertion timestamp range determined based on the designated database record insertion timestamp and including a plurality of database record insertion timestamp values.

Abstract: A data processing system for providing a distributed timer implements receiving a first timer message associated with a first computing device requesting creation of a first timer having a first duration and a first timer identifier; responsive to the first timer message creating a first timer, and inserting a first timer queue entry into a first timer queue associated with a first timer wait interval; receiving a plurality of second timer messages to reset the first timer; inserting a plurality of second timer queue entries into the first timer queue based on the plurality of second timer messages; and processing timer queue entries in the first timer queue responsive to the first timer wait interval having passed.

Abstract: An object of the present disclosure is to determine whether or not communication between ECUs after update of a software program is expected communication. A vehicular communication system includes: a storage unit which stores a first piece of information indicating data scheduled to be transmitted and received on a bus connecting a plurality of ECUs so that the ECUs can communicate with one another; an acquiring unit which acquires a second piece of information indicating data being transmitted and received on the bus when a software program of at least one of the plurality of ECUs is updated; and a determining unit which determines whether or not expected communication is being executed on the bus based on the first piece of information and the second piece of information.

Abstract: A computing system and platform includes an event subsample processor and a risk item subsample processor to generate approximations when undertaking processing to model complex events in order to minimize CPU, memory and storage overhead. The event subsample processor approximates values associated with events based on a measure of the importance of select events; the risk item subsample processor groups similar event/risk item pairs and approximates values using representatives from each group.

Abstract: An image forming apparatus includes a display unit with a power saving function, where the display unit is turned off after a predetermined period of time has elapsed to save power. If however, the display unit is displaying a code used by external devices to establish communication with the image forming apparatus, the power saving function is disabled during the time period the code is being displayed.

Abstract: Embodiments of the present disclosure disclose a method and an apparatus for testing a code file. A preferred embodiment of the method comprises: compiling a to-be-tested code file to obtain an intermediate code file; instrumenting a code block identifier of each code block in the intermediate code file to the intermediate code file; determining an identifier of a jump relationship between two code blocks that have the jump relationship in the intermediate code file; performing dynamic testing to the instrumented intermediate code file based on respective code block identifiers and respective identifiers of jump relationships. This embodiment enhances bug detection capabilities for testing a code file.

Abstract: Exposing a leap second to a plurality of applications includes identifying that a positive leap second should be added to the end of a chosen date. Based on the occurrence of the positive leap second, a first conversion component is exposed to a first application. The first conversion component presents, over a period of two seconds of actual time, a last second of the chosen date as if it is one second of system time. Based on the occurrence of the positive leap second, and based on a second application opting in to leap seconds, a second conversion component is exposed to the second application. The second conversion component presents an extra 61st second of system time at the end of a last minute of the chosen date.

Abstract: Timer management techniques are described. An example processing device includes a memory configured to store successive wheels available to be included in traversal paths for timers running on the device, each wheel representing a queue of timers, each wheel having a different, corresponding time delay (TO) value for queuing a timer, and processing circuitry in communication with the memory. The processing circuitry is configured to determine, in response to a request for a timer, a total traversal time for the timer, to select, from the stored wheels, a subset of wheels such that a sum of the respective TO values of the selected subset is within a predetermined margin of error with respect to the total traversal time for the timer, and to sequence the selected subset of wheels based on the respective TO values of the selected subset of wheels to form a traversal path for the timer.

Abstract: There is provided a transmission apparatus including a clock signal generator that generates a clock signal and a transmitter that operates on the basis of the clock signal and transmits data in which the clock signal is embedded or a synchronization signal for maintaining CDR synchronization, in which during a period of data transmission, the clock signal generator generates a first clock signal for data transmission and the transmitter transmits data in which the first clock signal is embedded on the basis of the first clock signal, and during a pause period of data transmission, the clock signal generator generates a second clock signal having a frequency lower than that of the first clock signal and the transmitter transmits the synchronization signal on the basis of the second clock signal.

Abstract: A convenience gaming system is provided. The convenience gaming system allows users to access applications via gaming communication devices coupled to a communication network. At least a portion of the network may be wireless. The gaming applications include gambling, financial, entertainment service, and other types of transactions. The system may include a user location determination feature to prevent users from conducting transactions from unauthorized areas.

Abstract: In one or more embodiments, one or more systems, methods, and/or processes may start a single threaded power on self test process without a periodic handler to communicate with a watchdog timer of an information handling system; may initialize the watchdog timer with an amount of time; may store the amount of time and watchdog timer access interface information via a memory medium of the information handling system; may, after storing the amount of time and the watchdog timer access interface information, boot an operating system; may provide information indicating a location of the amount of time and the watchdog timer access interface information to the operating system; and may periodically reset the watchdog timer via a device driver of the operating system.

Abstract: A system, method and method for verifying a location of a mobile device by providing instructions to a user of the mobile device to physically manipulate the mobile device, and determining whether the mobile device was, in fact, physically manipulated according to the instructions.

Abstract: The present invention provides a sensing circuit, for sensing a working status of a real-time clock (RTC) module, comprising a comparator module, coupled to the real-time clock module, for receiving an initial voltage of the real-time clock module, and comparing the initial voltage with a threshold voltage, to generate a comparison result; and a storage module, coupled to the comparator module, for storing the comparison result and delivering the comparison result to a host circuit; wherein the host circuit determines whether the working status of the real-time clock module is normal or abnormal according to the comparison result.

Abstract: Exposing a leap second to a plurality of applications includes identifying a system setting enabling leap second support and that a positive leap second should be added to the end of a chosen date. Based on the system setting enabling leap second support and based on the occurrence of the positive leap second, a first conversion component is exposed to a first application. The first conversion component presents, over a period of two seconds of actual time, a last second of the chosen date as if it is one second of system time. Based on the system setting enabling leap second support, based on the occurrence of the positive leap second, and based on a second application opting in to leap seconds, a second conversion component is exposed to the second application. The second conversion component presents an extra 61st second of system time at the end of a last minute of the chosen date.

Abstract: A differential message security policy includes receiving information regarding activities of a user, determining a security risk for the user based on the activities of the user, and setting a security policy for the user based on the security risk. The security policy of the user may be modified based on a change in the security risk of the user or the security risk of the user exceeding a predetermined level. The security risk may be determined based on an aggregated scoring system that uses security variables related to the activities of the user.

Abstract: A hardware thread scheduler (HTS) is provided for a multiprocessor system. The HTS is configured to schedule processing of multiple threads of execution by resolving data dependencies between producer modules and consumer modules for each thread. Pattern adaptors may be provided in the scheduler that allows mixing of multiple data patterns across blocks of data. Transaction aggregators may be provided that allow re-using the same image data by multiple threads of execution while the image date remains in a given data buffer. Bandwidth control may be provided using programmable delays on initiation of thread execution. Failure and hang detection may be provided using multiple watchdog timers.

Abstract: At least one processor core has debug and non-debug modes of operation. Debug control circuitry controls operation of the at least one processor core when in the debug mode. On power up of a given processor core, the core checks a debug status value stored in a debug status storage element. When the debug status value has a first value, a debug connect sequence of messages is exchanged with the debug control circuitry over a debug interface to determine whether the given processor core should operate in the debug mode or the non-debug mode, and the debug status value is set to a second value when it is determined that the given processor core should operate in the non-debug mode. When the debug status value has the second value, the given processor core omits initiating the debug connect sequence and determines that it should operate in the non-debug mode.

Abstract: A noise cancelling circuit includes: a first parallel-serial conversion circuit which converts inputted 2N-bit parallel data into serial data; an inverting circuit which inverts one of odd-numbered bits and even-numbered bits included in the inputted 2N-bit parallel data; a second parallel-serial conversion circuit which converts, into serial data, parallel data outputted by the inverting circuit and parallel data of the other one of the odd-numbered bits and the even-numbered bits included in the inputted 2N-bit parallel data which were not inverted; a first buffer which receives output data of the first parallel-serial conversion circuit; and a second buffer which receives output data of the second parallel-serial conversion circuit.