Counting, Scheduling, Or Event Timing Patents (Class 713/502)
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Patent number: 8909973Abstract: A timer unit includes a first selector that receives a fixed value and a first enable signal, a second selector that receives the fixed value and a count cycle signal, a third selector that receives an output of the second selector, the count cycle signal, and a second enable signal, a first counter circuit that starts counting in response to an output of the first selector, and that generates the count cycle signal and a first counter circuit output signal indicating that a count value approaches a predetermined value, a second counter circuit that starts counting in response to an output of the third selector, and that generates a second counter circuit output signal, a first output signal generator that receives the first counter circuit output signal and the second counter circuit output signal to generate a first output signal, and a second output signal generator.Type: GrantFiled: January 4, 2012Date of Patent: December 9, 2014Assignee: Renesas Electronics CorporationInventor: Yasuhiro Takata
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Patent number: 8909974Abstract: A data processing apparatus comprising: a gate unit connected to an input or an output of a processing unit and configured to cut off the data input and output; a control unit configured to control a supply of clock to the processing unit; and an instruction unit configured to give an instruction for the clock control to the control unit, wherein the control unit controls the gate unit and controls the clock supplied to the processing unit based on an instruction from the instruction unit, whereby securing a higher power saving effect.Type: GrantFiled: December 9, 2011Date of Patent: December 9, 2014Assignee: Canon Kabushiki KaishaInventor: Kinya Osa
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Patent number: 8909824Abstract: This invention relates to techniques for managing the transmission and reception of data fragments that contains one or more data blocks. One embodiment of the invention includes the following steps: processing the fragments sequentially, wherein each fragment has a processing index that corresponds to sequential processing of that fragment; processing each of the fragments until a termination upon meeting at least one pre-defined condition; assigning a timer to an un-terminated fragment having a lowest processing index; starting said timer having a timeout value; and running said timer until the processing of said un-terminated fragment is terminated.Type: GrantFiled: February 25, 2013Date of Patent: December 9, 2014Inventors: Yalun Li, William Li, Jr.
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Patent number: 8903968Abstract: A distributed computing environment for executing applications in a degraded state during constrained resource availability.Type: GrantFiled: August 29, 2006Date of Patent: December 2, 2014Assignee: International Business Machines CorporationInventors: Christopher J. Dawson, Craig W. Fellenstein, Vincenzo V. Di Luoffo
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Patent number: 8904222Abstract: A watchdog timer includes an execution address detection section comparing a value of a program counter of a central processing unit with an address of a predetermined area, a timer count section having a first overflow time set thereto when the execution address detection section indicates that the value of the program counter has entered the predetermined area, and a counter clear control section generating a request signal for clearing the timer count section when the execution address detection section indicates that the value of the program counter has exited from the predetermined area.Type: GrantFiled: February 16, 2010Date of Patent: December 2, 2014Assignee: Renesas Electronics CorporationInventor: Hideo Isogai
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Publication number: 20140337658Abstract: A method includes reading first and second timer count values from a timer, wherein the first timer count value is associated with a first time point and the second timer count value is associated with a second time point, calculating a difference between the first and the second timer count values, and determining whether the difference is within a range, wherein the range is based on a desired executing frequency to perform a computing task, a variation of the desired executing frequency, and a timer frequency. Further, based on the difference not being within the range, the method includes setting an error flag value to be true and incrementing an error count value.Type: ApplicationFiled: May 7, 2014Publication date: November 13, 2014Inventor: David P. MAGEE
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Publication number: 20140331075Abstract: A time reference system includes a master clock, generating a clock reference, interface logic and a CPU-based subsystem. The interface logic receives the clock reference and generates the clock, pulses, and timestamp signals. The CPU-based subsystem includes an internal counter, a CPU and a clock synthesizer, the CPU and receiving the pulses and timestamp signals. The clock synthesizer receives the clock signal and generates a CPU clock signal. Some examples include an FPGA-based subsystem having an FPGA-based card coupled to the interface logic for receipt of the clock, pulses and timestamp signals. In a method the timestamp value TO is generated by the CPU upon receipt of the timestamp signal. Upon receipt by the CPU of the next pulse signal, a timestamp counter baseline value TSCO is generated so the CPU internal counter is calibrated to the clock signal.Type: ApplicationFiled: August 12, 2013Publication date: November 6, 2014Applicant: Spirent Communications, Inc.Inventors: John R. Morris, Thomas R. McBeath
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Patent number: 8880926Abstract: Control events may be signaled to a target system having a plurality of components coupled to a scan path by using the clock and data signals of the scan path. While the clock signal is held a high logic level, two or more edge transitions are detected on the data signal. The number of edge transitions on the data signal is counted while the clock signal is held at the high logic state. A control event is determined based on the counted number of edge transitions on the data signal after the clock signal transitions to the low logic state.Type: GrantFiled: August 12, 2013Date of Patent: November 4, 2014Assignee: Texas Instruments IncorporatedInventor: Gary L. Swoboda
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Patent number: 8880833Abstract: A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link interfaces to any of the memory controllers, a write buffer and read cache for each memory device and a read synchronization module. The read synchronization module includes a write pointer, a read pointer and a buffer. The write pointer is incremented in response to the receipt of read data. The read pointer increments in response to coupling of the read data from the memory hub. A comparator compares the read pointer an the write pointer, and the comparison is used to adjust the memory timing.Type: GrantFiled: March 4, 2013Date of Patent: November 4, 2014Assignee: Micron Technology, Inc.Inventors: Joseph M. Jeddeloh, Paul A. LaBerge
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Publication number: 20140317434Abstract: A distribution network, comprises: circuit blocks having counters, wherein the counters are synchronized relative to an input signal; drivers connected in a balanced tree for distributing the input signal synchronously to the circuit blocks; and drivers connected in an unbalanced tree for distributing a reset signal to the circuit blocks, wherein the input signal is distributed via the balanced tree as a function of the reset signal.Type: ApplicationFiled: January 31, 2014Publication date: October 23, 2014Applicant: Kool Chip, Inc.Inventors: Prasad Chalasani, Venkata N.S.N. Rao
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Publication number: 20140298074Abstract: A method of determining processor utilization includes: counting, via a first counter on a processor, a number of elapsed clock cycles while code is being executed; counting, via a second counter on a processor, a total number of free-running clock cycles; and dividing the number of clock cycles where code is being executed by the total number of free-running clock cycles to determine a CPU utilization.Type: ApplicationFiled: March 29, 2013Publication date: October 2, 2014Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLCInventors: Terry Murrell, Ray M. Ransom, Namal P. Kumara
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Publication number: 20140298073Abstract: Various embodiments enable on-demand scaling of a timer wheel. Some embodiments dynamically start and stop a timer wheel based, at least in part, on whether the timer wheel has any associated active timers. In some cases, the timer wheel is suspended when all associated active timers have been serviced. Alternately or additionally, the timer wheel is re-activated upon associating one or more active timers in need of service to the timer wheel. Various embodiments enable addition and removal of timer(s) to the timer wheel and/or various time slots associated with the timer wheel without using a global lock associated with the timer wheel.Type: ApplicationFiled: March 28, 2013Publication date: October 2, 2014Applicant: MICROSOFT CORPORATIONInventors: Ziyan Zhou, Ivan D. Pashov, Jonathan A. Silvera, Matthew R. Cox
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Publication number: 20140298049Abstract: A digital integrated circuit may include a digital data processing circuit having multiple signal lines that each go through signal transitions during operation of the digital data processing circuit. A digital counter circuit may count the combined number of signal transitions that take place on at least two of the multiple signal lines during operation of the digital circuit. A digital counter circuit may count the number of times a particular pattern of signal transitions takes place on at least one signal line during operation of the circuit. A computer program may receive information indicative of a composition of a digital integrated circuit, input vectors to the digital integrated circuit, and how much power is being consumed by the digital integrated circuit under each of the input vectors. The program may output information indicative of an amount of power being consumed by each of multiple, different sub-sections of the digital integrated circuit while responding to the input vectors.Type: ApplicationFiled: March 26, 2014Publication date: October 2, 2014Applicant: UNIVERSITY OF SOUTHERN CALIFORNIAInventors: Young H. Cho, Siddharth S. Bhargav, Andrew Goodney
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Publication number: 20140281659Abstract: An airborne, gas, or liquid particle sensor with one or more intelligent modules either within the instrument or attached to the instrument. These modules comprising sub-systems with local controllers or memory.Type: ApplicationFiled: March 15, 2014Publication date: September 18, 2014Applicant: Particles Plus, Inc.Inventor: David PARISEAU
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Publication number: 20140281658Abstract: Aspects of a low power memory buffer are described. In one embodiment, a sampling rate of a signal is adjusted to identify extrema of a signal. An extrema pulse is generated and, in response to the extrema pulse, a time segment and potential value of the signal are stored in a memory. In other aspects, rising and falling slopes of the signal are tracked to identify a local maximum and a local minimum of the signal. In this scenario, an extrema pulse is generated for each of the local maximum and minimum, and time segment and potential values are stored for the local maximum and minimum. Generally, the storage of analog values of the signal at an adjusted sampling rate is achieved with low power, and the signal may be reconstructed at a later time.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: WEST VIRGINIA UNIVERSITYInventor: West Virginia University
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Patent number: 8839018Abstract: An apparatus including a JTAG interface, synchronous bus optimizer, core clocks generator, synchronous strobe driver, and a DLL. The JTAG interface receives control information indicating a first amount to advance a synchronous data strobe associated with a first data group and a second amount to delay a data bit signal associated with a second data group. The synchronous bus optimizer receives the control information, and develops a first value on a first ratio bus that indicates the first amount and a second value on a second ratio bus that indicates the second amount. The core clocks generator advances a data strobe clock by the first amount. The synchronous strobe driver employs the data strobe clock to generate the synchronous data strobe, where the synchronous data strobe, when enabled, is advanced also by the first amount. The DLL generates a delayed data bit signal, delayed by the second amount.Type: GrantFiled: June 21, 2011Date of Patent: September 16, 2014Assignee: Via Technologies, Inc.Inventors: Darius D. Gaskins, James R. Lundberg
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Publication number: 20140258766Abstract: Methods and systems for determining latency across a bus, such as a PCIe bus, coupling a field programmable gate array (FPGA) and a processor having different time incrementation rates. Both the FPGA and the processor count clock ticks independently, and using a calibration offset and the two incrementation rates, the processor converts the FPGA clock ticks into processor clock ticks in order to determine latency across the bus.Type: ApplicationFiled: March 10, 2014Publication date: September 11, 2014Applicant: NovaSparks. S.A.Inventors: Marc Battyani, Jonathan Clairembault, Long Xu
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Patent number: 8832487Abstract: In embodiments of a high-speed I/O data system, a first computer chip includes a data transmission system, and a second computer chip includes a data reception system. A data channel communicates an NRZ data signal, and a clock channel communicates a forwarded clock signal, from the data transmission system to the data reception system. The data transmission system includes a first differential serializing transmitter to generate the NRZ data signal from pulsed data, and further includes a second differential serializing transmitter to generate a forwarded clock signal. A first multi-phase transmit clock generator generates transmit clock signals for the first and second differential serializing transmitters. The data reception system includes a data receiver and a de-serializer to receive and de-serialize the NRZ data signal, and includes a multi-phase receive clock generator to generate receive clock signals from the forwarded clock signal for the de-serializing data receiver.Type: GrantFiled: June 28, 2011Date of Patent: September 9, 2014Assignee: Microsoft CorporationInventor: Alan S. Fiedler
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Patent number: 8832488Abstract: A method and apparatus for digital I/O expander chip with multi-function timer cells have been disclosed. A series of match reload registers load a series of match registers which are driven by a master counter. The status of the match registers can be retrieved through ports. The master counter is reloaded on rollover by a count limit register. The master counter has increment/decrement control and the rollover can be used in an interrupt control block to generate an interrupt request.Type: GrantFiled: March 29, 2011Date of Patent: September 9, 2014Assignee: Digi International Inc.Inventors: Norman L. Rogers, Monte J. Dalrymple, Lynn S. Wood, Steve J. Hardy
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Patent number: 8826061Abstract: A method of implementing a system time in an electronic device using a timer is disclosed. The method comprises storing a first count reset value in the electronic device; increasing a count value; comparing the first count reset value with the count value at a first particular time; resetting the count value when the count value is the same as the first count reset value at the first particular time; and generating an interrupt request signal when the count value is reset.Type: GrantFiled: September 9, 2011Date of Patent: September 2, 2014Assignee: Samsung Electronics Co., Ltd.Inventor: Jong-Lae Park
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Patent number: 8826060Abstract: Methods and apparatus, including computer program products, are provided for using a relative timestamp to log activity in a distributed computing system. In one aspect, there is provided a computer-implemented method. The method may include receiving a message including a first timestamp representative of when the message is sent at a first processor. A second processor may generate an entry logging receipt of the received message. The second processor may determine a second timestamp representative of a time relative to the first timestamp. The second timestamp may be included as an entry at a log at the second processor.Type: GrantFiled: August 3, 2007Date of Patent: September 2, 2014Assignee: SAP AGInventors: Erol Bozak, Alexander Gebhart
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Patent number: 8819115Abstract: A method for sampling management includes establishing, for a multi-core intermediary comprising a plurality of packet evaluation components executing on a corresponding plurality of cores, a frequency at which the multi-core intermediary intercepts a response transmitted from a server to a client and injects data into the intercepted response. For each of the plurality of packet evaluation components, an offset and a frequency based on a number of packet evaluation components in the plurality of packet evaluation components is established, a combination of the established frequencies substantially similar to the frequency established for the multi-core intermediary. One of the plurality of cores intercepts a response from the server to the client, at a time specified by the frequency and the offset. The packet evaluation component executing on the one of the plurality of cores injects data into the intercepted response.Type: GrantFiled: December 23, 2009Date of Patent: August 26, 2014Assignee: Citrix Systems, Inc.Inventors: Roy Rajan, Saravanakumar Annamalaisami
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Publication number: 20140237285Abstract: A single pin is used to control an operating mode of an integrated circuit and to supply serial data to a host controller. The internal operating mode can be changed by changing a static level on an input/output terminal and maintaining that static level longer than a first time threshold. A read transaction from the integrated circuit can be performed in response to a predetermined sequence on the input/output terminal that includes a pulse that lasts a first predetermined time, the first predetermined time being less than the first time threshold.Type: ApplicationFiled: February 15, 2013Publication date: August 21, 2014Applicant: SILICON LABORATORIES INC.Inventors: Russell B. Fredrickson, Martin Pechanec, Jeffery A. Battles
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Patent number: 8812761Abstract: A system and method are described for warming a processor from a low power state in anticipation of a time critical interrupt. For example, one embodiment of a method comprises: detecting that a time-critical interrupt will require processor resources at some point in the future; estimating a time at which the time-critical interrupt will be triggered; scheduling a timer interrupt to fire at a specified time prior to the estimated time that the time-critical interrupt will be triggered, the timer interrupt being scheduled with sufficient time to ensure that the processor is warmed to a level at which it is capable of handling the time-critical interrupt at the time that the time-critical interrupt is triggered; and responsively triggering the timer interrupt at the specified time prior to the time critical interrupt.Type: GrantFiled: October 28, 2011Date of Patent: August 19, 2014Assignee: Apple Inc.Inventors: Daniel S. Heller, Christopher G. Peak, Guy G. Sotomayor, Umesh S. Vaishampayan
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Patent number: 8806496Abstract: In one embodiment, the present invention includes a method for determining a scaling factor between a frequency of a first processor and a frequency of a second processor after a guest software is migrated from first processor to the second processor, and executing the guest software on the second processor using a virtual counter based on a physical counter of the second processor and the scaling factor. Other embodiments are described and claimed.Type: GrantFiled: September 30, 2009Date of Patent: August 12, 2014Assignee: Intel CorporationInventor: Gang Zhai
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Patent number: 8799697Abstract: Methods, systems and devices configured to add synchronization to the entry and exit from low power modes in asynchronous operating systems on a multiprocessor system. A synchronizing agent tracks the requested sleep and wake up times of the different asynchronous operating systems executing on different cores of the same system on chip or multicore processor. The sleep/wake up times of some cores/operating systems may be delayed in order to synchronize the sleep/wake up times of two or more of the asynchronous operating systems executing on the multiprocessor system.Type: GrantFiled: November 4, 2011Date of Patent: August 5, 2014Assignee: QUALCOMM IncorporatedInventors: Paul R. Johnson, Gabriel A. Watkins
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Patent number: 8797083Abstract: Methods of operating timers include generating a periodic timing signal having a first frequency that differs from a desired timer frequency (1 KHz) by a first amount. This periodic timing signal having the first frequency can be generated by dividing a frequency of an input clock signal (e.g., 32.768 KHz) by N, where N is a positive integer greater than one. A typical value of N may be 32. The methods also include techniques to inhibit timing error accumulation by switching a frequency of the periodic timing signal from the first frequency to a second frequency that differs from the desired timer frequency by a second amount. This periodic timing signal having the second frequency can be generated by dividing the frequency of the input clock signal by M, where M is a positive integer unequal to N (e.g., M?N equals ±1).Type: GrantFiled: March 3, 2010Date of Patent: August 5, 2014Assignee: Samsung Electronics Co., Ltd.Inventor: Seung Kyu Kim
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Publication number: 20140201560Abstract: Methods, systems, and circuits for forming and operating a global hierarchical clock tree are described. The global hierarchical clock tree may comprise a clock circuit that operates to provide clock signals to a core circuit surrounded by the clock circuit. The clock circuit may include two or more first and second clock generator modules to generate a first and a second set of clock signals, respectively. The first and second clock modules may be located so that the first set of clock signals experience approximately equal first latencies and the second set of clock signals experience approximately equal second latencies. Additional methods, systems, and circuits are disclosed.Type: ApplicationFiled: January 21, 2014Publication date: July 17, 2014Applicant: Achronix Semiconductor CorporationInventors: Ravi Sunkavalli, Rahul Nimaiyar, Ravi Kurlagunda, Vijay Bantval
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Patent number: 8769330Abstract: Methods and apparatuses are provided that allow for the synchronization of an operating point transition in an embedded system environment. Identification of an upcoming operating point transition, operating point transition constraints, and maximum parking latency parameters is provided. Then, an ordering of seizing bus activity as well as an ordering of resuming bus activity is determined. The operating point transition is then implemented using the determined ordering. Simulation and determination of change of successfully completing operating point transition prior to initiating and while the transition is pending are also provided.Type: GrantFiled: March 17, 2011Date of Patent: July 1, 2014Inventor: Adam Kaiser
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Patent number: 8762755Abstract: Methods and systems for managing power consumption in data processing systems are described. In one embodiment, a data processing system includes a general purpose processing unit, a graphics processing unit (GPU), at least one peripheral interface controller, at least one bus coupled to the general purpose processing unit, and a power controller coupled to at least the general purpose processing unit and the GPU. The power controller is configured to turn power off for the general purpose processing unit in response to a first state of an instruction queue of the general purpose processing unit and is configured to turn power off for the GPU in response to a second state of an instruction queue of the GPU. The first state and the second state represent an instruction queue having either no instructions or instructions for only future events or actions.Type: GrantFiled: June 18, 2013Date of Patent: June 24, 2014Assignee: Apple Inc.Inventors: Joshua de Cesare, Bernard Joseph Semeria, Michael Smith
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Patent number: 8762763Abstract: The present invention discloses a single-wire transmission interface, and a method of transmission through single-wire. The method comprises: providing a single-wire signal through a single-wire; and transmitting information only in a transmission period defined by a fixed first time period starting from one of a rising or a falling edge of the single-wire signal.Type: GrantFiled: July 21, 2009Date of Patent: June 24, 2014Assignee: Richtek Technology CorporationInventors: Kwan-Jen Chu, Tsung-Wei Huang, Jien-Sheng Chen, Pao-Hsun Yu
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Patent number: 8756446Abstract: A microprocessor has a low-power mode and a non-low power mode. The microprocessor includes a processor core for executing instructions provided to the microprocessor and a clock providing a clock signal, which in the non-low power mode has a first frequency and in the low power mode has a second frequency lower than the first frequency. A hardware timer is present, for scheduling an execution of an event by the microprocessor at a future point in time. The hardware timer is connected to the clock for determining a period of time between a current point in time and a point in time the event based on a number of clock cycles of the clock signal. A timer controller can determine, when the data processing system switches from the low power mode to the non-low power mode, a number of clock cycles of a clock signal with the first frequency that corresponds to a low-power mode period during which the microprocessor has been in the low power mode and adjusting the hardware timer based on the determined number.Type: GrantFiled: April 11, 2008Date of Patent: June 17, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Vianney Rancurel, Vincent Bufferne, Gregory Meunier
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Patent number: 8756352Abstract: A system for managing time-stamped events with uncertain events-sequence signalling, including a list of variables of which a change of value must lead to the detection of an event to be time-stamped and to be saved; means, for each variable, for positioning a marker indicating the quality of the time-stamping of said event; a buffer for the storage, before they are read by client software, of said events to be time-stamped and to be saved, associated respectively with a time-stamping time, said time-stamped events read by the client software being erased from the buffer; means for enabling and for disabling means for saving in a history the values of the variables corresponding to said time-stamped events that have been read.Type: GrantFiled: November 15, 2012Date of Patent: June 17, 2014Assignee: Schneider Electric Industries SASInventors: Annick Eyraud, Philippe Wilhelm, Jacques Piacibello
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Patent number: 8756452Abstract: Pulses are used to control work ingress. Generally, a variable-speed clock is used for accepting work for lower-priority services. A clock rate is controlled by a load monitor. The load monitor periodically collects sensor measurements of resources available after allocations by higher-priority services. Based on the sensor measurements, the load monitor adjusts the clock speed up or down (i.e., depending on the amount of resources available after allocations by higher-priority services). At the boundary of the lower-priority service (e.g., where work enters the system), work requests are enqueued to be associated with a future pulse of the clock. Work is accepted or rejected based on a determination of whether the work request can be allocated a clock pulse within a defined period of time.Type: GrantFiled: March 1, 2013Date of Patent: June 17, 2014Assignee: Microsoft CorporationInventors: Nicholas A. Allen, Justin D. Brown
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Patent number: 8751852Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a Joint Test Action Group (JTAG) interface, a synchronous bus optimizer, and a delay-locked loop (DLL). The JTAG interface is configured to receive control information over a standard JTAG bus, where the control information indicates an amount to delay a data bit signal associated with a data group. The synchronous bus optimizer is configured to receive the control information, and is configured to develop a value on a ratio bus that indicates the amount. The DLL is coupled to the ratio bus, and is configured generate a delayed data bit signal, where the DLL adds the amount of delay to the data bit signal to generate the delayed data bit signal.Type: GrantFiled: June 21, 2011Date of Patent: June 10, 2014Assignee: Via Technologies, Inc.Inventors: Darius D. Gaskins, James R. Lundberg
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Patent number: 8751855Abstract: A method and memory device for generating a time estimate are provided. In one embodiment, a memory device generates a time estimate from time stamps in file system metadata for a plurality of files stored in the memory device and uses the time estimate to perform a time-based activity in the memory device. In another embodiment, a memory device generates a time estimate from time stamps stored in a plurality of files stored in the memory device and uses the time estimate to perform a time-based activity in the memory device. In yet another embodiment, a memory device obtains a plurality of time stamps, selects one or more of the plurality of time stamps based on validity rankings, generates a time estimate from the selected time stamp(s), and uses the time estimate to perform a time-based activity in the memory device.Type: GrantFiled: April 15, 2013Date of Patent: June 10, 2014Assignee: SanDisk IL Ltd.Inventors: Rahav Yairi, Itzhak Pomerantz, Itai Dror, Ori Stern
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Patent number: 8751842Abstract: A microcontroller includes a data input unit that receives input data and outputs a start request signal according to the input data upon receiving the input data; an oscillator that starts according to the start request signal, to generate a clock signal; a clock signal supply control unit that outputs the start request signal supplied from the data input unit to the oscillator, and supplies the clock signal supplied from the oscillator generated after the start as a first clock signal and a second clock signal that are operation clock signals of the data input unit; and a CPU that operates the second clock signal as an operation clock, and performs processing according to the input data when the second clock signal is operated.Type: GrantFiled: May 13, 2011Date of Patent: June 10, 2014Assignee: Renesas Electronics CorporationInventors: Yosuke Kawanaka, Seiya Indo, Tomoya Katsuki, Shinichi Nakatsu, Kimiharu Eto, Hirotaka Shimoda, Kuniyasu Ishihara, Yuusuke Urakawa, Yuusuke Sakaguchi, Shingo Furuta
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Patent number: 8751850Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a resistor network, a composite delay element, and delay-locked loops (DLLs). The resistor network is configured to provide a ratio signal that indicates an amount to delay data bit signals associated with a data group. The composite delay element is configured to equalize delay paths within a receiving device, where the delay paths correspond to a data strobe signal that is received from a transmitting device. The receiving device and resistor network are coupled to a motherboard. The ratio signal enters said receiving device through an external pin. The DLLs are coupled to the ratio signal and disposed within the receiving device, and are configured to generate delayed data bit signals, where the DLLs add the amount of delay to the data bit signals to generate the delayed data bit signals.Type: GrantFiled: June 21, 2011Date of Patent: June 10, 2014Assignee: VIA Technologies, Inc.Inventors: Darius D. Gaskins, James R. Lundberg
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Patent number: 8751851Abstract: An apparatus includes a Joint Test Action Group (JTAG) interface, a synchronous bus optimizer, a core clocks generator, and a synchronous strobe driver. The JTAG interface is configured to receive control information over a standard JTAG bus, where the control information indicates an amount to advance a synchronous data strobe associated with a data group. The synchronous bus optimizer is configured to receive the control information, and is configured to develop a value on a ratio bus that indicates the amount. The core clocks generator is coupled to the ratio bus and is configured to advance a data strobe clock by the amount. The synchronous strobe driver is configured to receive the data strobe clock, and is configured to employ the data strobe clock to generate the synchronous data strobe, where the synchronous data strobe, when enabled, is advanced also by the amount.Type: GrantFiled: June 21, 2011Date of Patent: June 10, 2014Assignee: VIA Technologies, Inc.Inventors: Darius D. Gaskins, James R. Lundberg
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Patent number: 8745433Abstract: A memory device includes a memory unit, a memory control unit that controls an access of the memory unit, a control unit that performs a communication process with a host device, a data terminal, a reset terminal, and a clock terminal. The control unit outputs a response signal for reporting the connection of the memory device to the host device through the data terminal in an m-th clock cycle (m is at least an integer of 1?m?n) corresponding to ID information of the memory device among first to n-th clock cycles (n is an integer of 2 or more) of clocks input to the clock terminal.Type: GrantFiled: February 18, 2011Date of Patent: June 3, 2014Assignee: Seiko Epson CorporationInventor: Jun Sato
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Patent number: 8738227Abstract: Disclosed is a dark current cutoff system and method for a vehicle junction. In particular, a controller is configured to monitor signal input through a CAN communication module to determine when other modules in the vehicle are in a sleep mode, cut off battery power to a load device by turning off a switching element when the controller determines that the other modules in the vehicle are in sleep mode, and forcibly maintains an off state of the switching element for a set period time after the power has been cut, regardless of signal input through the CAN communication module.Type: GrantFiled: September 6, 2012Date of Patent: May 27, 2014Assignee: Hyundai Motor CompanyInventors: Wang Seong Cheon, Young Kug Lee
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Publication number: 20140143584Abstract: A circuit for generating a peripheral clock for USB, provided on a USB major structure, comprises an internal oscillator, a receiver, a transmitter, a clock counter, and a clock processor; wherein the internal oscillator generates a clock having a settled frequency; the receiver is connected with the internal oscillator and a system unit, and receives a packet transmitted by the system unit; the transmitter is connected with the internal oscillator and the system unit, and transmits a packet of the USB major structure to the system unit; the clock counter is connected with the receiver and the internal oscillator, and counts a length of the packet received; and the clock processor is connected with the clock counter, the internal oscillator, and the transmitter, and controls and adjusts a length of the packet transmitted by the transmitter according to the length of the packet counted by the clock counter.Type: ApplicationFiled: November 16, 2013Publication date: May 22, 2014Applicant: IPGoal Microelectronics (Sichuan) Co., Ltd.Inventor: Xiu Yang
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Patent number: 8732514Abstract: Clock pulses of a variable speed clock are adjusted relative to system utilization. A load monitor periodically collects sensor measurements of resources and based on the sensor measurements, the load monitor adjusts the clock speed up or down.Type: GrantFiled: March 4, 2013Date of Patent: May 20, 2014Assignee: Microsoft CorporationInventors: Nicholas A. Allen, Justin D. Brown
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Patent number: 8726062Abstract: The present invention discloses data recovery architecture (CDR) to improve a multi-link system's tolerance to delay mismatches (or skewing effect) in its different links. The architecture is entirely digital and usable in any multi-link transceiver implementation that makes use of a separate clock link and requires timing synchronization between the different data links.Type: GrantFiled: December 1, 2011Date of Patent: May 13, 2014Assignee: Synopsys, Inc.Inventor: Jose Angelo Rebelo Sarmento
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Patent number: 8719615Abstract: A semiconductor device performs operation in synchronization with a certain clock signal. The semiconductor device includes a control unit for outputting operation control information, a storage unit for storing data, a first operation unit for performing operation on first data in accordance with first operation control information, and a second operation unit for performing operation on second data in accordance with second operation control information. The first operation unit includes a plurality of operation circuits. The number of logic gates constituting the entire operation circuits is m. The second operation unit includes at least one operation circuit in which the number of logic gates is n (n>m). Each of the total delay of the operation unit or the total delay of the operation unit is set at a value equal to or less than the cycle of the clock signal.Type: GrantFiled: March 17, 2011Date of Patent: May 6, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Yohei Hasegawa, Yutaka Yamada, Takashi Yoshikawa, Shigehiro Asano
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Patent number: 8713349Abstract: A semiconductor apparatus may comprise: a first chip ID generation unit configured to receive an enable signal through a first through-silicon via and a clock signal through a second through-silicon via and generate a first chip ID signal and a delayed enable signal; a second chip ID generation unit configured to receive the delayed enable signal through a third through-silicon via from the first chip ID generation unit and the clock signal and generate a second chip ID signal; a first chip selection signal generation unit configured to receive the first chip ID signal and a main ID signal and generate a first chip selection signal; and a second chip selection signal generation unit configured to receive the second chip ID signal and the main ID signal and generate a second chip selection signal.Type: GrantFiled: June 22, 2011Date of Patent: April 29, 2014Assignee: SK Hynix Inc.Inventors: Sang Jin Byeon, Jae Bum Ko
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Patent number: 8713347Abstract: A system and method are disclosed for masking a clock input from a clock line when the clock line is not being driven by a clock source. The clock mask is triggered by a clock cycle from the clock source. In one version, a memory controller configures a masking circuit to either allow a clock signal to the clock input or to mask the clock input from a bidirectional clock bus. The masking circuit may comprise a storage element and a gate, as an example.Type: GrantFiled: June 10, 2011Date of Patent: April 29, 2014Assignee: Marvell International Ltd.Inventor: Ross Swanson
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Publication number: 20140108850Abstract: Various techniques are provided to detect abnormal clock rates in devices such as imaging sensor devices (e.g., infrared and/or visible light imaging devices). In one example, a device may include a clock rate detection circuit that may be readily integrated as part of the device to provide effective detection of an abnormal clock rate. The device may include a ramp generator, a counter, and/or other components which may already be implemented as part of the device. The ramp generator may generate a ramp signal independent of a clock signal provided to the device, while the counter may increment or decrement a count value in response to the clock signal. The device may include a comparator adapted to select the current count value of the counter when the ramp signal reaches a reference signal. A processor of the device may be adapted to determine whether the clock signal is operating in an acceptable frequency range, based on the selected count value.Type: ApplicationFiled: December 13, 2013Publication date: April 17, 2014Applicant: FLIR Systems, Inc.Inventors: Brian Simolon, Eric A. Kurth, Jim Goodland, Mark Nussmeier, Nicholas Högasten, Theodore R. Hoelter, Katrin Strandemar, Pierre Boulanger, Barbara Sharp
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Patent number: 8694670Abstract: Techniques are described for synchronizing multiple time-based data streams with independent clocks wherein relationships between clock rates of timing devices associated with the time-based data streams are determined, and based on these relationships, times in at least one of the time-based data streams may be translated to times in any of the other time-based data streams despite the data streams having independent clocks.Type: GrantFiled: October 12, 2012Date of Patent: April 8, 2014Assignee: Apple Inc.Inventors: James D. Batson, John S. Bushell, Gregory R. Chapman, Christopher L. Flick
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Publication number: 20140089722Abstract: A single wire serial interface for power ICs and other devices is provided. To use the interface, a device is configured to include an EN/SET input pin. A counter within the device counts clock pulses sent to the EN/SET input pin. The output of the counter is passed to a ROM or other decoder circuit. The ROM selects an operational state for the device that corresponds to the value of the counter. In this way, control states may be selected for the device by sending corresponding clock pulses to the EN/SET pin. Holding the EN/SET pin high causes the device to maintain its operational state. Holding the EN/SET pin low for a predetermined timeout period resets the counter and causes the device to adopt a predetermined configuration (such as off) until new clock pulses are received at the EN/SET pin.Type: ApplicationFiled: September 16, 2013Publication date: March 27, 2014Applicant: Skyworks Solutions, Inc.Inventors: Kevin P. D'ANGELO, David Alan Brown, John Sung K. So, Jan Nilsson, Richard K. Williams