Abstract: A timer distribution module supports multiple timers and comprises: a command decoder arranged to determine expiration times of a plurality of timers; and a timer link list distribution adapter, LLDA, operably coupled to the command decoder. The LLDA is arranged to: receive a time reference from a master clock; receive timer data from the command decoder wherein the timer data comprises at least one timer expiration link list; construct a plurality of timer link lists based on at least one of: the timer expiration link list, at least one configurable timing barrier; dynamically split the link list timer data into a plurality of granularities based on the timer expiration link list; and output the dynamically split link list timer data.

Abstract: A data lineage tracking system may include a memory storing a module comprising machine readable instructions to obtain trace log entries representing an interaction with, a manipulation of, and/or a creation of a data value. The data lineage tracking system may further include machine readable instructions to select the trace log entries that are associated with commands performed by an application, cluster similar trace log entries from the selected trace log entries, and analyze mappings between the clustered trace log entries to determine data lineage flow associated with the data value.

Abstract: Example embodiments of the present invention provide a method, an apparatus, and a computer program product for scalable monitoring and error handling in multi-latency systems. The method includes gathering events from a multi-latency logical data store comprising a first data store having a first data latency and a second related data store having a second data latency substantially different than the first data latency. Processing then may be performed on the gathered events, with notification of the processed events provided toward downstream queues for consumption. In certain embodiments, consumption comprises holistic error handling; according, in those embodiments holistic error handling of the multi-latency logical data store may be performed according to the notification of the processed gathered events asynchronously from gathering events from the multi-latency logical data store.

Abstract: A system and method for securely recording voice communications, comprising an authentication server, further comprising at least a software components operating on a network-capable computing device, and a database, wherein an authentication server verifies the validity of voice communications and a database stores voice communication recordings.

Abstract: A virtualized application delivery controller (ADC) device operable in a communication network comprises a hardware infrastructure including at least a memory, a plurality of core processors, and a network interface; a plurality of instances of virtual ADCs (vADCs), the plurality of vADCs are executed over the hardware infrastructure, each of the plurality of vADCs utilizes a portion of hardware resources of the hardware infrastructure, the portion of hardware resources are determined by at least one ADC capacity unit allocated for each of the plurality of the vADCs; a management module for at least creating the plurality of instances of the vADCs; and a traffic distributor for distributing incoming traffic to one of the plurality of vADCs and scheduling execution of the plurality of vADCs on the plurality of core processors, wherein each of the plurality of vADCs is independently executed on at least one of the plurality of core processors.

Abstract: A calculation device is provided that executes calculations within real-time restrictions. The calculation device implements a step of predicting a processing time of a calculation related to the amount and property of input data based on a prediction model; a step of adjusting the processing time by decreasing the amount of data used for the calculation or decreasing the number of iterative calculations when the processing time exceeds a time slice allocated to the calculation; a step of executes the calculation using the adjusted processing time; a step of updating, as required, the prediction model used for predicting the processing time according to the result of the calculation which is executed in a period where the calculation is not performed while implementing a change of the amount of data or the number of iterative calculations or change to an approximation.

Abstract: Methods, non-transitory storage medium, and systems for generating an aggregated list of problem conditions associated with blade servers to facilitate efficient debugging thereof. In a blade server environment, each chassis is equipped with a chassis management module and each blade in each chassis is associated with a blade management controller. A data map representing the relationships between the blade servers and the shared resources is utilized by a chassis management module to aggregate and link problem conditions sensed by any of the blade management controllers.

Abstract: A method for high-speed scheduling and arbitration of events for computing and networking is disclosed. The method includes the software and hardware implementation of a unique data structure, known as a pile, for scheduling and arbitration of events. According to the method, events are stored in loosely sorted order in piles, with the next event to be processed residing in the root node of the pile. The pipelining of the insertion and removal of events from the piles allows for simultaneous event removal and next event calculation. The method's inherent parallelisms thus allow for the automatic rescheduling of removed events for re-execution at a future time, also known as event swapping. The method executes in O(1) time.

Abstract: Provided is a timing control device including: a storage unit that stores multiple pieces of timing control information including identification information and expected value data; a first selector that selectively outputs any of the multiple pieces of timing control information; a second selector that selectively outputs any of data items output from data output devices based on the identification information; a reference data generation unit that generates reference data based on expected value data and a data item output from the second selector in synchronization with a switching of the timing control information; a comparator that compares the reference data with the data item output from the second selector and outputs a coincidence signal when the reference data and the data item coincide with each other; and an output control unit that outputs a timing signal according to the coincidence signal.

Abstract: A security device includes a controller configured to determine a flow identifier and an event counter associated with a received data packet and a counter memory including multiple memory banks where each memory bank stores a partial counter value for one or more event counters. The counter memory is indexed by a counter identifier associated with the event counter. A memory controller selects a memory bank in the counter memory that was not the memory bank last selected and the partial counter value associated with the counter identifier in the selected memory bank is updated, the updated partial counter value being written back to the selected memory bank. In one embodiment, the partial counter value is updated and written back within the latency window of the memory bank last selected.

Abstract: A method is provided for efficiently scheduling timer events within an operating system by allocating a plurality of timers, each of which has an expiry time, to a set of available timer slots. The method defines a timer spread value that denotes the allowed variance of the expiry times of each of the timers, calculates a set of available timer slots for each of the timers based on the timer spread value, and adjusts the expiry times of the timers so as to insert and evenly spread the timers across the set of available timer slots. In one implementation, the set of available timer slots is located in a timer wheel existing within the operating system, and the timer wheel uses a plurality of timer vectors arranged into successively increasing levels, beginning with level zero.

Abstract: A method and computer program product for implementing the method, where the method comprises obtaining boot dependencies among a plurality of systems, wherein a boot dependency identifies a dependent system, a service system that provides a service to the dependent system, a provide state of the service system, and a need state of the dependent system that requires the service system to have reached the provide state. The method further comprises obtaining historical measurements of the time periods between states for each of the systems. Then, during a process of booting the plurality of systems, the method initiates boot of each dependent system at a time that is determined, based on the historical measurements, to allow the dependent system to reach the need state no earlier than the time at which the service system is determined, based on the historical measurements, to reach the provide state.

Abstract: A method for synchronizing clocks in nodes of a vehicle network of a motor vehicle corrects a time difference between a master clock and a slave clock, taking into account transmission delay for a message between a master node and a slave node. At least for a first synchronization of the master clock to a slave clock after the nodes of the vehicle network are started up, a default transmission delay in the slave node is used to correct the time difference, and/or the slave node sending out a Delay Request message, and recording in the master node the time at which Delay Request message is received and the master node sending the time, as a Delay Response message, back to the slave node. In the slave node, the transmission delay for a message between the master node and the slave node is determined.

Abstract: The present invention provides a method and an apparatus for wake-up control of an intelligent terminal. At least two alarm set indications are sent by one or more applications of the intelligent terminal. The alarm set indication is used to indicate a first alarm wake-up time determined by the application for waking up the intelligent terminal. At least two of the at least two first alarm wake-up times corresponding to the at least two alarm set indications are delayed until a second alarm wake-up time. The second alarm wake-up time is determined according to preset adjustment control information. The intelligent terminal is welcome at the second alarm wake-up time.

Abstract: A control method for an information processing system including a first computer, a second computer, and a plurality of storage devices coupled to the first computer and the second computer through a switch, a processing performance of the second computer being higher than a processing performance of the first computer, the control method includes setting, by the switch, the first computer as a target for connection of the plurality of storage devices; transmitting, by the first computer, data to be processed from the first computer to the plurality of storage devices and thereby storing the data in the plurality of storage devices; switching, by the switch, the target from the first computer to the second computer when the storing is completed; and executing, by the second computer, processing of the data stored in the plurality of storage devices.

Abstract: A transmission control device in the present invention includes: a data storage memory in which data are written; a plurality of data copy memories into which the data written in the data storage memory are copied; an unread copy-memory selection unit that selects one of the data copy memories for which reading of data is not performed from among the data copy memories; a memory copy unit that copies the data written in the data storage memory into a data copy memory selected by the unread copy-memory selection unit; a read copy-memory selection unit that selects a data copy memory into which the memory copy unit copies data from among the data copy memories; and a data output unit that reads data from a data copy memory selected by the read copy-memory selection unit and outputs the read data to a transmission unit.

Abstract: Disclosed are systems and methods for processing events in an event stream using a map-update application. The events may be embodied as a key-attribute pair. An event is processed by one or more instances implementing either a map or an update function. A map function receives an input event from the event stream and publishes one or more events to the event stream. An update function receives an event and updates a corresponding slate and publishes zero or more events. Systems and methods are also disclosed herein for implementing a map-update application in a multithreaded architecture and for handling overloading of a particular thread or node. Systems and methods for providing access to slates updated according to update operations are also disclosed.

Abstract: A thread (or other resource consumer) is compensated for contention for system resources in a computer system having at least one processor core, a last level cache (LLC), and a main memory. In one embodiment, at each descheduling event of the thread following an execution interval, an effective CPU time is determined. The execution interval is a period of time during which the thread is being executed on the central processing unit (CPU) between scheduling events. The effective CPU time is a portion of the execution interval that excludes delays caused by contention for microarchitectural resources, such as time spent repopulating lines from the LLC that were evicted by other threads. The thread may be compensated for microarchitectural contention by increasing its scheduling priority based on the effective CPU time.

Abstract: To provide a communication system and a communication method that are capable of determining with a simple configuration the validity of a message that is communicated with the communication system, a plurality of ECUs is connected in the communication system to a communication bus, allowing communication of messages. A communication interval, which is defined for each message being communicated, is set for each ECU. The ECU that transmits the message transmits the message on the basis of the defined communication interval. The ECU that receives the transmitted message detects the communication interval of the received message, and determines the validity of the received message on the basis of a comparison between the detected communication interval and the defined communication interval.

Abstract: The present invention discloses devices and methods for a connectivity hub, for connecting a plurality of storage devices to a host system, including: a plurality of ports, each port operative to electrically engage with a storage device; electrical paths joining the plurality of ports to a common point operationally connected to the host system; and a controller operative to associate a relative physical location with a logical identity for each port. Preferably, the controller is configured to perform the association by correlating an insertion time of the storage device in a respective port with a detection time of the logical identity. A connectivity hub, for connecting a plurality of storage devices to a host system, including: at least 23 ports, each port operative to electrically engage with a corresponding storage device; and electrical paths joining at least 23 ports to a common point operationally connected to the host system.

Abstract: A multicore system includes multiple processor cores; a scheduler in each of the processor cores and allocating a process to the processor cores when having a master authority that is an authority to assign processes; and a master controller performing control to repeat until a process to be executed no longer exists, a cycle in which the schedulers transfer the master authority to another processor core after receiving the master authority and before assigning a process to the processor cores, discards the master authority after assigning the process to the processor cores, and enters a state of waiting to receive the master authority.

Abstract: A method and an apparatus for controlling a dormancy mode of the portable terminal by minimizing the dormancy mode entry delay of the display in power-off state are provided. The method includes starting, when the application processor and the communication processor stop data communication in display power-off state, a dormancy mode timer, checking, when the dormancy mode timer expires, a dormancy mode flag indicating communication channel state, and entering, when the dormancy mode flag indicates a communication channel connection release state, the dormancy mode, wherein the dormancy mode timer counts a number of segments constituting a maximum standby time for entering the dormancy mode.

Abstract: An image forming apparatus communicates with a plurality of data processing apparatuses via a plurality of interfaces. The image forming apparatus includes a determination unit configured to determine a communication state with the plurality of interfaces, and a control unit configured to perform control to switch between a first sleep mode in which power supplied to any one of the plurality of interfaces is turned off and a second sleep mode in which power supplied to the plurality of interfaces is repeatedly turned on and off at predetermined time intervals according to the communication state determined by the determination unit.

Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for storing a plurality of items, each item including digital content, for each item of the plurality of items, generating a quality score to provide a plurality of quality scores, each quality score indicating a quality of an associated item and being based on at least one of a status score and a content score, the status score being associated with an author user of a respective item and the content score being associated with digital content provided in the respective item, determining an order of items based on respective quality scores, and transmitting instructions to display items to a user based on the order.

Abstract: Managing updates to executable programming code on a computer system in a computer network. A maintenance service utility is configured to launch a maintenance procedure at a specified time during operation of the computer system. Operation of a maintenance timer utility is activated during startup of the computer system to track and monitor the amount of time the computer system has been operating since startup. The maintenance service utility determines if there any updates to the executable programming code that require installation. The maintenance procedure is launched after a specified time if there are updates to the executable programming code. The computer system is automatically rebooted to install the updates to the executable programming code. A maintenance service editor utility enables the maintenance service utility to be configured to launch the maintenance procedure after a specified time if there are updates to the executable programming code.

Abstract: Provided is a technique that is capable of efficiently compressing instructions by inserting instruction compression bits into valid instruction bundles and deleting no operation (NOP) instruction bundles. Accordingly, the number of instructions that can be parallel-processed in a processor may be increased.

Abstract: Provided is a memory controller that manages memory access requests between the processor and the memory. In response to the memory controller receiving two or more memory access requests for the same area of memory, the memory controller is configured to stall the memory controller and sequentially process the memory access requests.

Abstract: In general, embodiments of the invention provide an approach to proactively adjust timeout settings on a display device based on user activity. Specifically, a system and method are presented to adaptively adjust the inactivity timeout settings on a display device based on the application being used, the content being displayed on the device, and an analysis of the user's history with the application. The present invention calculates an inactivity timeout modifier which is utilized to modify the default operating system timeout value.

Abstract: An integrated-circuit memory controller outputs to a memory device a first signal in a first state to enable operation of synchronous data transmission and reception circuits within the memory device. A transaction queue within the memory controller stores memory read and write requests that, to be serviced, require operation of the synchronous data transmission and reception circuits, respectively, within the memory device. Power control circuitry within the memory controller determines that the transaction queue has reached a predetermined state and, in response, outputs the first signal to the memory device in a second state to disable operation of the synchronous data transmission and reception circuits within the memory device.

Abstract: Methods for preventing activation of hardware backdoors installed in a digital circuit, the digital circuit comprising one or more hardware units to be protected. A timer is repeatedly initiated for a period less than a validation epoch, and the hardware units are reset upon expiration of the timer to prevent activation of a time-based backdoor. Data being sent to the hardware unit is encrypted in an encryption element to render it unrecognizable to a single-shot cheat code hardware backdoor present in the hardware unit. The instructions being sent to the hardware unit are reordered randomly or pseudo-randomly, with determined sequential restraints, using an reordering element, to render an activation instruction sequence embedded in the instructions unrecognizable to a sequence cheat code hardware backdoor present in the hardware unit.

Abstract: Systems and methods are disclosed which relate to improving synchronization of clocks between a sender and a receiver communicating via an asynchronous serial interface. In a ring topology, a master device is connected to a plurality of slaves communicating using a bi-frequency encoded bit stream. A host device communicates with the master device using a non-return-to-zero data encoding. Each slave receives data from the master and sends it to the next slave in the ring unaltered unless the master indicates a requirement for a particular data, and transmits placeholder bits with a value of 0 around the ring. A particular slave can “fill-in” the placeholder bits with the information to be sent back to the master by inverting the placeholder bit. Clock synchronization between a receiving device and a transmitting device is improved using a fractional rate multiplier to generate a data sampling clock from a system clock.

Abstract: Provided is a timing control device including: a storage unit that stores multiple pieces of timing control information including identification information and expected value data; a first selector that selectively outputs any of the multiple pieces of timing control information; a second selector that selectively outputs any of data items output from data output devices based on the identification information; a reference data generation unit that generates reference data based on expected value data and a data item output from the second selector in synchronization with a switching of the timing control information; a comparator that compares the reference data with the data item output from the second selector and outputs a coincidence signal when the reference data and the data item coincide with each other; and an output control unit that outputs a timing signal according to the coincidence signal.

Abstract: A microcontroller has a central processing unit (CPU), a plurality of peripherals, and a programmable scheduler unit with: —a timer being clocked by an independent clock signal; —a comparator coupled with a timer register of said timer and having an output generating an output signal; —an event register coupled with said comparator; —a delta time register; and —an arithmetic logic unit controlled by the output signal of the comparator and with first and second inputs and an output, wherein the first input is coupled with the timer register or the event register and the second input is coupled with the delta time register and the output is coupled with the event register.

Abstract: A device configured to switch a clock speed for multiple links running at different clock speeds and a method for switching the clock signals are disclosed. A frequency divider derives a plurality of clock signals at different frequencies from a source clock signal. A clock switching controller selects a maximum data rate among data rates requested by a plurality of ports of links and outputs a transmit clock signal at the selected maximum data rate to the ports along with a clock enabling signal for each of the ports. Each of the clock enabling signals selectively enables the transmit clock signal for matching a data rate requested by each port. The clock speed may be selected and updated as required by the ports glitch-free in a known amount of time without interrupting data transfers on any of the other ports.

Abstract: A clock-less asynchronous processing circuit or system having a plurality of pipelined processing stages utilizes self-clocked generators to tune the delay needed in each of the processing stages to complete the processing cycle. Because different processing stages may require different amounts of time to complete processing or may require different delays depending on the processing required in a particular stage, the self-clocked generators may be tuned to each stage's necessary delay(s) or may be programmably configured.

Abstract: A clock-less asynchronous processing circuit or system utilizes a self-clocked generator to adjust the processing delay (latency) needed/allowed to the processing cycle in the circuit/system. The timing of the self-clocked generator is dynamically adjustable depending on various parameters. These parameters may include processing instruction, opcode information, type of processing to be performed by the circuit/system, or overall desired processing performance. The latency may also be adjusted to change processing performance, including power consumption, speed etc.

Abstract: An integrated circuit implements a multistage processing pipeline, where control is passed in the pipeline with data to be processed according to the control. At least some of the different pipeline stages can be implemented by different circuits, being clocked at different frequencies. These frequencies may change dynamically during operation of the integrated circuit. Control and data to be processed according to such control can be offset from each other in the pipeline; e.g., control can precede data by a pre-set number of clock events. To cross a clock domain, control and data can be temporarily stored in respective FIFOs. Reading of control by the destination domain is delayed by a delay amount determined so that reading of control and data can be offset from each other by a minimum number of clock events of the destination domain clock, and control is read before data is available for reading.

Abstract: Computing devices and methods for resetting an inactivity timer of each of a first and second computing device are described. In one embodiment, the method comprises establishing a communication channel between the first computing device and the second computing device, receiving activity input responsive to a user interaction at the first computing device, resetting the inactivity timer of the first computing device, and transmitting a notification via the communication channel to the second computing device that the activity input was received at the first computing device, the inactivity timer of the second computing device being reset in response to receipt of the notification.

Abstract: Apparatuses, master-slave detect circuits, memories, and methods are disclosed. One such method includes performing a master detect phase during which a memory unit in a memory group is determined to be a master memory unit, determining at each memory unit its location relative to other memory units, and determining at each memory unit its location in the memory group based on a total number of slave memory units and its location relative to other memory units.

Abstract: Circuitry is disclosed that comprises: at least one element located within the circuitry and configured to hold an increasing count value; an encoder for receiving the increasing count value from a source of the increasing count value and configured to encode the increasing count value into encoded values, the encoded values each indicating an exponential amount to be applied to the count value held in the at least one element; interconnect circuitry for receiving the encoded value and transmitting the encoded value to the at least one element; wherein the at least one element comprises a decoder for decoding the encoded values and for increasing the count value in dependence upon the exponential amount.

Abstract: Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits.

Abstract: An information processing apparatus includes a processor programmed to detect scheduled starting times of two events to be executed at a current time or thereafter; calculate a difference of the scheduled starting times of the two events, when the scheduled starting times of the two events have been detected; and correct, based on the calculated difference and to an extent that a restriction indicated in restriction information of an event to be corrected is observed, the scheduled starting time of at least any one of the two events, as the event to be corrected, such that an interval between the scheduled starting times of the two events is shortened.

Abstract: Disclosed is a data processing system that permits the analysis of software in the entire data processing system even when it is configured so that a plurality of control modules is dispersively installed at remote places. In the data processing system formed of the control modules, the control modules each include a timer that counts time common to the entire data processing system, and a time synchronization process is employed to synchronize time information derived from the timer in a low-level control module with time information derived from the timer in a high-level control module. The data processing system incorporates a log acquisition function that not only acquires a log but also adds a timestamp based on timer time to the acquired log during, for example, an application process.

Abstract: A timer module having a status register is connectable to an external arithmetic unit and generates at least one activity signal for an internal signal of the timer module and/or an internal unit of the timer module and/or a process within the internal unit, and enters an activity status into a status register in the event of a determined activity, and allows the activity status to be polled and reset by the external arithmetic unit at times determined by the external arithmetic unit. Furthermore, the activity status entered into the status register remains until it is reset by the external arithmetic unit.

Abstract: An overclocking module, a computer system and a method for overclocking are provided. The method is used to overclock the computer system. The overclocking module of the invention includes a timer, a monitoring unit and a control unit. The timer starts to count when the computer system is booted. The monitoring unit monitors whether the computer system performs a boot-up procedure within a period of time. The control unit adjusts an operating frequency of the computer system to overclock the computer system automatically according to the monitoring result of the monitoring unit.

Abstract: A memory controller includes an digitally programmable delay unit having a selectable delay time receiving a read-enable signal and outputting a delayed read-enable signal. The delay time is selected in response to an externally applied delay-control signal. A sampling unit in the memory controller outputs data received from a separate memory, in synchronization with the delayed enable signal. The delay time may be a multiple of the period of a clock signal.

Abstract: Method and system for rate matching in networks is provided. The method includes setting a strobe counter of a network device equal to an initial value; and determining whether a current clock phase matches a clock phase during which a first sub-port from among a plurality of sub-ports is designated to read from a memory at a receive segment of the network device. When the current clock phase matches the designated clock phase for the first sub-port, determining if the strobe counter is equal to one of a plurality of mask values; and when the strobe counter is not equal to one of the mask values, reading data out of the memory.

Abstract: A technique for detecting full-system idle state in an adaptive-tick kernel includes detecting non-timekeeping CPU idle state, initiating a hysteresis period, waiting for the hysteresis period to end, manipulating a data structure whose state indicates whether a scheduling clock tick may be disabled on all CPUs, and disabling the scheduling clock tick if the data structure is in an appropriate state. In a first embodiment, non-timekeeping CPUs manipulate a global counter when entering an idle state, but add hysteresis to avoid thrashing the counter. Timekeeping is turned off based on the count maintained on the global counter. In a second embodiment, a Read-Copy Update (RCU) dynticks-idle subsystem running on a timekeeping CPU manipulates a global state variable whose states indicate whether all non-timekeeping CPUs are in an idle state, and if so, for how long. Timekeeping is turned off based on the state of the global state variable.

Abstract: A host interface for a storage module may include an out-of-band (OOB) detector that is configured to detect receipt of an OOB signal using a clock signal. The clock signal may be generated by a clock generator that is activated using a counter. When an OOB signal is received, the counter may activate the clock generator. When no OOB signal is being received, the counter may wait for a predetermined time period before deactivating the clock generator.

Abstract: A system provides virtual per-processor timers based on a timer such as a platform timer. To virtualize a timer to be used by each processor independently, a data structure is maintained in memory for the timer. The data structure has an entry for each interrupt to be produced for each processor using the timer, specifying the processor and the due time, with the entries sorted by due time. If the virtualized timer is a platform timer that maintains context during power transitions, a processor can switch to the virtual per-processor timer upon a context-losing power transition.