Abstract: Disclosed are various embodiments for a timeout management application. Latency data for executing services is obtained. The used service capacity is calculated. If the service capacity is outside of a predefined range, the timeout of a selected service is reconfigured.

Abstract: A circuit for trimming an internal oscillator of a USB device that generates a clock signal as a frequency source of the USB device includes a counter, a first detector for detecting an end of packet from an input data stream to initialize a counter, a second detector for detecting a synchronization sequence, a token packet or a handshake packet in the data stream for the counter to carry out clock counting on the clock signal, and a trimming code controller for comparing the count value with a reference value to determine a trimming code for trimming a clock frequency of the internal oscillator.

Abstract: A method is provided for efficiently scheduling timer events within an operating system by allocating a plurality of timers, each of which has an expiry time, to a set of available timer slots. The method defines a timer spread value that denotes the allowed variance of the expiry times of each of the timers, calculates a set of available timer slots for each of the timers based on the timer spread value, and adjusts the expiry times of the timers so as to insert and evenly spread the timers across the set of available timer slots. In one implementation, the set of available timer slots is located in a timer wheel existing within the operating system, and the timer wheel uses a plurality of timer vectors arranged into successively increasing levels, beginning with level zero.

Abstract: A method of providing a synchronization channel to a SuperSpeed USB device is provided. The method including a SuperSpeed communication channel connection to the SuperSpeed USB device with a USB cable that has USB 2.0 D+ and D? data signalling lines disabled or disconnected at an upstream connection point; multiplexing synchronization information onto the D+/D? data signalling lines at the upstream connection point; and demultiplexing the synchronization information from the D+/D? signalling lines at a downstream connection point of the cable; whereby the synchronization channel is maintained across the D+/D? data signalling lines.

Abstract: An apparatus having a first memory and a circuit is disclosed. The first memory may be configured to store a plurality of timers. Each of the timers may have a respective value that indicates an expiration time. A first one of the timers nearest to expiring is generally stored at a first address of the first memory. The circuit may be configured to (i) assert a signal in response to the respective value of the first timer matching a counter of time, (ii) read a second of the timers and a third of the timers both from a second address of the first memory, (iii) sort the second timer and the third timer to determine which expires next and (iv) replace the first timer by writing one of the second timer or the third timer that expires next into the first memory at the first address.

Abstract: A method for monitoring a frequency signal provided within a unit is disclosed. The method comprises a step of receiving one or more binary signal levels of a cycle signal (CLK) or a control signal (CS) from a communication interface (CLK, CS, MOSI, MISO), wherein the communication interface (CLK, CS, MOSI, MISO) is designed to transfer information according to a communication protocol. The method further comprises a step of providing the frequency signal in the unit and comparing the frequency signal to a temporal sequence of signal levels of the cycle signal (CLK) received by the communication interface (CLK, CS, MOSI, MISO) in order to obtain a comparison result or controlling a counter by the control signal (CS) and the frequency signal in order to obtain a counter status.

Abstract: System and method for synchronizing devices. A device reads a first counter coupled to and associated with a master clock and a second counter coupled to and associated with the device, where the device is one of one or more devices coupled to the master clock and each other via a switched fabric, where each device includes a respective clock, and is coupled to and associated with a respective second counter. Each of the first counter and the second counters is accessible by each of the one or more devices. The device determines a difference between the device's associated second counter and the first counter, and determines and stores a time reference for the device relative to the master clock based on the determined difference, where the time reference is useable to timestamp events or synchronize future events.

Abstract: A method of tuning a phase of a clock signal includes performing data training on a plurality of data pins through which data are input and output, in synchronization with a data clock signal; determining one of the data pins to be a representative pin; performing clock and data recovery (CDR) on read data of the representative pin; and adjusting a phase of the data clock signal based on the CDR.

Abstract: A data processing apparatus includes a storage unit and operates in a first power mode in which power that the storage unit can operate is supplied to the storage unit or in a second power mode in which power that the storage unit can operate is not supplied to the storage unit. The data processing apparatus includes an input unit configured to input data, a storing unit configured to store the data in the storage unit, a setting unit configured to set waiting time for making the data processing apparatus wait to shift from the first power mode to the second power mode according to a storage destination if the data is stored in the storage unit, and a control unit configured to shift the data processing apparatus from the first power mode to the second power mode when the waiting time elapses after the data is stored in the storage unit.

Abstract: In a first circuit for detecting clock glitches in a clock signal, a master counter is clocked by the clock signal and memorizes a master count. An incrementer advances the master count by one increment. A slave counter is clocked by the clock signal and memorizes a slave count. The slave count is retarded relative to the master count by at least a particular number of clock edges. A comparator determines whether the difference between the master count and the slave count is at least a value of the incrementer times the particular number of clock edges.

Abstract: In one embodiment, an apparatus may include a rising edge detector to detect a rising edge in a signal. The apparatus may also include a counter to perform a count to a first value based on an input clock signal. The apparatus may also include an output unit to generate a sleep signal after the first value is reached if the rising edge detector does not detect the rising edge in the signal.

Abstract: A method for enabling an oscillating crystal available in a system to be used to generate a software-realized time function, and an apparatus for implementing the method, without requiring additional hardware components, wherein a periodic interrupt signal is generated by the system-internal real-time clock, a table entry with a reference to a routine in an intra-system table is accessed upon receipt of the periodic interrupt signal and a counter is formed by the routine.

Abstract: This invention relates to a method and a system for generating user passcodes for each of a plurality of transaction providers from a mobile user device. A method and system for activating a plurality of passcode generators on a user device configured with a passcode application installed on the user device is provided. Each of the passcode generators may correspond to a different user account or transaction provider, such that each passcode generator provides a user passcode configured for the corresponding account or transaction provider. One or more of the passcode generators may include a passcode generating algorithm and a passcode key. Access to one or more of the passcode generators may require providing a PIN or a challenge.

Abstract: A circuit and method for trimming an internal oscillator of a USB device that generates a clock signal as a frequency source of the USB device detect an end of packet from an input data stream to initialize a counter, identify a token packet in the data stream to detect a start of frame token packet for the counter to carry out clock counting on the clock signal to thereby obtain a count value, and compare the count value with a reference value to determine a trimming code for trimming a clock frequency of the internal oscillator.

Abstract: Apparatuses, master-slave detect circuits, memories, and methods are disclosed. One such method includes performing a master detect phase during which a memory unit in a memory group is determined to be a master memory unit, determining at each memory unit its location relative to other memory units, and determining at each memory unit its location in the memory group based on a total number of slave memory units and its location relative to other memory units.

Abstract: System and method for synchronizing devices. A device reads a first counter coupled to and associated with a master clock and a second counter coupled to and associated with the device, where the device is one of one or more devices coupled to the master clock and each other via a switched fabric, where each device includes a respective clock, and is coupled to and associated with a respective second counter. Each of the first counter and the second counters is accessible by each of the one or more devices. The device determines a difference between the device's associated second counter and the first counter, and determines and stores a time reference for the device relative to the master clock based on the determined difference, where the time reference is useable to timestamp events or synchronize future events.

Abstract: A method for providing a timestamp in a real-time system, whereby the real-time system has an FPGA and a CPU, which cooperate with one another, and at least one register, which contains a system time, is implemented in the FPGA. The method includes the steps of providing a CPU counter for the system time, which is driven by a clock signal of the CPU, providing a synchronization counter in the CPU, whereby the synchronization counter is driven by a clock signal of the CPU, reading of the counter for providing the system time by a real-time application, querying the synchronization counter in the real-time application, and synchronizing the counter with the system time in the real-time application, when the synchronization counter outputs a value that corresponds to more than a predefined time period since the last synchronization of the CPU counter with the system time.

Abstract: The present invention may provide a system with a fixed clock to provide a fixed clock signal, and a variable clock to provide a variable clock signal. The system may also include a chipset with a chipset time stamp counter (TSC) based on the fixed clock signal. A processor may include a fast counter that may be based on the variable clock signal and generate a fast count value. A slow counter may download a time stamp value based on the chipset TSC at wakeup. The slow counter may be based on the fixed clock signal and may generate a slow count value. A central TSC may combine the fast count and slow count value to generate a central TSC value.

Abstract: A method for trimming a cycle time of an adjustable oscillator to match a Controller Area Network-bus (CAN-bus) operating with a predetermined bit time includes determining a measured number of cycles of an adjustable oscillator between a first signal and a second signal within a CAN frame transmitted on a CAN-bus; determining an information about a present cycle time of the adjustable oscillator using the measured number of cycles and a nominal number of cycles per bit time; and trimming a cycle time of an adjustable oscillator to match the CAN-bus operating with a predetermined bit time based on the determined information.

Abstract: When a user presses down an extension directing button, a control unit of an image forming apparatus detects the press-down of the extension directing button and executes a setting process of new mode set time. In this case, the control unit calculates the new mode set time by adding extension time extracted from an extension time data storage unit to basic set time acquired from a basic set time data storage unit and records the new mode set time in a mode set time data storage unit. Then, when start of a sleep mode is detected, the control unit of the image forming apparatus records the basic set time, which is extracted from the basic set time data storage unit, in the mode set time data storage unit as new mode set time when the mode set time is extended.

Abstract: Techniques for classifying unknown files taking into account temporal proximity between unknown files and files with known classifications are disclosed. In response to a classification request for a target file, client systems hosting (or hosted) instances of the target file are identified. For each system, files created around the time the target file was created on the system are identified. Within the identified files, files with known classifications are identified, and a score is determined for each such file to measure temporal proximity between the creation of the file and the creation of the target file. Local temporal proximity scores aggregate the scores for the client system. Global temporal proximity scores measures an aspect of the local temporal proximity scores for all identified client systems. The global temporal proximity scores are fed into a classifier to determine a classification, which is returned in response to the classification request.

Abstract: An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a logic circuit, for example a memory device. A first phase detector, array of delay lock loop (DLL) delay elements and accompanying circuitry are disclosed to phase-lock the rising edge of the output signal with the rising edge of the system clock XCLK signal. Additionally, a comparator circuit, a register delay, an array of DLL delay elements and accompanying circuitry are disclosed to add or subtract delay from the falling edge of the DQ signal in order to produce a symmetrical output of the DQ signal.

Abstract: Objects of the invention are to provide a clock generation circuit and to provide a semiconductor device including the clock generation circuit. The clock generation circuit includes an edge detection circuit, a reference clock generation circuit, a reference clock counter circuit, and a frequency-divider circuit. The reference clock counter circuit is a circuit which outputs a counter value, which is obtained by counting the number of waves of a reference clock signal outputted from the reference clock generation circuit, in a period of time from when the edge detection circuit detects an edge of a signal which is externally inputted to the edge detection circuit to when the edge detection circuit detects the next edge, to the frequency-divider circuit. The frequency-divider circuit is a circuit which frequency-divides the reference clock signal based on the counter value.

Abstract: Receiving an indication of a frequency ratio of first and second clocks; generating an indication of a number of clock pulses of the second clock occurring between first and second clock pulses of the first clock; and generating an indication of a time offset between (1) a clock pulse of the second clock occurring between the second clock pulse and a third clock pulse of the first clock, and (2) the second clock pulse of the first clock. Also, receiving an input data word representing a fractional number, a first part of the input data word comprising an integer portion of the fractional number and a second part comprising a decimal portion of the fractional number; providing a first output data word that is either the first part of the input data word or an increment by one of the first part; and providing a second output data word that is an integer multiple of the second part.

Abstract: A system and method for encrypting secondary copies of data is described. In some examples, the system encrypts a secondary copy of data after the secondary copy is created. In some examples, the system looks to information about a data storage system, and determines when and where to encrypt data based on the information.

Abstract: A computer system includes a processor, a submodule connected to the processor, an external access monitor configured to monitor a data transfer between the processor and the submodule, and a synchronization/desynchronization controller configured to synchronize or desynchronize the clock of the processor with respect to the clock of the submodule, depending on the result of the monitoring. Specifically, the processor clock is synchronized to the submodule clock when the frequency of access to the submodule by the processor is high, and the processor clock is desynchronized with respect to the submodule clock when the access frequency is low.

Abstract: A watchdog timer circuit for use in microcomputer monitor systems is disclosed. This circuit includes a timer circuit responsive to receipt of a count clock signal for counting it up, and a timer control circuit which loads an externally inputted data signal (stn) in sync with a timer refresh instruction (prun) and holds therein a sequentially loaded latest multi-bit data signal as reference data. When the reference data agrees with a predefined pattern and simultaneously another prespecified condition is met, the timer control circuit interrupts the clock signal counting operation of the timer circuit. During interruption of the counting operation, when the reference data does not agree with the predefined pattern or when the above-stated another prespecified condition becomes unsatisfied, the control circuit allows the timer circuit to restart the clock signal counting operation.

Abstract: Apparatuses, master-slave detect circuits, memories, and methods are disclosed. One such method includes performing a master detect phase during which a memory unit in a memory group is determined to be a master memory unit, determining at each memory unit its location relative to other memory units, and determining at each memory unit its location in the memory group based on a total number of slave memory units and its location relative to other memory units.

Abstract: A decision tree for classifying computer files is constructed. Computational complexities of a set of candidate attributes are determined. A set of attribute vectors are created for a set of training files with known classification. A node is created to represent the set. A weighted impurity reduction score is calculated for each candidate attribute based on the computational complexity of the attribute. If a stopping criterion is satisfied then the node is set as a leaf node. Otherwise the node is set as a branch node and the attribute with the highest weighted impurity reduction score is selected as the splitting attribute for the branch node. The set of attribute vectors are split into subsets based on their attribute values of the splitting attribute. The above process is repeated for each subset. The tree is then pruned based on the computational complexities of the splitting attributes.

Abstract: Systems and methods are disclosed for limiting power consumption of a non-volatile memory (NVM) using a power limiting scheme that distributes a number of concurrent NVM operations over time. This provides a “current consumption cap” that fixes an upper limit of current consumption for the NVM, thereby eliminating peak power events. In one embodiment, power consumption of a NVM can be limited by receiving data suitable for use as a factor in adjusting a current threshold from at least one of a plurality of system sources. The current threshold can be less than a peak current capable of being consumed by the NVM and can be adjusted based on the received data. A power limiting scheme can be used that limits the number of concurrent NVM operations performed so that a cumulative current consumption of the NVM does not exceed the adjusted current threshold.

Abstract: Disclosed herein is an information processor including: a processing section adapted to perform a predetermined process on a data signal output in synchronism with one of positive and negative edges of a clock signal and output an execution result thereof; a holding section adapted to hold the execution result in synchronism with the other of the positive and negative edges; a timing determination section adapted to determine whether a grace period lasting until the execution result is held by the holding section meets a setup time of the holding section; a clock control section adapted, if it is determined that the grace period does not meet the setup time, to control at least the timing of either the positive or negative edge in such a manner that the grace period meets the setup time; and a clock generation section adapted to generate the clock signal according to the controlled timing.

Abstract: An audio-video (AV) playback chain and rendering peripheral device 300 for generating two or more interrupts 306, 308 with a programmable delay 304 between them. Such are configured to prevent two processors 310, 314 from racing to access the same system resources in their respective interrupt service routines.

Abstract: A calculation method includes calculating, by a processor, a difference between a first value and a second value, the first value being read from a clock counter that counts pulses of a clock signal having a plurality of types of frequencies, supplied to the processor in response to control command to start processing for an unit to be allocated to the processor, the second value being read from the clock counter in response to control command to stop processing.

Abstract: There is provided a serial reception circuit that can suppress the occurrence of a bit error due to long-period jitter while suppressing the power consumption. A serial reception circuit for receiving a serial signal in synchronization with a clock signal samples the serial signal in synchronization with multiphase sampling clock signals out of phase with the clock signal, determines based on sampled signals that a sampling phase having little effect of phase variation of the serial signal on a sampling result is an optimum phase, performs a reception operation in which a signal sampled by the optimum phase is reception data, and has, as determination operations for the optimum phase, a first mode and a second mode in which optimality of an optimum phase determined in the first mode is determined based on a sampling result of a reduced number of samplings.

Abstract: A method for providing applications with a current time value includes receiving a trap for an application to access a time memory page, creating, in a memory map corresponding to the application, a mapping between an address space of the application and the time memory page in response to the trap, accessing, based on the trap, a hardware clock to obtain a time value, and updating the time memory page with the time value. The application reads the time value from the time memory page using the memory map.

Abstract: User space applications can utilize custom network protocol timers. A registration request is received from an application to register a custom timer. Responsive to receiving the registration request, a handle is created. The handle is a pointer to be used by the application to reference the custom timer. The handle is forwarded to the application. When a custom timer is required, a request to use a custom timer is received from an application. The kernel is then requested to start the custom timer. A determination is then made as to whether a receipt confirmation is received from the kernel before expiration of the custom timer.

Abstract: Methods, systems, and products are disclosed for evaluating the performance of a viewer watching media programming. The media programming is received and includes at least one of a live media program and a recorded media program. Display is caused of the media programming and a cue. The cue prompts the viewer during presentation of the media programming to provide a response to the cue within a time period. Upon receiving the response to the cue within the time period, then the response is detected and a response time of the response is measured. The response time is a time between occurrence of the cue and receipt of the response. The viewer's performance is evaluated by comparing the response time to a reference response time.

Abstract: A tracing apparatus for tracing operational information that is output from a plurality of processing units in relation to data processing operations, the tracing apparatus comprising for each of the processing units: a counting unit configured to obtain and output a counter value for the corresponding processing unit, the counter value obtained by counting clock signals that are input to the processing unit at an operating frequency thereof; a counter value conversion unit configured to obtain and output a converted counter value for the corresponding processing unit, the converted counter value obtained by converting the counter value based on the assumption that the processing unit has a given reference operating frequency; and an adding unit configured to acquire an operational information set from the corresponding processing unit, and to add the converted counter value to the operational information set.

Abstract: Methods and systems for providing lime information in intermittently powered devices that are batteryless and operate purely on harvested energy (also referred to as zero power devices). The method of these teachings for improving security of zero power devices includes determining an estimate of time using a decay of data in a volatile device, and deciding whether to respond to a query based on the estimate of time.

Abstract: Methods and structures that implement an event counter in a RAM are provided. A method includes providing a count-RAM, a carry-RAM, and a pre-counter corresponding to an event source. A column in the count-RAM and a column in the carry-RAM represent a value of a value of the event counter. The method further includes storing a count of the event counter received via the pre-counter in the count-RAM and the carry-RAM in a transposed, bit-serial format, such that location zero of the count-RAM and the carry-RAM counts the least significant bit (LSB) of the event counter.

Abstract: A time measurement device includes a first measurement unit configured to measure a clock number of a first reference clock signal within a specific cycle of a second reference clock signal; a calculation unit configured to calculate a physical amount indicating a variance amount of the clock number relative to a reference clock number; a compensation unit configured to compensate an expected measurement value indicating the clock number of the first reference clock signal corresponding to a time as a measurement target according to the physical amount calculated with the calculation unit; and an output unit configured to output time information indicating that the clock number of the first reference clock signal reaches the expected measurement value when the clock number of the first reference clock signal measured with the first measurement unit reaches the expected measurement value compensated with the compensation unit.

Abstract: A real time clock for outputting data indicating a time of day includes: an event detection circuit for detecting that an event detection signal has been inputted from outside; a timing circuit for generating the time-of-day data according to a signal outputted from an oscillator circuit; a memory; and a control circuit for, if the event detection circuit detects input of the event detection signal, recording event data in the memory, the event data including additional data indicating an operating state of the real time clock and the time-of-day data generated by the timing circuit.

Abstract: An information processing device having low power consumption without affecting interruption request response speed. The device specifies a waiting time until execution of a given event and makes a system call and includes a first timer circuit for a first cycle; a second timer circuit for a second cycle shorter than the first cycle; a timeout supervisor which stores the waiting time; and a first cycle supervisor which stores waiting time until the next interruption request. The timeout supervisor stores the time calculated by subtraction of the waiting time stored in the first cycle supervisor from that in the timeout supervisor upon an interruption request from the first timer; and if the waiting time stored in the timeout supervisor is shorter than the first cycle, the second cycle time is subtracted from the time stored in the timeout supervisor upon an interruption request from the second timer circuit.

Abstract: A communication method is provided to reduce an overhead of inter-processor synchronization for a communication phase in collective communication and to speed up the collective communication. Each of processors in a parallel computer start a previous process before a collective communication phase in which communications are performed at a same time among the processors through a inter-processor network. Each processor executes a synchronization command in advance at a time when a portion of the previous process for a predetermined time t is left. The inter-processor synchronization control section transmits a synchronization completion notice to each processor, if a synchronization condition is met. For the period, each processor executes the previous process in parallel. Then, the plurality of processors enter the collective communication phase.

Abstract: An electronic device is adapted to be connected to a plurality of peripheral devices, and includes a storage unit and a control circuit. The storage unit records a preset time and a control list. The control list lists at least a selected one of the electronic device and the peripheral devices, and an operation mode therefor. The control circuit detects whether the preset time matches a reference time, and if so, controls operation of the selected one of the electronic device and the peripheral devices according to settings in the control list.

Abstract: A method and memory device for generating a time estimate are provided. In one embodiment, a memory device generates a time estimate from time stamps in file system metadata for a plurality of files stored in the memory device and uses the time estimate to perform a time-based activity in the memory device. In another embodiment, a memory device generates a time estimate from time stamps stored in a plurality of files stored in the memory device and uses the time estimate to perform a time-based activity in the memory device. In yet another embodiment, a memory device obtains a plurality of time stamps, selects one or more of the plurality of time stamps based on validity rankings, generates a time estimate from the selected time stamp(s), and uses the time estimate to perform a time-based activity in the memory device.

Abstract: A method of using a counter stored in flash memory includes providing a base value field, a selector field, and a plurality of increment fields. The base value field represents a base value for the counter, and the selector field indicates a first one of the increment fields. The method further includes changing a bit of the first increment field from an erased value to a written value to indicate a change in a value stored in the counter.

Abstract: A token calculates a one time password by generating a HMAC-SHA-1 value based upon a key K and a counter value C, truncating the generated HMAC-SHA-1 value modulo 10^Digit, where Digit is the number of digits in the one time password. The one time password can be validated by a validation server that calculates its own version of the password using K and its own counter value C?. If there is an initial mismatch, the validation server compensate for a lack of synchronization between counters C and C? within a look-ahead window, whose size can be set by a parameter s.

Abstract: A network notifying device applied to a first network device is provided, where the first network device is coupled to a second network device, and the network notifying device includes an interface control circuit, a clock generator and a counter. The interface control circuit is coupled to the second network device, and stores a notify command. The clock generator is utilized for generating a clock signal. The counter is coupled to the interface control circuit and the clock generator, and the counter counts the clock signal to periodically generate a trigger signal to the interface control circuit to trigger the interface control circuit to transmit the notify signal to the second network device. In addition, operations of the clock generator and the counter are independent from a processor of the first network device.

Abstract: A clock generation device comprises a clock generation unit, a counter, a common factor calculation element, a first frequency divider, a phase-locked loop (PLL) and a second frequency divider. The counter receives a clock signal from the clock generation unit and a periodic signal from a USB host, and outputs a count value. The common factor calculation element calculates the common factor of the count value and a value to output a first adjustment value and a second adjustment value. The first frequency divider divides the frequency of the clock signal by the first adjustment value to output a reference signal. The second frequency divider divides the frequency of the output clock signal of the PLL by the second adjustment value to obtain a feedback signal input to the PLL. Based on the reference signal and the feedback signal, the PLL outputs a clock signal complying with the USB specification.