Abstract: A method and mechanism for generating a clock signal with a relatively linear increase or decrease in clock frequency. A first clock signal is generated with a first frequency which is then used to generate a second clock signal with a second frequency. The second frequency is generated by dropping selected pulses of the first clock signal. Particular patterns of bits are stored in a storage element. Bits are then selected and conveyed from the storage element at a frequency determined by the first clock signal. The conveyed bits are used to construct the second clock signal. By selecting the particular pattern of bits selected and conveyed, the frequency of the second clock signal may be determined. Further, by changing the patterns of bits within the registers at selected times, the frequency of the second clock signal may be made to change in a relatively linear manner.

Abstract: It is one objective of the present invention to limit the frequency whereat a user can display or reproduce digital content data, such as photograph data or music data, and instead, to reduce the price of such digital content data and accelerate its sale via the Internet. According to the present invention, an information processing apparatus comprises: a reception unit, for externally receiving, via a network, a content data file to which an encrypted life counter has been added; a processor, for processing the content data file; a subtraction unit, for subtracting a specific value from the encrypted life counter; and a controller, for inhibiting the processing means from processing the content data file when the value held by the encrypted life counter has been reduced to a value smaller than the specific value.

Abstract: A clock data recovery system is provided for resampling a clock signal according to an incoming data signal stream. It comprises a clock generator for generating said clock signal wherein one of the frequency and phase of that clock signal is dependent upon a control signal. It is further provided a phase detector operable to detect the phase difference between said clock signal and said incoming data signal stream and is operable to generate a phase difference signal. A loop controller has a variable-gain and is operable to control said clock generator by generating said control signal. That control signal is dependent in said phase difference signal and that variable-gain. The variable-gain is dependent upon a transition rate of the incoming data signal stream. The loop controller can comprise a low-pass filter to generate from the phase difference signal a low-pass filered phase signal and to adjust the bandwidth of the clock data recovery system.

Abstract: In the Retirement Payload Array (RPA) of a microprocessor, the signal “READ” is logically combined with the primary clock signal “CLK” in a control circuit of a modified glitch latch such that the glitch latch will only reset, and therefore a reset edge or “glitch” will only appear, when new data is read and the signal IN will return to zero and allow the modified glitch latch to recover.

Abstract: In a system where a plurality of mobile terminals shares a data of the server, upon issuing an update request data of server from the mobile terminals, without depending on the stability of the communication method used by the mobile terminals, a fair data updating becomes possible which only relies on an issuing order of the update request. In the present system, the clock module is provided to all the mobile terminals and the server having a synchronized time. The mobile terminal adds the update request issuing time obtained from the timing module to the update request data upon issuing the update request data, and the update request data is repeatedly sent until the server receives it. During the repeated transmission, an issuing time attached to the update request is identical to the original issuing time, and the server processes the data update request received within the update request reception period in an order of the issuing time.

Abstract: A system and method for initializing and resetting a clocking subsystem having a phased locked loop (PLL) within an input/output interface of a data processing system. A first timer generates signals in response to receiving clock signals from a clock source. A second timer detects the presence or absence of signals from the first timer and in response to an absence outputs a circuit reset signal to a circuit. The circuit in turn issues a reset signal to the PLL and to other systems.

Abstract: A system and method for monitoring a host computer using a service processor is provided. A shared nonvolatile random access memory (NVRAM) area is used to store progress information from the host computer system. The host computer system writes progress information corresponding to the initialization step being performed to the shared NVRAM and also updates a host pointer in the NVRAM. The service processor reads the shared NVRAM and compares its pointer with the host pointer to determine whether new host initialization activity has been reported. The service processor sets a timer so that if host activity is not reported during a set amount of time an error condition occurs causing the service processor to handle the host computer error. An optional service processor routine determines whether the host computer is stuck in an initialization loop whereupon the service processor once again handles the host computer error.

Abstract: A circuit has at least one data input, an enable input, a clock input, and an output. In one embodiment, the circuit is configured to perform a pre-charge function before an evaluate function in response to the enable input.

Abstract: In a network environment, a first master timing generator generates a first frame reference signal and a second master timing generator generates a second frame reference signal. A first data source generates a first data source signal, a first frame source signal, and a first clock source signal in response to a selected one of the first and second frame reference signals. Similarly, a second data source generates a second data source signal, a second frame source signal, and a second clock source signal in response to a selected one of the first and second frame reference signals. A timing recovery circuit generates a recovered reference signal and a recovered clock signal in response to a selected one of the first and second frame reference signals. A phase aligner stores the first data source signal in response to the first frame source signal and the first clock source signal.

Abstract: An application specific integrated circuit (ASIC) employs various logic blocks. The blocks may include logic circuits that operate at different clock rates. Consequently, an interface logic block may be needed to efficiently transfer signals from one frequency clock domain to another. One such interface, known as a universal asynchronous boundary module (UABM) is situated between the two domains allowing communication between the logic circuits.

Abstract: A device is presented including a host controller to generate a transaction schedule. The transaction schedule includes many transactions. The transactions are stored in many data structures. Each of the data structures contain initialized transactions or initialized and non-initialized transactions. The host controller executes the transactions that are initialized and the data structures each contain a pointer to the next initialized transaction.

Abstract: A computer system may include a host computer system and a storage device such as a tape device that includes one or more tape drives. The host computer system may be configured to provide commands to the storage device and to initiate a timeout period for each command provided to the storage device. The host computer system may be configured to initiate a first timeout period if a first type of command is provided to the storage device, to initiate a second timeout period if a second type of command is provided to the storage device, and to initiate a third timeout period if a third type of command is provided to the storage device, where the first timeout period, the second timeout period, and the third timeout period each have a different duration.

Abstract: A method including frequency dividing a high-frequency clock signal into a divided frequency, and further dividing the divided frequency into another divided frequency in accordance with a data input (DIN).

Abstract: A device for synchronizing processes which run on a plurality of units including a central unit linked with other units via a field bus, includes a device provided in the central unit for producing a system clock, the field bus having a vacant line for distributing the system clock to the other units, and respective multiplication devices located at the other units for multiplying the system clock; and a method of operating the device for synchronizing processes.

Abstract: An apparatus for immediately outputting a response of a synchronous system to an asynchronous event includes an advanced calculation device by means of which the responses of the synchronous system to possible asynchronous events can be calculated in advance. Also, a switching device is included by means of which the output signal from the advanced calculation device or the output signal from the synchronous system can be passed on selectively. It is thus possible to output responses from synchronous systems to asynchronous events immediately after such events occur.

Abstract: Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits.

Abstract: A clock monitoring apparatus according to the invention including a main clock monitoring portion including a first counter for counting a main clock, issuing a normal operation confirming flag indicating that a normal operation is being carried out when the first counter is overflowed or reaches a previously determined set value, monitoring the normal operation confirming flag by a sub clock, issuing a first main clock stop flag having an output in correspondence with H (high level)/L (low level) of the normal operation confirming flag and a main clock initializing signal for initializing the main clock when the main clock is determined to stop and resetting the first main clock stop flag when the main clock is recovered by receiving the main clock initializing signal, and a sub clock switching control portion including a second counter for counting a signal output produced by calculating a logical sum of the sub clock and the first main clock stop flag at fall of the sub clock at a time point of generating

Abstract: A method, system, and device capable of generating one or more clocks internally to detect, sample, and receive synchronous data streams and eliminate the need for corresponding external synchronization clocks for each data stream. One aspect of the clock generator provides a two-stage interpolation system. In a first stage, two clocks are selected which accurately detect a calibration data sample. In a second stage, a single, fine-tuned, clock is synthesized by interpolating the two selected clocks.

Abstract: A method and apparatus for generating a delay in the timing of a bus or other logic circuit such that changes may be made to timing parameters without undue hardware design changes is disclosed. A counter is used to count a number of clock cycles to time the delay. The number of clock cycles is pre-loaded into the counter from a memory. This eliminates the need for costly hardware design changes when timing parameters change, since all that must be changed is the number of clock cycles to be counted, which can be modified by replacing or reprogramming the memory.

Abstract: An apparatus comprising a first plurality of parallel switches and a second plurality of parallel switches. The first plurality of parallel switches may be configured to control a voltage on a first output pin. The second plurality of parallel switches may be configured to control a voltage on a second output pin. The first and second pluralities of parallel switches may be configured to provide rise time control of a differential waveform and be driven by a phased data signal.

Abstract: A setting value is initially stored in a comparison and coincidence register. Thereafter, a value of a count signal is incremented in a base timer while resetting the value of the count signal to zero each time the value of the count signal reaches a prescribed value. A coincidence signal set to “1” is output from the comparison and coincidence register each time the setting value agrees with the value of the count signal, and a clock signal is produced in an RS flip-flop according to the coincidence signal. A data transmission is performed each time the coincidence signal is received in a transmission shift register. On a reception side, the clock signal is received, and the data is received according to the clock signal. Therefore, in cases where a desired setting value is stored in the comparison and coincidence register, the repetition period of the data transmission and reception can be freely changed.

Abstract: A disk storage system has high throughput between a disk adapter of a disk controller and a disk array. The disk adapter of the disk controller is connected to the disk array through switches. Data on a channel between the switch and a RAID group is multiplexed in the switch to be transferred onto a channel between the switch and the disk adapter and data on the channel between the switch and the disk adapter is demultiplexed in the switch to be transferred onto the channel between the switch and the RAID group. A data transfer rate on the channel between the disk adapter and the switch is made higher than that on the channel.

Abstract: The present invention is related to a method and apparatus for managing memory in a network switch, wherein the memory includes the steps of providing a memory, wherein the memory includes a plurality of memory locations configured to store data therein and providing a memory address pool having a plurality of available memory addresses arranged therein, wherein each of the plurality of memory addresses corresponds to a specific memory location. The method further includes the steps of providing a memory address pointer, wherein the memory address pointer indicates a next available memory address in the memory address pool, and reading available memory addresses from the memory address pool using a last in first out operation. The method also includes writing released memory addresses into the memory address pool, adjusting a position of the memory address pointer upon a read or a write operation from the memory address pool.

Abstract: An embodiment of a digital recording apparatus real-time clock is disclosed. In particular, a real-time clock to mark when each recording is taken is described. The embodiment comprises a digital recording apparatus that contains a real-time clock powered by the main battery of the digital recording apparatus. The real-time clock resets when the digital recording apparatus's batteries are removed. When a recording is made, the digital recording apparatus marks the recording with the current value of the real-time clock, e.g., seconds since the batteries were changed. A computer then reads the media recorded by the digital recording apparatus and provides a date and time reference to which to relate the digital recording apparatus's real-time clock.

Abstract: A real time based system and a method for monitoring the same are disclosed, in which applications in operation are monitored by a system monitoring module at a constant time period to detect whether they operate abnormally. The system monitoring module detects whether all the applications currently in operation are controlled normally, so that it is possible to effectively detect any abnormal status of the system in the real time environment. Thus, reliability of the real time based system can be improved.

Abstract: A method of determining a transfer speed of an encoded data signal including a clock signal and a data signal is provided. First, the encoded data signal is decoded to generate a decoded clock signal. Then, a data transfer speed of the encoded data signal is determined using the decoded clock signal.

Abstract: A network traffic shaper includes a traffic shaper table for storing traffic specifiers, such as permissible data transmission rates, an arithmetic logic unit (ALU), and a high-speed forwarding trigger mechanism having at least one time-searchable data structure or queue and a retrieve time generator that substantially tracks, but never exceeds, a system time. As network messages are received, they are stored at a message buffer and certain message parameters, including message length and a corresponding traffic specifier, are provided to the traffic shaper. The traffic shaper determines when the message may be sent in accordance with the associated traffic specifier and stores this transmission start time along with the message's buffer location in the time-searchable queue of the forwarding trigger. The forwarding trigger continuously examines the transmission start times for previously stored messages.

Abstract: The burden of developing a complex bridge block imposed on the IP reuser is reduced by introducing a system clock into the IP. The IP composed of a functional circuit of this invention and its synchronizing circuit takes in the system clock by integrating the synchronizing circuit taking in the system clock with the IP functional circuit into the IP in reusing the IP complying with the standard in the development of an LSI with a built-in IP and its derivatives. This enables the reuser to incorporate the IP into the LSI via a simple bridge block, taking into account only the system clock for driving the system bus, which reduces the burden of handling the IP and increases the reusability of the IP.

Abstract: An apparatus comprising a counter circuit, a first register circuit, a second register circuit and an output circuit. The counter circuit may be configured to generate a count signal in response to a data input signal and a first clock signal operating in a first clock domain. The first register circuit may be configured to generate a first control signal in response to the count signal. The second register circuit may be configured to generate a second control signal in response to the data input signal. The output circuit may be configured to generate a data output signal operating in a second clock domain in response to the first control signal, the second control signal, the count signal, and a second clock signal.

Abstract: A method for verifying clock signal frequency of a sound interface of a computer system is disclosed. The processes include steps of initializing and setting a DMA controller and the sound interface, starting DMA data transfer, resetting a time out counter. During the DMA data transfer, a step of incrementing the time out counter is performed until the selected DMA channel of the DMA controller reaches a terminal count condition. After each increment, it is checked if DMA data transfer is time out. When the DMA channel of the DMA controller reaches the terminal count condition, the current count of the time out counter is compared with a maximum tolerable count and a minimum tolerable count. If the count of the time out counter is between the maximum and minimum tolerable counts, a message indicating the clock signal frequency of the sound interface is correct is issued, otherwise a message indicating the clock signal frequency is incorrect is issued.

Abstract: Disclosed is a method and a computer circuit design for a dynamic clock ratio detector. The detector is used to determine the ratio between two clock domains. The detector has a driver 101 and a receiver, which reside in different clock domains. The driver 101 constantly produces a ratio clock pulse to the receiver. The ratio-counter in the receiver counts the pulse width based on its local clock cycles. The clock ratio detector has many features, including absorbing the meta-stability effect when the pulse crosses an asynchronous interface. The clock ratio detector prevents output counts oscillation, provides an adjustable ratio-detecting coverage range, a programmable system-parameter generator 104, and a programmable error reporter 105.

Abstract: A data transfer method allowing improved data transfer speed without increasing the number of signal lines is disclosed. After dividing data to be transferred into odd-numbered data and even-numbered data, the odd-numbered data are sequentially read at timing of a leading edge of each clock pulse and the even-numbered data are sequentially read at timing of a trailing edge of each clock pulse. Thereafter, a data transfer completion indicator is appended to one of the odd-numbered and even-numbered data strings. A transfer clock signal includes a fixed-level pulse in a period of time corresponding to the data transfer completion indicator. The one of the odd-numbered and even-numbered data strings followed by the data transfer completion indicator, the other of the odd-numbered and even-numbered data strings, and the transfer clock signal are transferred through different signal lines.

Abstract: Methods, devices, and systems for monitoring the status of a computer through a driverless device node port, such as a universal serial bus port or P/S 2 port, are disclosed. A driverless device node is emulated and presents a message to the operating system of the computer through the device node port. The message requires a response from the operating system, and the time taken for the response to be generated is detected. From the detected time, the status of the computer can be found. A status indication may be transmitted from a remote management device emulating the driverless device node to a remote management computer so that the condition of the computer can be monitored remotely.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to wake-up the second circuit in response to an input signal. The input signal generally comprises a programmable delay value.

Abstract: Methods and apparatus are disclosed herein for providing tri-state noise immunity for memory systems such as DDR memory systems, wherein 1) there are large variations in read data loop delay, and 2) strobe buses have similar termination and threshold voltages. In one embodiment, strobe receiver circuitry includes a counter and counter control logic. The counter updates a count in response to strobe edges of received strobe signals. The counter control logic enables the counter before each strobe signal is received by generating control signals asynchronously with respect to the received strobe signals. The counter control logic also resets the counter after each strobe signal is received by receiving feedback from the counter and, in response to the feedback, resetting the counter asynchronously with respect to the received strobe signals. The strobe receiver circuitry may form part of a DDR memory controller.

Abstract: The invention concerns a method of checking the synchronization between at least two nodes Ni?1, Ni, with i=1, . . . , n in a network, each of said nodes having respectively an internal clock having a respective clock frequency Fi?1, Fi, wherein said method includes the following steps: a) transmitting the frequency Fi?1 of the internal clock from the node Ni?1 to the node Ni, b) comparing the frequency Fi?1 of the internal clock of the node Ni?1 transmitted to the node Ni with the frequency Fi of the internal clock of said node Ni, c) checking the synchronization between the nodes Ni?1 and Ni using the result of the comparison between the frequencies Fi?1 and Fi.

Abstract: An input signal with an associated pulse width can be sampled using a sampling method that does not require a clock signal. The input signal is compared to a reference level signal to produce a comparator output signal. Strobe signals are generated from the input signal, where the strobe signals occur within a pulse width of the input signal. Sampled data points are generated in response to the comparator output signal and the strobe signals such that the sampled data points are within the pulse-width of the input signal. One of the strobe signals may be used to periodically reset the comparator. The sampling logic circuit may be constructed from common logic gates and memory circuits such as flip-flops. In one example application the sampling method is applied to an equalizer system. The equalizer system includes an equalizer circuit that produces an equalized signal. A data slicer circuit converts the equalized signal into a digital representation.

Abstract: A timing adjustment device, method and chip for a bus interface. Through repetitive adjustment of the amount of phase shift in the clocking signal to the bus interface, read/write testing of the bus interface and checking for the correctness of the read/write data, suitability of the phase shift in the memory bus clocking signal for operating normally is determined. Hence, a safety range for the amount of phase shift in the bus interface timing signal is found and the phase shift of the bus interface timing signal is set to the mid-point of the safety range. The method may also be applied to a system bus and the timing adjustment of signals between a control chipset bus and a memory bus.

Abstract: A method, comprising the steps of receiving a timeout setting, determining a selected timer unit of one of a first timer unit and a second timer unit, wherein a first set of slots is included in the first timer unit and a second set of slots is included in the second timer unit. The selected one of the timer units being determined by determining a maximum time period of the first timer unit based on a number of slots in the first set of slots and a granularity which defines a relationship between each slot in the first set of slots, comparing the timeout setting to the maximum time period of the first timer unit, and incrementing to the second timer unit if the timeout setting is greater than the maximum time period of the first timer unit. Determining one of the first slots and the second slots into which the timeout setting is to be inserted and inserting the timeout setting into the one of the slots.

Abstract: A computer system including a first repeater and a second repeater that is coupled to the first repeater. The computer system also includes a third repeater that is coupled to the first repeater. The first repeater contains a first arbiter that arbitrates transactions between the first repeater and the second repeater and also arbitrates transactions between the first repeater and the third repeater. The second repeater receives transactions from the first repeater and contains a second arbiter that predicts receipt of transactions from the first repeater to the second repeater.

Abstract: A method and apparatus for position dependent data scheduling for communication of data for different domains along a bus is provided. Having an awareness of the relative position of different domains along a bus, one embodiment of the invention schedules bus operations to allow data from multiple bus operations to be simultaneously present on the bus while preventing interference among the data. The invention is compatible with buses having a termination on one end and those having terminations on both ends. In accordance with one embodiment of the invention, bus operations are scheduled so that first data of a first bus operation involving a first domain are not present at domains involved in a second bus operation at times that would result in interference with second data of the second bus operation.

Abstract: An interface between synchronous and asynchronous data transfer includes a plurality of stages coupled to each other to form a pipeline for data transfer. The plurality of stages include a first stage which performs synchronous to asynchronous data transfer, at least one intermediate stage which performs asynchronous to asynchronous data transfer and a last stage which performs asynchronous to synchronous data transfer. A synchronous clock path propagates a timing signal across the plurality of stages to enable the first and last stages to perform operations when the timing signal is present at that stage.

Abstract: A method and device for the exchange of data in messages between at least two users which are connected by a bus system and have separate time bases, the messages containing the data being transmitted by the users via the bus system; and a first user, in a function as timer, controls the messages as a function of time in such a way that it repeatedly transmits a reference message, which contains time information regarding the time base of the first user, via the bus at a specifiable time interval; the at least second user forms its own time information, using its time base, as a function of the time information of the first user; a correction value is ascertained from the two pieces of time information; and the second user adapts its time information and/or its time base as a function of the correction value.

Abstract: Methods and systems for generating and synchronizing multiple clocks are disclosed herein that have extremely low skew across multiple channels and latency that is both minimal and well-defined. A phase-locked loop circuit generates a plurality of clock signals to synchronize channel circuits that receive core data streams. The channel circuits convert the core data streams into serial data streams. The phase-locked loop circuit or another phase-locked loop circuit generates a core clock signal for the registered transfer of the core data streams to the channel circuits. One or more of the plurality of clock signals may be distributed to the channel circuits by a register-to-register transfer.

Abstract: A value for a first counter is maintained. A value for a second counter based on a content of a non-volatile memory is maintained. Updates to the value for the first counter and to the value for the second counter are controlled.

Abstract: According to telecommunication standards relating to communication networks supporting an Asynchronous Transfer Mode (ATM), timing information relating to a Constant Bit Rate (CBR) service needs to be communicated between a source network entity and a destination network entity. Typically, the timing information is obtained by measuring a phase of an incoming CBR stream of bits at the source network entity against a synchronous standard, such as a master clock signal. However, where the stream of bits comprises multiplexed services, it is difficult to measure the phase of the parts of the stream of bits relating to a service of interest without first demapping or demultiplexing the stream of bits. Consequently, the present invention overcomes this difficulty by counting justification event amongst the stream of bits, the count of justification events corresponding to timing information relating to the service of interest.

Abstract: A timer management system and method for managing timers in both a synchronous and asynchronous system. In one embodiment of the present invention, a timer management system comprises an application program interface (API) for providing a set of synchronous functions allowing an application to functionally operate on the timer. The timer management system further comprises a timer database for storing timer-related information. Furthermore, the timer management system comprises a timer services for detecting the expiring of the timer. A handle function of the timer services allows an asynchronous application, i.e., application in a multi-task system, to synchronously act on the timer. That is, when a timer in a asynchronous system times-out, the handle function allows the asynchronous application to act on the expired timer without incurring an illegal time-out message.

Abstract: An apparatus for evaluating at least one timer in the event of a timeout condition in a system includes circuitry that generates an indication that certain system conditions have occurred, clock circuitry, enabled by the indication, that generates a timeout counter enable signal, and a number of timer units, coupled to the clock circuitry, where each of the timer units is incremented an incrementing signal and reset by a monitored signal that represents conditions in the system. The apparatus includes comparison circuitry coupled to the timeout units, such that when at least one of the timer units reaches a predetermined count, the count, or the maximum count reached to this point, of each of the timer units is stored.

Abstract: Methods and apparatus for enabling timeouts with arbitrary resolutions to be implemented are disclosed. According to one aspect of the present invention, a method for enabling a device driver to communicate with a processor in a computing system includes exchanging information between the device driver and a clock system, and exchanging information between the clock system and a cyclic system. Information is also exchanged between the cyclic system and the processor. Although the clock system indirectly exchanges information with the processor, the clock system does not directly exchange information with the processor. In one embodiment, the clock system includes a callout system and a system clock, and exchanging information between the device driver and the clock system includes exchanging information between the system clock and the callout system, and exchanging information between the callout system and the device driver.

Abstract: According to some embodiments, a local receive clock signal is adjusted.