Abstract: A virtual machine monitor, a virtual machine system and a clock distribution method thereof. The clock distribution method includes: distributing real clock resource to a Guest Operation System (GOS), and saving correspondence between said GOS and said real clock resource; intercepting an access operation of said GOS to a virtual clock resource; sending said access operation to the corresponding real clock resource according to said correspondence, and then performing a write operation, or injecting an interrupt of said real clock resource into a local Advanced Programmable Interrupt Controllers (APIC) of a virtual CPU of the corresponding GOS of said GOSs.

Abstract: The present invention relates to timer generation corresponding to a plurality of timer requests, etc. necessary for task processes of a CPU and achieves efficient timer generation. The present invention includes a count setting unit (register) presetting a timer value that should be set at the time of completion of counting in a counter (down counter) that counts down or up a lapse of time to achieve the start and switching of the timer operation even without a high-speed response in the CPU. In such a configuration, a CPU clock can be operated at lower speed and the reduction of the consumption currents can be achieved. The present invention is applied to various electronic apparatuses such as portable terminal apparatuses.

Abstract: Systems, methods, and other embodiments associated with synchronizing link delay is provided. In one example system, a system for synchronizing signal communication between a first electronic component and a second electronic component connected by one or more serial communication links comprises an offset logic configured to apply a selected offset to signal transmissions to cause a unidirectional delay between the first and the second electronic components to be synchronized for both directions of signal transmissions. A synchronization logic is configured to determine the uni-directional delay for signal transmissions between the first and second electronic components and configured to control the offset logic to apply the selected offset.

Abstract: Generally described, embodiments of the present invention are directed at reducing the power consumed by a CPU. In accordance with one embodiment, a method is provided that transitions the CPU into a reduced power state in response to a fetch operation being dispatched to an I/O device. More specifically, the method includes comparing the latency associated with recovering from a reduced power state with the time remaining before a timer expires. Then, a signal is generated that identifies a timer-specific reduced power state. The method aggregates signals received from different timers to identify a reduced power that is appropriate given all of the processing that is scheduled to be performed.

Abstract: A method of securely transferring data from a transmitter to a receiver which includes the steps of at the transmitter encrypting data which at least in part is based on timer information at the transmitter, to form a transmission word, transmitting the transmission word to the receiver, at the receiver decrypting the transmission word, validating the transmission word by comparing the transmitted timer information to predetermined information at the receiver; and when a valid transmission word is received adjusting the said predetermined information.

Abstract: A self-generated strobe signal generator generates a self-generated strobe signal for a peripheral device using a peripheral device selection signal and a clock signal, without using a conventional strobe signal for all of the peripheral devices. Using the self-generated strobe signal synchronized to the clock signal, a delay time of the conventional strobe signal due to a high fan-out capability requirement and a long path length may be reduced and an operating frequency of an entire system may be improved.

Abstract: A semiconductor device is composed of an oscillator circuit developing a clock, and an oscillation failure detect unit. The an oscillation failure detect unit is configured to obtain at least one count value through counting clock pulses of the clock, and to activate an oscillation failure detect signal in response to the at least one count value being out of a predetermined count value range.

Abstract: Methods and apparatuses for detecting an in-band reset using digital circuitry. A first counting circuit is coupled to receive a first clock signal and to generate output signals based on a number of cycles of the first clock signal. A second counting circuit is coupled to receive a second clock signal and the output signals from the first counting circuit. The second counting circuit generates output signals based on number of cycles of the second clock signal. A comparison circuit is coupled with to receive the output signals of the second counting circuit and to generate a reset signal if the output signals from the second counting circuit correspond to a pre-selected range.

Abstract: A clock diagnostics module, such as a state machine, integrated into an integrated clock controller monitors clock signals associated with the integrated clock controller and reports the status of the clock signals through a management bus, such as an SMBus. For instance, a counter integrated into the integrated clock controller counts clock signal cycles that occur in a management bus cycle and compares the clock signal with an expected value to determine the accuracy of the clock. A power on reset allows the management bus to read the clock diagnostics module in the event of clock controller failure.

Abstract: Identifying a transaction from a real time event stream having latency. A method of the invention receives events from the real time event stream where events define a plurality of transactions to be identified. Each of the transactions includes a first event and a second event; the first event has a first latency relative to the real time event stream and the second event has a second latency relative to the real time event stream. The first event is identified from the received real time event stream, and a time is record when the first event is received. The method determines a time period during which the second event occurs as a function of the first latency, the recorded time of the first event, and the second latency. The transaction having the first and second events is identified based on the determined time period of the second event.

Abstract: In a timer circuit mounted on a mobile communication terminal etc, a plurality of time measurements with different sets of measurement time are realized with measurement errors reduced, and the power consumption is reduced. The timer circuit includes a counter 101 that operates under a reference clock, a storage unit (time memory 102 and comparison register 103) that stores the timer timeout time corresponding to a time measurement request when receiving the time measurement request from a CPU 120, and a comparator 104 that generates an interruption signal to the CPU 120 when the time corresponding to the output value of the counter 101 is coincident with the timer timeout time stored in the storage unit.

Abstract: The method is applicable to the reception of data in the case of a digital transmission in which the pieces of data are transmitted by a unit of equipment A to a unit of equipment B with an accompanying clock signal HA. This accompanying clock signal transmitted by the transmitter equipment A is used by the receiver equipment B to sample the transmitted data. An alternation is effected at the receiver equipment B between a phase of operation during which the clock signal HA accompanying the data is replaced by a local clock signal HLS of the same frequency and a phase of operation during which the local clock signal is periodically re-synchronized with the accompanying clock signal. Means to implement the method are also disclosed.

Abstract: Cycle-accurate real-time clocks and methods to operate the same are disclosed. An example real-time clock comprises a first counter to count cycles of a selectively-operable clock, a multiplexer to select from at least an output signal associated with the first counter or a continuously-operating clock, and a second counter to count cycles of an output signal of the multiplexer.

Abstract: Some embodiments of the invention provide a training sequence that may be used in a deskewing process or a protocol to be implemented in a training sequence deskew. Embodiments may also comprise a training pattern that allows for header or frame alignment.

Abstract: Systems and methods for detecting a leading edge of a bus clock signal are disclosed herein. One edge detecting system includes a device for providing a bus clock and a processor clock, in which the processor clock is an integer multiple of the bus clock. The device for providing the clocks, however, does not provide a control signal that indicates the location of an edge of the bus clock. The system further includes a clock tree configured to distribute the bus clock and processor clock to multiple destinations, whereby the destinations receive the bus clock and processor clock delayed by an insertion time of the clock tree. The system also includes a processor having a device for detecting the leading edge of the bus clock delayed by the insertion time. Furthermore, a method is disclosed herein.

Abstract: The present disclosure describes using the JTAG Tap's TMS and/or TCK terminals as general purpose serial Input/Output (I/O) Manchester coded communication terminals. The Tap's TMS and/or TCK terminal can be used as a serial I/O communication channel between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC. The use of the TMS and/or TCK terminal as serial I/O channels, as described, does not effect the standardized operation of the JTAG Tap, since the TMS and/or TCK I/O operations occur while the Tap is placed in a non-active steady state.

Abstract: A method for time stamping a digital document is disclosed. The document originator creates a time stamp receipt using the document and the current time. The time stamp receipt is submitted to a time stamping authority having a trusted clock. The time stamping authority validates the time stamp receipt by comparing the time value specified in the time stamp receipt to the current time. If the time value specified in the time stamp receipt is within a predetermined time window, the time stamping authority cryptographically binds the time value and document, or the time value and some representation of the document, e.g., by signing the time stamp receipt with its private signature key.

Abstract: Embodiments of the invention relate to distribution of clocks to CPUs in processing cells of a multi-cell system. In an embodiment, each cell includes an interface, referred to as an agent. A plurality of interfaces, referred to as switches, together with the agents of the cells, connects the cells together. A clock source provides a clock to a switch, which replicates the clock and provides the replicated clocks to its ports. Each port of the switch, receiving a replicated clock, encodes this replicated clock and sends it over a link to each agent of a cell. Each agent of the cells, receiving an encoded clock, decodes this encoded clock, resulting in a decoded, or an extracted, clock. The agent then replicates the extracted clock and provides the replicates of the extracted clock to a plurality of CPUs of the cell. As a result, CPUs in all cells of the system receive clocks that all are synchronized to the clock provided by the clock source.

Abstract: A virtual computer system includes multiple timer emulators for emulating multiple virtual timers in a virtual machine (VM). A time coordinator keeps track of an apparent time that is provided to the multiple timer emulators for presentation to the VM through the virtual timers. In particular, the time coordinator ensures that timer events generated by the multiple timer emulators are presented to the VM in an appropriate sequence and with substantially appropriate relative apparent times. Also, when guest software reads a count from a virtual timer, the time coordinator ensures that the apparent time presented to the guest software is substantially consistent with the apparent times represented by preceding and succeeding timer events. When the apparent time falls behind the real time of the physical computer system, the time coordinator speeds up the apparent time until it catches up to the real time.

Abstract: A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a channelized timer for use in controlling the issuance of signals to the processor(s) or control logic (such as interrupts, descriptors, etc.) that that identify system-related functions for a plurality of channels. Using control registers to select an individual bit of a multi-bit counter, a timing interval pulse is provided for prompting signal generation that is otherwise subject to a minimum count requirement.

Abstract: A system and method are provided for periodically servicing a channel in a timer used for controlling events. The method services a channel in a fixed periodic cycle, and reads a first control word loaded in the channel to determine a timer operation. Then, a first data word in the channel is managed in response to the determined operation. In one aspect, a clock signal is supplied with a fixed period. Then, servicing the channel in a fixed periodic cycle includes: establishing a cycle having a first number of clock signals; and, servicing the channel for a second number of clock signals each cycle. If the timer includes a plurality of channels, then each channel is serially serviced in a single cycle.

Abstract: An apparatus and method for tracking coherence event signals transmitted in a multiprocessor system. The apparatus comprises a coherence logic unit, each unit having a plurality of queue structures with each queue structure associated with a respective sender of event signals transmitted in the system. A timing circuit associated with a queue structure controls enqueuing and dequeuing of received coherence event signals, and, a counter tracks a number of coherence event signals remaining enqueued in the queue structure and dequeued since receipt of a timestamp signal. A counter mechanism generates an output signal indicating that all of the coherence event signals present in the queue structure at the time of receipt of the timestamp signal have been dequeued. In one embodiment, the timestamp signal is asserted at the start of a memory synchronization operation and, the output signal indicates that all coherence events present when the timestamp signal was asserted have completed.

Abstract: Various methods, apparatuses and systems are described in which a skew delay time between communication lanes is determined. A data transfer path is established which includes two or more communication lanes in a communication link. A skew delay time is determined between the communication lanes of the communication link with respect each other with using a clock period of a input output circuit as a reference time.

Abstract: A method and apparatus for processing packetized data spanning multiple clock cycles includes at least one comparator, for comparing a present clock cycle count to a reference clock cycle count, wherein the reference clock cycle values may be anywhere within the packet and may be non-contiguous with other reference clock cycle values. At least one word recognizer, compares a presently clocked word to a reference word, and an output circuit provides an indication of a favorable word comparison that occurred in response to a favorable clock cycle count comparison.

Abstract: A clock interface for a media access controller in a programmable logic device is described. The media access controller includes a clock generator for providing a clock signal to configured configurable routing of the programmable logic device to obtain a loaded version thereof. The loaded clock signal is provided to a clock network of the media access controller and to a delay cell of the media access controller to obtain an indication of the loading by the user instantiated design.

Abstract: A method and apparatus are disclosed for detecting a presence of a device. Specifically, a method and a system are disclosed that may comprise providing a clock driver having a pair of differential clock signal lines capable of connection to a device, providing a presence detection signal for transmission through the pair of differential clock signal lines, determining whether the presence detection signal is received through the pair of differential clock signal lines, identifying the absence of the device if no presence detection signal is received through the pair of differential clock signal lines, identifying the presence of the device if the presence detection signal is received through the pair of differential clock signal lines, and notifying a system management module of the presence of the device.

Abstract: An information processing device, such as cellular phone, includes a first timer set for executing count processing applied to a preassigned first processing, a second timer set for executing count processing applied to the preassigned first processing, a display state determination unit configured to determine a display state of a display unit, and a timer switching unit configured to select and set the first timer for the preassigned first processing at a time when the display state determination unit determines that the display unit is in an “ON” state and to select and set the second timer for the preassigned first processing at a time when the display state determination unit determines that the display unit is in an “OFF” state.

Abstract: A system and method is provided for generating and using multiple synchronized local program timestamps in a media processing system. The system includes an input processor, one or more local timestamp insertion modules, one or more parsers, and an input buffer. Each local program timestamp module includes a clock reference recovery module, a local program clock synchronized to the system time clock of a program source, and a timestamp generator. The system also includes one or more processing modules such as record modules, transmission modules, and display modules. When a data packet is received by the media processing system, the local timestamp insertion module appends a timestamp to the data packet. The timestamp is based on the synchronized local program clock for the program associated with the data packet. The processing modules utilize the synchronized local timestamps and their associated local program clock in a variety of applications.

Abstract: Disclosed is a method for minimizing the buffer size of an elasticity FIFO queue when synchronizing data between two clock domains. Data communication is typically sent by a transmitter device to a receiver device. The transmitted data signal includes an embedded clock signal and null data characters, as specified by the data communication signal protocol. A null character indicates an empty data frame and is included as part of most standard communication protocols. An embodiment skips one or more null characters from the elasticity FIFO queue during a single clock cycle when it is detected that the write pointer is catching up to the read pointer. By skipping multiple null characters during a single write cycle, the read pointer is moved ahead by one or more queue locations and the write pointer is insured to not catch up to the read pointer for a wider variation in frequencies between a transmitter and receiver than is normally possible.

Abstract: An integrated circuit having a connection terminal for receiving an electric data carrying signal, a circuit for delivering a first clock signal having clock pulses sent after each falling edge of the electric data carrying signal and inside a data sampling window, a circuit for delivering a second clock signal having clock pulses sent only when the electric data carrying signal is at the high level, and a data processing circuit clocked by the second clock signal.

Abstract: A system, method and computer program product for calibrating a Time Of Day (TOD)-clock in a computing system node provided in a multi-node network. The network comprises an infrastructure of computing devices each having a physical clock providing a time base for executing operations that is stepped to a common oscillator. The system implements steps for obtaining samples of timing values of a computing device in the network, the values including a physical clock value maintained at that device and a TOD-offset value; computing an oscillator skew value from the samples; setting a fine steering rate value as equal to the opposite of the computed oscillator skew value; and, utilizing the fine steering rate value to adjust the physical clock value and correct for potential oscillator skew errors occurring in the oscillator crystal at the computing device.

Abstract: A method for transferring variable isochronous data and an apparatus therefor are provided. The method for transferring variable isochronous data includes the steps of (a) determining isochronous transfer to be terminated when the bus is in an idle state for a time interval which is larger than an isochronous gap period, (b) detecting a residual gap having a time interval which is larger than the time interval of an isochronous gap and smaller than the time interval of a subaction gap, (c) checking whether bandwidth for the transfer of isochronous data remains when the residual gap is detected in the step (b), and (d) transferring the isochronous data when it is determined that the bandwidth remains in the step (c).

Abstract: The invention relates to a method and an arrangement for recording an information signal with first copy protection information to a storage medium using recording means, the recording being performed according to first copy rules identified by the first copy protection information. The method comprises the steps of detecting said first copy protection information identifying said first copy rules, recording at least second copy protection information according to said detected first copy rules, said first and at least second copy protection information identifying a legality message to be interpreted by reading means, the at least second copy protection information changing within a predefined time interval after the change in said detected first copy rules according to an interpreting rule.

Abstract: A circuit and method are provided herein for monitoring the status of a clock signal. In general, the method may include supplying a pair of clock signals to a clock monitor circuit, which is configured for monitoring a status of one clock signal relative to the other. The status indicates whether the frequency of the one clock signal is faster, slower or substantially equal to the frequency of the other clock signal. Once determined, the status may be stored as a bit pattern within a status register, which is operatively coupled to the clock monitor circuit. This enables the status to be read by detecting a logic state of one or more bits within the status register.

Abstract: The clocks of remote computing devices are synchronized within a range of certainty through the determination of an upper bound and a lower bound around a reference time. A message from a computing device is propagated up a network tree of devices to a device having a reference time, which encodes the reference time and returns the message down the tree. Each receiving device can determine that the reference time could not have occurred before their transmission of the message, nor could it have occurred after their receipt of the return message. Cryptographic hashes can be used to guard against malicious computing devices. Alternate paths and scheduling of messages can be used to provide a narrower spread between the upper and lower bounds, and clock drift can be accounted for by increasing the spread over time.

Abstract: Provided are a method, system, and device to effectuate a transfer of data from one clock domain to another. In accordance with one aspect of the description provided herein, bits of data to be transferred are shifted in the first clock domain. The shifted bits of data to be transferred may be sampled in a second clock domain at a fixed time within each clock signal of the first clock domain. A stream of sampled bits may be output in the second clock domain. Additional embodiments are described and claimed.

Abstract: One embodiment of a method is disclosed. The method generates requests waiting for data to be loaded into a data cache including a first level cache (FLC). The method further receives the requests from instruction sources, schedules the requests, and then passes the requests on to an execution unit having the data cache. Further, the method checks contents of the data cache, replays to the requests if the data is not located in the data cache, and stores the requests that are replay safe. The method further detects the readiness of the data of bus clocks prior to the data being ready to be transmitted to a processor, and transmits an early data ready indication to the processor to drain the requests from a resource scheduler.

Abstract: Data is communicated through two separate circuits or circuit groups, each having clock and mode inputs, by sequentially reversing the role of the clock and mode inputs. The data communication circuits have data inputs, data outputs, a clock input for timing or synchronizing the data input and/or output communication, and a mode input for controlling the data input and/or output communication. A clock/mode signal connects to the clock input of one circuit and to the mode input of the other circuit. A mode/clock signal connects to the mode input of the one circuit and to the clock input of the other circuit. The role of the mode and clock signals on the mode/clock and clock/mode signals, or their reversal, selects one or the other of the data communication circuits.

Abstract: A method and system of cell timing distribution which greatly reduces the bus bandwidth required for transmission of cell timing information in a WCDMA base station. The system of the present invention comprises a timing control unit connected to several communication cells through transmission lines. Each communication cell comprises a timing generator which determines a local timing (sfn) according to a frame boundary signal and a timing difference (t_cell) parameter received from the timing control unit. The frame boundary signal indicates the starting boundary of the central base station (nodeB) timing, whereas the t_cell parameter represents the offset between the local cell timing and the nodeB timing. The timing generator is implemented using a finite state machine and a counter.

Abstract: A distributed system that uses distributed synchronized time to perform uncorrelated actions. A distributed system according to the present teachings includes a set of nodes each having a synchronized real-time clock. The nodes use the synchronized real-time clocks to trigger a set of uncorrelated actions from the nodes.

Abstract: The method is applicable to the reception of data in the case of a digital transmission in which the pieces of data are transmitted by a unit of equipment A to a unit of equipment B with an accompanying clock signal HA. This accompanying clock signal transmitted by the transmitter equipment A is used by the receiver equipment B to sample the transmitted data. An alternation is effected at the receiver equipment B between a phase of operation during which the clock signal HA accompanying the data is replaced by a local clock signal HLS of the same frequency and a phase of operation during which the local clock signal is periodically re-synchronized with the accompanying clock signal. Means to implement the method are also disclosed.

Abstract: A state machine circuit may be used to control a multiplexing circuit that selects and provides respective ones of multiple input clock signals to a clock-synthesizing circuit that generates a synthesized clock signal in response to such input clock signals. The state machine circuit may, for example, be configured so that the synthesized clock signal is a spread-spectrum clock signal and/or a clock signal having a nominal frequency that is greater than a nominal frequency of each of the input clock signals.

Abstract: A sample rate converter (SRC) is used to slave hardware devices to a master hardware device. A clock manager registers the time at each clock of each device, communicates with memory that stores the clock times, and reports correlations between each clock time and the time at a reference clock. The processing of a data stream can be slaved to one or more hardware devices. The processing of a wake up period can be slaved to the clock of the master hardware device by adjusting the wakeup period. Slaving of hardware devices to the master hardware device can also be accomplished by finding a correlation between the clock times in memory and the reference clock. Each correlation can be input into an SRC corresponding to each slave hardware device. Each SRC can then generate or consume a data stream at the actual rate of the corresponding slave hardware device.

Abstract: A memory module includes several memory devices coupled to a memory hub. The memory hub includes several link interfaces coupled to respective processors, several memory controller coupled to respective memory devices, a cross-bar switch coupling any of the link interfaces to any of the memory controllers, a write buffer and read cache for each memory device and a read synchronization module. The read synchronization module includes a write pointer, a read pointer and a buffer. The write pointer is incremented in response to the receipt of read data. The read pointer increments in response to coupling of the read data from the memory hub. A comparator compares the read pointer an the write pointer, and the comparison is used to adjust the memory timing.

Abstract: An information handling system including a local event timer operably associated with a management application interface is disclosed. The information handling system can also include a remote event timer accessible by a system management application. The remote event timer can be used relative to use of the local event timer. The information handling system can also include an event timer detection module operable to determine an availability of the local event timer relative to an operating system type. The event timer detection module can also initiate use of the local event timer, and disable use of the remote event timer in response to detecting a local event timer enabled operating system. A method and a chipset configured to be used by an information handling system are also disclosed.

Abstract: A method for controlling bi-directional data transfers in an electronic circuit is provided. The method involves when a first of at least two data signals is activated as an originating data signal prior to a second of the at least two data signals: allowing only a device associated with the first of the at least two data signals to be a signal source, and causing a device associated with the second of the at least two data signals to enter a receive state as a signal sink. The method further involves passing at least one bit of data from the signal source to the signal sink.

Abstract: A value representing a clock, such as a video clock, that is independent of the clock of a communication system, is encoded using the communication system clock and then sent with the video for subsequent recovery by a receiver. In particular, during an interval defined by the communication system clock, the number of video clock cycles is counted and sent to the receiver. The receiver recovers the video clock using the number of video clock cycles and the communication system clock.

Abstract: The invention relates to a controller for generating control signals (evload_o, odload_o, st_chgclk_o, clk_o , clkorfiford_i) synchronous with a continuous clock signal (clk_hr_i) input to it for a device (1) to be controlled synchronously with the clock signal (clk_hr_i), wherein the controller (SE) has: register means for registering at least one set signal (st_load_i, st_fiford_i), comprising a plurality of bit positions, counting means for counting edges of the clock signal (clk_hr_i) depending on one or a plurality of set signals respectively registered in the register means, and synchronization and output means for synchronizing a value counted by the counting means with the clock signal (clk_hr_i) and the registered set signal and outputting at least one of the control signals, wherein the register means, the counting means and the synchronization and output means are configured and connected to one another in such a way that the output control signal(s), depending on the respectively registered set si

Abstract: A method for generating a digital signal pattern at M outputs involves retrieving an instruction from memory comprising a first set of bits identifying a first group of N outputs that includes fewer than all of the M outputs, and a second set of N bits each corresponding to a respective output included in the identified first group of N outputs. For each of the M outputs that is included in the identified first group of N outputs, the signal at the output is toggled if the one of the N bits corresponding to that output is in a first state and is kept in the same state if the one of the N bits corresponding to that output is in a second state. For each of the M outputs that is not included in the identified first group of N outputs, the signal at that output is kept in the same state.

Abstract: The sleep watchdog circuit for asynchronous circuits of the present invention contains clock means, counting means with multiple trigger input function and a digital supply. When the circuit is in the normal operation state, a periodic reset or activity signal is present that will reset the watchdog counter. As a result the clock means will keep on running, and the digital supply is operating in “normal” mode. When the circuit is put into the “sleep/standby” state, the “activity” signal becomes inactive, and if no wakeup events occur before the counter is finished the clock means will be put to a halt and the digital supply changes into a low power mode.