Abstract: A method for operating a device (such as a printer) having a first interface (such as USB interface) connectable to a first computer and a second interface (such as an Ethernet interface) connectable to a second computer. A phase lock loop (PLL) circuit is obtained which is driven by a clock source, which is adapted for switching between operating at the first and second clock frequencies, and which is operatively connected to the first and second interfaces to provide a clock signal to the first and second interfaces. The PLL circuit is operated at the first clock frequency when the first interface is active and is operated at the second clock frequency when the second interface is active. A device includes the first and second interfaces, the PLL circuit, and the clock source.

Abstract: On the basis of a period of a timing signal, a signal propagation delay in a device unit, signal propagation delay in the timing signal bus and the data bus, and a setup time of another device unit or a device connected to the data bus, a timing at which noise caused by active connection of the first device to the data bus is propagated to the other device unit or the device is computed in a step of noise propagation computing, and on the basis of the timing computed in the step of noise propagation computing, a connection timing at which the first device unit is connected to the data bus. With thes two steps, a noise caused by active connection of a device unit does not affect other device units and devices connected to the same data bus.

Abstract: A method and apparatus for transferring data across a clock domain boundary is described. In one embodiment, a fixed relationship between a faster clock and a slower clock is maintained in the process of phase alignment to allow great flexibility in allowable combinations of slower clock and faster clock frequencies. In one embodiment, an encoded edge select word is generated once at system initialization and used thereafter to select edges of the faster clock on which to sample data that comes from the clock domain of the slower clock. The value of the encoded edge select word is based, in part, on the fixed relationship between the faster clock and the slower clock.

Abstract: A timekeeping system and method is provided for enabling users to graphically represent one or more activities, as well as the time that has been allocated to each. A graphical display uniquely identifies activities or events based on different visual indicators (e.g., colors), as well as a dimension (e.g., length, area, etc.) that visually represents the duration of the activities or events. At least one dimension of the visual indicator changes in real time to represent the elapsed time of an activity. A report module comprising a report generator and report editor is provided to enable users to account for and summarize the time that has been spent on various activities.

Abstract: Systems and methods of managing power provide for receiving notification of a pending power state transition and using coordination hardware to determine whether the power state transition in a primary device is permitted by a set of secondary devices. In one embodiment, the primary device shares a resource with the set of secondary devices.

Abstract: Methods and apparatus for producing an electronic ID number include modifying at least one physical bit element from among each of at least first and second groups of physical bit elements, each physical bit element of each group having a first physical state in which it is operable to produce a signal having a first electrical state, and being capable of permanent modification to a second physical state in which it is operable to produce a signal having a second electrical state; and producing (i) one bit of an identification (ID) number from the respective signals issuing from each of the respective at least first and second groups of physical bit elements, and (ii) a validity signal indicative of whether the one bit of the ID number is valid.

Abstract: An information processing device having low power consumption without affecting interruption request response speed. The device specifies a waiting time until execution of a given event and makes a system call and includes a first timer circuit for a first cycle; a second timer circuit for a second cycle shorter than the first cycle; a timeout supervisor which stores the waiting time; and a first cycle supervisor which stores waiting time until the next interruption request. The timeout supervisor stores the time calculated by subtraction of the waiting time stored in the first cycle supervisor from that in the timeout supervisor upon an interruption request from the first timer; and if the waiting time stored in the timeout supervisor is shorter than the first cycle, the second cycle time is subtracted from the time stored in the timeout supervisor upon an interruption request from the second timer circuit.

Abstract: A design method for a bus system comprising a noise propagation computation step and a connection timing computation step. Based on the cycle of a timing signal, a signal propagation delay in a device unit, signal propagation delays in a timing-signal bus and a data bus, and a setup time in the device unit or device connected on the data bus, the noise propagation computation step computes timing at which, when the device unit is connected on the data bus being active, noise propagates to other device units other than the connected device unit or to the device connected on the data bus. Based on the timing computed in the noise propagation computation step, the connection timing computation step computes connection timing at which the device unit is connected on the data bus.

Abstract: Apparatuses and methods for starting a mobile communications device are disclosed. The mobile communications device is operated by a device user. The device includes an output device for emitting a sensible signal. An input device receives user input from the device user. An alarm application receives an input time and date through the input device and determines an adjusted time and date. The adjusted time and date comprises the input time and date minus a predicted boot time for the device. The alarm application also causes the output device to emit the sensible signal at the input time and date. A system timer component monitors a current time and date when the device is in a low-power or off state and initiates a boot process when the current time and date match the adjusted time and date. The boot process is completed prior to the input time and date to enable the alarm application to cause emission of the sensible signal at the input time and date.

Abstract: A method of maintaining a count of active events of a process is provided by a start counter and a complete counter. The start counter maintains a first count of start events and may be operated upon only by the start event of the process. The complete counter maintains a second count of complete events and may be operated upon only by the complete event of the process. The count of active events is established by determining the difference between the first and second counts. The present invention further provides for re-setting the first and second counts of the start and complete counters, respectively, when one or both of the counters have reached a maximum count value.

Abstract: An apparatus and a method for controlling key events generated when handling a graphics object are provided. The apparatus includes an event-determining unit that determines a type of an event; an event-managing unit that determines execution of the event depending on the determined type of the event; and a count-checking unit that checks an event count that indicates a number of predetermined event occurrences and a number of times the graphics object has been handled, according to the request of the event-managing unit.

Abstract: The present invention discloses a circuit for generating a wait signal in a semiconductor device. Even if an address input enable signal is synchronized with a clock and continuously or irregularly inputted, the circuit for generating the wait signal in the semiconductor device generates the wait signal suitable for a latency counter by using the finally-inputted address input enable signal. In addition, the circuit for generating the wait signal in the semiconductor device generates the wait signals having various pulse widths to be suitable for various latency counters, and enables the object wait signal earlier than data input or output by one clock, or simultaneously with data input or output.

Abstract: Systems and methods are disclosed for timer architectures. For example, in accordance with an embodiment of the present invention, a timer system includes a prescaler and one or more timer cells each having a multiplexer and a counter.

Abstract: A memory module and an apparatus having a memory module for generating an internal clock synchronized to an external clock, the memory module being operated based on the internal clock as an operation clock and includes a first DLL circuit for generating a first internal clock from an external clock in a first frequency band, a second DLL circuit for generating a second internal clock from an external clock in a second frequency band different from the first frequency band, and a selector for selecting any of the first internal clock generated by the first DLL circuit and the second internal clock generated by the second DLL circuit, and outputting the selected clock as the operation clock of the memory module.

Abstract: Multiple data processing circuits may share a semiconductor memory circuit, such as double-data-rate synchronous dynamic random access memory (DDR-SDRAM). A data processing circuit (202-1 or 202-2) ending control of a semiconductor memory circuit (201) supplies a clock enable signal and chip select signal at predetermined levels. A data processing circuit (202-2 or 202-1) starting control of a semiconductor memory circuit (201) supplies a clock enable signal and chip select signal at the same predetermined levels, before the data processing circuit (202-1 or 202-2) ending control stops supplying a clock enable signal and chip select signal. Therefore, a clock enable signal and chip select signal do not enter an undefined state, and malfunctions that could otherwise occur are prevented.

Abstract: A method of controlling a semiconductor device using a microcomputer having a timer is provided. An interrupting step interrupts the semiconductor device using the timer, by generating a control signal for controlling a timing of turning on/off the semiconductor device. The interrupting step is performed in accordance with an interrupting signal which is input to the microcomputer at every occurrence of a predetermined period. The interrupting step comprises a setting step of giving a set value to the timer and a calculating step of determining a set value for a subsequent interrupting step, such that the set value determined in the calculating step is given to the timer in the setting step of the subsequent interrupting step. Therefore, a longer time can be allowed for determining a set value for the timer, and the processing speed required for the microcomputer can be reduced.

Abstract: The present invention relates to a data processing circuitry and method of processing an input data pattern and out-putting an output data pattern after a processing delay which depends on a processing activity of the data processing circuitry, wherein the processing delay is estimated based on the input pattern and the processing is controlled in response to the estimated processing delay. The processing control may be a power control based on an activity monitoring or a clock control in a pipeline structure. Thereby, an efficient solution is provided to derive the current activity of the processing circuitry in order to dynamically adapt its operating conditions to its demands.

Abstract: Lookback is defined as the ability of a logical process to change its past locally (without involving other logical processes). Logical processes with lookback are able to process out-of-timestamp order events, enabling new synchronization protocols for the parallel discrete event simulation. Two of such protocols, LB-GVT (LookBack-Global Virtual Time) and LB-EIT (LookBack-Earliest Input Time), are presented and their performances on the Closed Queuing Network (CQN) simulation are compared with each other. Lookback can be used to reduce the rollback frequency in optimistic simulations. The relation between lookahead and lookback is also discussed in detail. Finally, it is shown that lookback allows conservative simulations to circumvent the speedup limit imposed by the critical path.

Abstract: A frame boundary discriminator has a first input for receiving a high speed master clock signal having a multitude of master clock pulses within a frame, and a second input for receiving synchronized input frame pulses subject to jitter. An output frame pulse generator controlled by the high speed master clock signal generates output frame pulses. A control circuit for compares the timing of the synchronized input frame pulses with said master clock pulses and adjusts the timing of said output frame pulses to average out jitter in the input frame pulses.

Abstract: An apparatus and method is disclosed to compensate for skew and asymmetry of a locally processed system clock used to synchronize an output signal, e.g., a data signal or a timing signal, from a logic circuit, for example a memory device. A first phase detector, array of delay lock loop (DLL) delay elements and accompanying circuitry are disclosed to phase-lock the rising edge of the output signal with the rising edge of the system clock XCLK signal. Additionally, a comparator circuit, a register delay, an array of DLL delay elements and accompanying circuitry are disclosed to add or subtract delay from the falling edge of the DQ signal in order to produce a symmetrical output of the DQ signal.

Abstract: A fast data access circuit that has both a standard clock mode and a fast data access mode. The mode is selectable through a mode/configuration register. A configuration word loaded into the register has bits to indicate the desired mode and the input clock frequency. In the fast data access mode, a clock delay circuit uses the clock frequency setting bits to select a delay to be added to the input clock. The higher the clock frequency, the less the added delay. The delayed clock generates FIFO control signals to control a data FIFO register. During the fast data access mode, the data is output from the data FIFO register at a faster rate than in the standard clock mode.

Abstract: Disclosed are systems and methods for determining time-outs with respect to a plurality of transactions comprising utilizing a first time-out clock for simultaneously determining time-out states with respect to a first set of transactions of the plurality of transactions, and determining when transactions of the first set of transactions have reached a timed-out state of the time-out states.

Abstract: A simple and accurate processor derating method includes: sampling a real-time counter/clock too obtain an initial time value T1; resetting an Icnt Counter; incrementing the Icnt Counter to reflect the processing of each instruction; comparing the count in the Icnt Counter to a predetermined count IcntMax and if the count in the Icnt Counter is at least IcntMax, then sampling the RTC to obtain a second time T2. T1 is then subtracted from T2 to obtain a time difference DT which is multiplied by ((1?1/DF)?1) to obtain a Degradation Delay DD period, DF being a constant having a value which is the desired submodel performance with respect to full performance. The Degradation Delay is instituted, the RTC is sampled from time to time to obtain a test third time T3. When a test T3 minus T2 is not less than DD, then T1 is set to T3. Then, the procedure is repeated for a next group of instructions.

Abstract: The disclosed invention provides methods and systems for writing and reading data in systems using multiple FIFO buffer elements. For each buffer element, a determination is made of when the rising edge of the read clock occurs during the second half of the write clock cycle. Responsive to this determination, the data written into the FIFO buffer element is shifted in order to reduce skew.

Abstract: A clock generation system for generating a first-, a second-, and a third-reference frequency clocks having respective frequencies having predetermined ratios to the reference frequency of a reference clock, using PL circuits in such a way that the clocks have sufficient S/N ratios in spite of the S/N ratio limitation by the noise floor. A first reference frequency clock is supplied to a first PLL circuit to generate an intermediate-frequency clock having an intermediate frequency having a predetermined ratio to the reference clock. The intermediate-frequency clock is supplied to a second and a third PLL circuits to generate a second and a third reference frequency clocks having frequencies respectively having a second and a third ratios to the intermediate frequency, respectively.

Abstract: In an in-vehicle electronic control apparatus (ECU), when a microcomputer stops operation, a timer IC starts the count-up operation. When the count value reaches a preset value, a signal from the timer IC becomes high and a power supply voltage is outputted from a power supply IC to activate the microcomputer. The microcomputer reads the count value from the timer IC when it starts the operation. If such a count value has exceeded the specified value, the microcomputer determines occurrence of a failure. Therefore, if the timer IC cannot activate the power supply IC, the microcomputer can detect a failure upon activation with turning on of an ignition switch.

Abstract: A source synchronous scheme in which data from one clock domain is synchronized to a clock of a second clock domain. Using a more reliable clock of the second domain to control and adjust the alignment after the data is latched in allows more robust performance to maintain correctly ordered data. In this manner, a write pointer based on strobe signal(s) from the first clock domain may be avoided.

Abstract: An embodiment of the present invention includes a standby clock generator and a selector. The standby clock generator generates a standby clock synchronous to a core clock. The core clock is generated by a core clock generator during a normal operation mode. The core clock generator stops the core clock during a frequency transition. The selector generates a processor clock from the standby clock during the frequency transition from the normal operation mode according to a selector control signal.

Abstract: One or more derived timers based on a source timer are provided to accommodate a plurality of periodic tasks while maintaining the high resolution of the source timer. To accommodate a number of periodic tasks, a number of derived timers can be selected utilizing a novel method based on the number of periodic tasks that are most time-critical, the number of tasks that are less time-critical, and the number of tasks that can be performed during the source timer interval. The interval and start time for each derived timer is selected based the source timer and number of the derived timer. After establishing the derived timers, the most time-critical tasks can be assigned to the source timer and the less time-critical tasks arranged amongst the derived timers.

Abstract: Function circuits composing one function macro are divided and mounted on plural chips, plural internal clock signals having different phases with one another are generated based on a clock signal to be a reference, a phase of a clock signal supplied to the function circuits within the chips is adjusted based on a result of a test operation performed by using a selected internal clock signal, a clock signal with an optimal phase is obtained from among the plural internal clock signals having the different phases with one another, and a skew generated by being divided into the plural chips is adjusted automatically to thereby realize a proper operation of the circuits as a whole.

Abstract: The invention relates to a method for synchronizing a first clock C to a reference clock A, the first clock C being connected to said reference clock A via a processing unit B. The invention moreover relates to a processing unit B and to a synchronization system. In order to enable a synchronization of said first clock C to said reference clock A via said processing, unti B. it is proposed that the processing unit B generates a correction message cmsg for the first clock C based on timestamps exchanged between the processing unit B and the reference clock A, which exchanged of timestamps is triggered by clock pulses cclk received in the processing unit B from the first clock C.

Abstract: A master device communicating a first range of speeds at which the master device is operable, to a first slave device, the master device and the first slave device determining a second range of speeds most closely matched to the first range of speeds at which each of the master device and the first slave device is respectively operable; and the master device setting the operating range of speeds of each of the master device and the first slave device to the second target range of speeds.

Abstract: A method and apparatus for emulating a high-precision, high-accuracy clock. In one embodiment, two clocks are used in the emulation. The first clock has precision greater than precision of the second clock and accuracy less than accuracy of the second clock. A checkpoint time relative to elapsed cycles of the second clock and a checkpoint cycle count of cycles of the first clock are periodically stored relative to a checkpoint period that lasts for a selected number of cycles of the second clock. A reference cycle rate of the first clock is calculated relative to the cycle rate of the second clock. The current time is determined as a function of the checkpoint time, a number of cycles of the first clock elapsed since storing the most recent checkpoint cycle count, and the reference cycle rate of the first clock.

Abstract: A method for processing data is provided that includes receiving a clock signal at a source driver and communicating the clock signal to a plurality of destination receivers. The clock signal may be received at the destination receivers during a substantially equivalent time interval, the plurality of destination receivers being five.

Abstract: A method and system are provided for processing data packets at a data-transfer network node. The method and system include determining a length of time that a packet has been buffered at the node by associating a timer with each data packet received and buffered in the node's central queue. The central queue subsequently reads the associated timer to determine a length of time that a data packet has been buffered prior to the data packet being transmitted by the node. If a packet has been buffered too long, then the queue discards the packet. Otherwise, the queue permits transmission of the packet. The amount of circuitry in the switching node's central queue is reduced by locating the packet timers in timer logic external to the queue.

Abstract: A recording medium and a method and apparatus for managing data are provided. The method includes recording additional data in a data file separate from a file containing main data and recording navigation information that links the main data and the additional data. The additional data are segmented into a plurality of predetermined units, each of the predetermined units including time information indicating a presentation start time of the corresponding unit.

Abstract: A method, apparatus, and program storage device for providing clocks to multiple frequency domains using a single input clock of variable frequency. Independent clock signals are generated at predetermined clock frequency targets in response to control signals that are based on a determined bus clock frequency.

Abstract: An information processing unit has a system bus that connects devices configuring the information processing unit. An arbiter performs arbitration related to use of this system bus, and a clock control circuit controls the clock to be supplied to the devices. The clock control circuit can make a bus request to the arbiter and executes a clock switch or clock halt after being granted use of the bus by the arbiter.

Abstract: Embodiments of the present invention are described in an integrated circuit. The integrated circuit comprises circuit elements configured to be clocked via an oscillating signal, and a detector. The detector is configured to detect a state of the oscillating signal and provide a detection signal indicative of the state of the oscillating signal. The detector comprises a first delay line configured to provide a first delayed signal to logic that provides the detection signal.

Abstract: A method for transferring variable isochronous data and an apparatus therefor are provided. The method for transferring variable isochronous data includes the steps of (a) determining isochronous transfer to be terminated when the bus is in an idle state for a time interval which is larger than an isochronous gap period, (b) detecting a residual gap having a time interval which is larger than the time interval of an isochronous gap and smaller than the time interval of a subaction gap, (c) checking whether bandwidth for the transfer of isochronous data remains when the residual gap is detected in the step (b), and (d) transferring the isochronous data when it is determined that the bandwidth remains in the step (c).

Abstract: Methods, apparatus, systems, and articles of manufacture for maintaining virtual real time clocks (virtual RTCs) in a logically partitioned computer system are described. Changes made to a hardware real time clock (hardware RTC) while a partition manager is not running (or is not fully operational) are tracked. The cumulative effect of these changes on the hRTC value may be captured in a clock delta variable. For some embodiments, a service processor may be configured to track the changes to the hRTC while the partition manager is not running and generate the clock delta. Upon loading, the partition manager may utilize this captured clock delta to make adjustments to vRTCs, in an effort to preserve their integrity by compensating for the changes made to the hRTC while the partition manager was not running.

Abstract: In a microcomputer, a watch-dog timer and a sleep control timer share a counter in their signal generating circuits. In a normal operation mode, an AND gate is in a signal passing state and a reset signal RST can be outputted. In a sleep mode, another AND gate is in a signal passing state and a wake-up signal WKUP can be outputted.

Abstract: A frequency manager automatically selects a clock frequency for each device or bus, or for a plurality of devices or buses, in a system, based on various factors and objectives. These factors and objectives can include optimizing performance of the devices without exceeding the system's power/thermal budget. The frequency manager can then control circuits that generate and provide clock signals having the selected frequency(ies) to these devices or buses. For example, in a system that is less than fully populated with devices, embodiments of the invention can select higher clock frequencies than a fully populated system would utilize. Some embodiments of the invention select higher clock frequencies for high-bandwidth devices than for low-bandwidth devices. Other embodiments use information about application programs that will be executed by systems, such as which devices these application programs will frequently access, to select higher clock frequencies for the frequently accessed devices.

Abstract: A method and apparatus for operating a clock in a processor having asymmetrically mirrored base-mirror units is disclosed. The method includes initializing a base-unit and a mirror-unit of the processor to the same state, and starting the mirror-unit-clock one clock cycle later than the base-unit-clock.

Abstract: A key managing system including information transmitting apparatus which transmits a date and time when secrecy protection is ended to a key controlling apparatus. The key controlling apparatus searches a key control table for an encryption key associated with a decryption key and the date and time. The key controlling apparatus transmits an encryption key from the search to the information transmitting apparatus. The key controlling apparatus discloses a decryption key for the present date and time to an information receiving apparatus in response to a request for a decryption key. The information transmitting apparatus, upon receipt of the encryption key, encrypts information using the encryption key and transmits the encrypted information to the information receiving apparatus. The information receiving apparatus, for the present date and time matching with the date and time, acquires a disclosed decryption key and decrypts the encrypted information by using the decryption key.

Abstract: A method and apparatus for position dependent data scheduling for communication of data for different domains along a bus is provided. Having an awareness of the relative position of different domains along a bus, one embodiment of the present disclosure schedules bus operations to allow data from multiple bus operations to be simultaneously present on the bus while preventing interference among the data. The present disclosure is compatible with buses having a termination on one end and those having terminations on both ends. In accordance with one embodiment of the present disclosure, bus operations are scheduled so that first data of a first bus operation involving a first domain are not present at domains involved in a second bus operation at times that would result in interference with second data of the second bus operation.

Abstract: A data processing system 2 is provided which is responsive to program instructions that operate in a variable timing mode to require a variable number of processing cycles to complete. The system is also operable in a fixed timing mode, which may be programmable using a bit (or several bits) within a configuration controlling register, to operate in a fixed timing mode in which such instructions are forced to operate using a fixed number of processing cycles. Thus, suppression of instructions which fail their condition codes may be suppressed and early termination of program instructions similarly suppressed in a manner which helps resist an attack upon the security of the system by observing the number of processing cycles required to process certain data.

Abstract: One or more programmable clock management components of an apparatus in one example are coupled with a backplane. The one or more programmable clock management components comprise a reconfigurable clock management component. Upon receipt of one or more control signals, the reconfigurable clock management component undergoes a reconfiguration to be able to process one or more frequency signals.

Abstract: A method for entering test mode of an integrated circuit device is disclosed. In one embodiment of the present invention, after a lockout period, a test controller generates a signal indicating the integrated circuit is willing to enter the test mode. After the signal, the test controller monitors a test interface during a predetermined period of time for a digital password. Then, in response to a valid password being received within the predetermined period, the test controller enters the test mode. In another embodiment, in addition to the above steps, in response to the valid password being received, the test controller generates an acknowledge signal. In one embodiment, the predetermined period of time takes place during a holdoff period after the lockout period. In another embodiment, the test interface is serial.

Abstract: A single wire serial interface for power ICs and other devices is provided. To use the interface, a device is configured to include an EN/SET input pin. A counter within the device counts clock pulses sent to the EN/SET input pin. The output of the counter is passed to a ROM or other decoder circuit. The ROM selects an operational state for the device that corresponds to the value of the counter. In this way, control states may be selected for the device by sending corresponding clock pulses to the EN/SET pin. Holding the EN/SET pin high causes the device to maintain its operational state. Holding the EN/SET pin low for a predetermined timeout period resets the counter and causes the device to adopt a predetermined configuration (such as off) until new clock pulses are received at the EN/SET pin.