Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for dynamic load balancing for multi-core computing environments. An example apparatus includes a first and a plurality of second cores of a processor, and circuitry in a die of the processor separate from the first and the second cores, the circuitry to enqueue identifiers in one or more queues in the circuitry associated with respective ones of data packets of a packet flow, allocate one or more of the second cores to dequeue first ones of the identifiers in response to a throughput parameter of the first core not satisfying a throughput threshold to cause the one or more of the second cores to execute one or more operations on first ones of the data packets, and provide the first ones to one or more data consumers to distribute the first data packets.

Abstract: A device for disabling faulty cores using proxy virtual machines includes a processor, a faulty core, and a physical memory. The processor is responsible for executing a hypervisor that is configured to assign a proxy virtual machine to the faulty core. The assigned proxy virtual machine also includes a minimal workload. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: An exemplary computing device comprises an in-band processor and an out-of-band controller. The exemplary computing device also comprises a machine check architecture that includes a pipeline and a plurality of error detectors. The error detectors are configured to detect errors that occur in a plurality of circuits and report the errors to the in-band processor and the out-of-band controller via the pipeline. Various other devices, systems, and methods are also disclosed.

Abstract: Setting a primary server within a business density cluster when the business density location changes. A new primary edge provisioning server replaces a current primary edge provisioning server when the business density cluster is determined not to include the current primary edge provisioning server. An edge provisioning framework handles the associations and dissociations of the edge network(s) to build the new primary server within the business density cluster. The former primary server is respawned as a new secondary node to the new primary server.

Abstract: A semiconductor device includes a data path having a plurality of processor elements, a state transition management unit managing a state of the data path, and a parallel computing unit in which an input and an output of data is sequentially carried out, and an output of the parallel computing unit is capable of being handled by the plurality of processor elements.

Abstract: The present disclosure discloses a processor. The processor is used to perform parallel computation and includes a logic die and a memory die. The logic die includes a plurality of processor cores and a plurality of networks on chip, wherein each processor core is programmable. The plurality of networks on chip are correspondingly connected to the plurality of processor cores, so that the plurality of processor cores form a two-dimensional mesh network. The memory die and the processor core are stacked vertically, wherein the memory die includes a plurality of memory tiles, and when the processor performs the parallel computation, the plurality of memory tiles do not have cache coherency; wherein, the plurality of memory tiles correspond to the plurality of processor cores in a one-to-one or one-to-many manner.

Abstract: A method, computer program product, and computer system are provided for supporting lossless transitions between interruption and polling mode of a resource. In response to a state variable setting or a timed trigger, launching a task to process replies for a resource. The task processes each ready reply for each resource. A timed trigger is established to relaunch the task based on the task executing in polling mode. The task is exited.

Abstract: The present disclosure relates to a method and apparatus for determining a relative energy between systems, an electronic device, a computer-readable storage medium, and a computer program product. The method includes: for a chemical system, performing a plurality of iteration rounds using a neural network variational Monte Carlo method; acquiring a linear relationship between energy errors and energy variances, which are obtained in the plurality of iteration rounds; determining a first energy error at a position where the energy variance is zero based on the linear relationship; and determining the relative energy between the chemical system and a further system based on the first energy error.

Abstract: A fault management system (FMS) receives events indicating an issue with a component in the system and determines, based on an inventory database, the component associated with the events. The FMS creates, based at least in part on the events, an error report that includes: (i) an error type identifying a type of error described in the error report, (ii) a timestamp indicating when the error report was created, and (iii) a universal unique identifier (UUID) to uniquely identify the error report. The FMS determines, based at least in part on the error report, a policy associated with the events and classifies the events, based at least in part on the policy, as either a threshold event or a discrete event. The FMS performs one or more actions to address the events.

Abstract: A controller is a controller forming, with another controller, a redundant controller. The controller includes a communication function unit that performs communication with an external device capable of executing control calculation needed for process control for a plant, and a redundancy management unit that switches states of the controller between an active state where a result of the control calculation obtained from the external device via the communication function unit is reflected in the process control and a standby state where the result of the control calculation is not reflected in the process control. The redundancy management unit switches the states of the controller to bring one of the controller and the another controller into the active state.

Abstract: A hybrid scheme is provided for performing translation lookaside buffer (TLB) shootdowns in a computer system whose processing cores support both inter-processor interrupt (IPI) and broadcast TLB invalidate (TLBI) shootdown mechanisms. In one set of embodiments, this hybrid scheme dynamically determines, for each instance where a TLB shootdown is needed, whether to use the IPI mechanism or the broadcast TLBI mechanism to optimize shootdown performance (or otherwise make the TLB shootdown operation functional/practical).

Abstract: A computing system includes (1) a primary processor executing executable instructions and generating first instruction data associated with the executable instructions, (2) a secondary processor executing the executable instructions one or more clock cycles behind the primary processor and generating secondary instruction data associated with the executable instructions, (3) a first first-in first-out (FIFO) buffer for the primary processor, (4) a second FIFO buffer for the secondary processor, (5) circuitry storing at least some of the first instruction data in the first FIFO buffer and at least some of the second instruction data in the second FIFO buffer, (6) compare circuitry comparing a first portion of first instruction data and a second portion of second instruction data that are associated with a given clock cycle, and (7) control circuitry halting the primary and secondary processors responsive to a mismatch between the first portion and the second portion.

Abstract: Systems and techniques that facilitate quantum circuit valuation are provided. In various embodiments, a system can comprise an input component that can access a first quantum circuit. In various embodiments, the system can further comprise a valuation component that can appraise the first quantum circuit based on one or more factors (e.g., frequency factor, complexity factor, resource factor, similarity factor), thereby yielding a value score that characterizes the first quantum circuit. In various instances, the system can further comprise an execution component that can recommend deployment of the first quantum circuit based on determining that the value score exceeds a threshold.

Abstract: Described is a camera device (3) for a motor vehicle (1), having: a camera (4) for recording an image, a computing unit (8) for executing a program sequence (12) for providing at least part of a driver assistance function (13, 14, 15) depending on the recorded image, a provisioning unit (11) for providing a temperature of the computing unit (8), and a control unit (10), which is configured to modify the program sequence (12) depending on the provided temperature, the computing unit (8) being configured to execute the modified program sequence (12?).

Abstract: Methods, systems, and apparatus for parallel decoding for quantum error correction codes. In one aspect, a classical computer system is configured to implement a decoding process on measurement data received from a quantum computing system to determine errors in a quantum computation. The classical computing system implements a main thread, multiple worker threads, and a data structure common to each worker thread. The data structure stores data of a dynamic system of disjoint clusters of nodes of a detector graph for the decoding process, where the data includes compressed logical flip information of child nodes in each cluster of nodes. During execution of the decoding process, the multiple worker threads are configured to, in parallel: obtain clusters of nodes and modify the clusters of nodes, where, for each modification, the worker thread updates data in the data structure that corresponds to the cluster under an atomicity primitive.

Abstract: A method is disclosed for requesting data in a cloud gaming system that includes a cloud storage system and a cloud compute system, each of which has a respective peripheral component interconnect express (PCIe) interface and a respective computer memory. The cloud gaming system includes a PCIe switch connected to both the PCIe interface of the cloud storage system and the PCIe interface of the cloud compute system. The PCIe switch exposes a doorbell register that is monitored by the cloud storage system. The cloud compute system writes to the doorbell register, which causes an interrupt to fire on the cloud storage system. The cloud storage system handles the interrupt, which directs the cloud storage system to read a message from a specified computer memory location. The message directs the cloud storage system to read requested data from a storage device accessible by the cloud storage system.

Abstract: Techniques for providing a fencing scheme for cluster systems without inherent hardware fencing. Storage nodes in an HA cluster communicate with one another over communication paths implemented through a variety of mechanisms, including drives and network connections. Each storage node in the HA cluster executes a fencing enforcer component operable to enforce actions or processes for initiating fencing of itself and/or initiating self-fencing of another storage node in the HA cluster determined to be malfunctioning. By providing for richer communications between storage nodes in an HA cluster and a richer set of actions or processes for fencing a malfunctioning storage node including self-fencing, the malfunctioning storage node can be made to exit the HA cluster in a more controlled fashion. In addition, a remaining storage node in the HA cluster can more safely take on the role of primary storage node with reduced risk of data corruption on shared resources.

Abstract: A semiconductor chip with functions implemented thereon in circuitry has a first region, in which a first group of safety-relevant base functions are implemented in circuitry, and a second region, which is separated from the first region using technological safety measures and in which a first group of monitoring functions that monitor the base functions are implemented in circuitry. It also contains a third region, which is formed on the semiconductor chip and is separated from the other regions using technological safety measures and in which a second group of monitoring functions that monitor the base functions are implemented in circuitry.

Abstract: A stand-alone embedded internet of things edge artificial intelligence device (“EIEAC”) may be provided. The EIEAC may be configured to operate independent of the computing device and may be configured to monitor and repair failures occurring at the computing device. The EIEAC may receive computer health data from a client agent application running on the computing device. The EIEAC may include a memory configured to store the computer health data and a battery configured to charge the EIEAC. The EIEAC may include a processor configured to process the computer health data to identify one or more failures using tiny machine learning (“tinyML”). When one or more failures are identified by the processor, the tinyML may be configured to execute instructions on the computer health data for repairing the one or more failures. When unsuccessful, the EIEAC may establish an electronic connection with a remote cloud lookup tower for repairing.

Abstract: A fault recovery system includes various fault management circuits that form a hierarchical structure. One fault management circuit detects a fault in a functional circuit and executes a recovery operation to recover the functional circuit from the fault. When the fault management circuit fails to recover the functional circuit from the fault within a predetermined time duration, a fault management circuit that is in a higher hierarchical level executes another recovery operation to recover the functional circuit from the fault. Such a fault management circuit is required to execute the corresponding recovery operation within another predetermined time duration to successfully recover the functional circuit from the fault. The fault recovery system thus implements the hierarchical structure of fault management circuits to recover the functional circuit from the fault.

Abstract: A method of memory deallocation across a trust boundary between a first software component and a second software component is described. Some memory is shared between the first and second software components. An in-memory message passing facility is implemented using the shared memory. The first software component is used to deallocate memory from the shared memory which has been allocated by the second software component. The deallocation is done by: taking at least one allocation to be freed from the message passing facility; and freeing the at least one allocation using a local deallocation mechanism while validating that memory access to memory owned by data structures related to memory allocation within the shared memory are within the shared memory.

Abstract: An apparatus and method are provided for storing and processing quantum information. More particularly, a physical layout is provided to perform Floquet codes. The physical layout includes a quantum processor having an array of qubits (e.g., columns of tetrons or hexons in which Majorana zero modes are located on topological superconductor segments) with a gateable semiconductor devices forming interference loops to perform two-qubit Pauli measurements. Coherent links between qubits in a column enable certain two-qubit Pauli measurements, especially those additional two-qubit Pauli measurements used at a boundary surrounding a region of the bulk code. The two-qubit Pauli measurements are selected to minimize a size of the interference loops. Certain embodiments perform Floquet codes in six time steps. Hexagon embodiments tile the array of qubits with unit cells of 6-gon vertical (or horizontal) bricks. Square-octagon embodiments tile the array of qubits with unit cells of two 4-gon and two 8-gon bricks.

Abstract: The present disclosure is directed to methods and systems for monitoring nodes on a distributed computing network. A distributed computing system can monitor each node within a wireless network to identify when a node is disconnected from the network. The distributed computing system can dynamically perform tasks on behalf of the node until the node is reconnected to the wireless network. In some implementations, the distributed computing system monitors the utilization of the wireless network to identify when the wireless network has the capacity to perform a task.

Abstract: The present disclosure relates to systems and methods for backing up a distributed database provided as a database instance across servers within a first geographic region. In one example, such a system may include at least one processor configured to: generate and transmit a command to duplicate the distributed database in object databases on first region servers; generate and transmit a command to duplicate the object databases on servers in at least a second geographic region independent from servers in the first region; and, when an error is detected with at least one server within the first region: generate and transmit a command to initiate a new distributed database on second region servers, generate and transmit a command to populate the new distributed database using the object databases on second region servers, and generate and transmit a command to re-route traffic from the distributed database to the new distributed database.

Abstract: A universal vehicle control router for small fly-by-wire aircraft may include multiple vehicle control computers, such as flight control computers. Each flight control computer may be part of an independent channel that provides instructions to multiple actuators to control multiple vehicle components. Each channel is a distinct pathway capable of delivering a system function, such as moving an actuator. Each flight control computer may include a fully analyzable and testable voter (FAT voter). In the event of a failure to one of the flight control computers, the FAT voters may cause the failing flight control computer to be ignored or shut off power. Each flight control computer may comprise a backup battery. In the event of a power disruption from the primary power source, such as a generator and primary battery, the backup battery may power the flight control computer and all actuators.

Abstract: In a network Fault Management (FM) model, network equipment (160) maintains a ManagedElement object (12). The ManagedElement object contains one or more ManagedFunction objects (14, 22, 24, 26) with each ManagedFunction object (16) comprising an FMControl object specifying the capabilities of the ManagedFunction objects to produce, report, and log fault reports, a Fault Type List object (18) listing the various types of faults the ManagedFunction object can detect, report, and log, and a currentFaultList object (20) listing the current faults and associated fault information. The FMControl object further includes several attributes that are set by a Management System (30) to control the reading of fault reports as well as the sending of the fault reports to other interested network nodes (190).

Abstract: In accordance with an embodiment of the invention, a cloud computing system is disclosed. The system includes a software-defined data center (SDDC), the SDDC including at least one cluster supported within the SDDC and at least one host computer running within the cluster, wherein the at least one host computer is configured to support at least one workload comprising an operating system and an application, and a cloud infrastructure, the cloud infrastructure including at least one child VM, the at least one child VM configured to virtualize the at least one host computer running within the cluster, and at least one parent virtual machine, wherein additional child VMs are deployed by forking the at least one parent VM.

Abstract: Disclosed herein is a data processing system comprising a processing unit operable to process data to generate a sequence of outputs, wherein the processing unit is configurable, when generating a sequence of outputs, such that the data processing for generating an output in the sequence of outputs will be performed within a respective processing period for the output. A controller for the processing unit is configured to cause the processing unit, when generating a sequence of outputs, during a respective processing period for at least one output in the sequence of outputs, to also undergo one or more fault detection test(s) such that both processing of data for the output and fault detection testing is performed during the respective processing period for the output.

Abstract: The examples disclosed herein provide classifying quantum errors. In particular, a classical computing system receives quantum error data from a first quantum computing device of a quantum computing system. The quantum error data includes error identification data and error correction data. The error identification data is associated with occurrence of a quantum error. The error correction data is associated with a corrective action taken by the first quantum computing device to correct the quantum error. The classical computing system determines an error type of the quantum error of the error identification data. The classical computing system associates an error classification tag with the quantum error data. The error classification tag identifies a quantum error type. The classical computing system sends the error classification tag to the first quantum computing device. The classical computing system processes a quantum computing request based on the error classification tag.

Abstract: In various examples there is a computing device comprising: a first microcontroller comprising a first immutable bootloader and first mutable firmware. The first immutable bootloader uses a unique device secret burnt into hardware of the computing device in order to generate an attestation of the first mutable firmware. The computing device has a second microcontroller. There is second mutable firmware at the second microcontroller. There is a second immutable bootloader at the second microcontroller which sends a measurement of the second mutable firmware to the first immutable bootloader whenever the second microcontroller restarts, such that the first microcontroller is able to include the measurement in the attestation.

Abstract: In described examples, an integrated circuit (IC) includes a first temperature sensor, a processor, a second temperature sensor, and a reset module. The first sensor senses a first body temperature of the IC. The processor asserts a thermal shutdown signal if the first body temperature exceeds a first threshold. In response to the thermal shutdown signal, the second sensor asserts a reset request signal and senses a second body temperature of the IC. If the second body temperature is less than a second threshold, the second sensor asserts a reset end signal. The reset module outputs a system reset signal to the first sensor and the processor if the reset request signal is asserted, and outputs a system recovery signal if the reset end signal is asserted. The first sensor and the processor deactivate if the system reset signal is asserted, and activate if the system recovery signal is asserted.

Abstract: Multi-chip systems and structures for modular scaling are described. In some embodiments an interfacing bar is utilized to couple adjacent chips. For example, a communication bar may utilized to coupled logic chips, and memory bar may be utilized to couple multiple memory chips to a logic chip.

Abstract: A voter-based method of controlling a redundancy is provided, including acquiring a processing element array in a target hardware, wherein the processing element array includes a plurality of processing elements, selecting a plurality of groups of processing elements from the processing element array so as to generate a voter set, wherein a corresponding voter is generated for each group of the plurality of groups of processing elements, and the corresponding voter configured to perform a voting operation in a redundancy control, acquiring, in response to a message indicating a fault state of a detected voter, a target voter from the voter set so as to replace the detected voter, and re-performing the voting operation in the redundancy control by using the target voter. An electronic device and a storage medium are further provided, which are implemented based on the processing element array of the target hardware.

Abstract: Methods, systems, and computer-readable media for execution of replicated tasks using redundant resources are disclosed. Replicas of a task are generated. Computing resources are selected from at least one pool of computing resources of a provider network. The provider network includes a plurality of pools of computing resources that vary in a characteristic, and the computing resources are selected based (at least in part) on the characteristic. Concurrent execution of the replicas of the task is initiated using the selected computing resources. Input data for the concurrent execution does not vary from one of the replicas to another of the replicas, and at least a portion of the replicas produce individual results for the input data. Based (at least in part) on a policy, an individual result of one or more of the replicas is selected as a final result of the task.

Abstract: Systems and methods for reporting API capability change according to an API filter are provided. According to one aspect, a method for reporting API capability change according to an API filter comprises receiving a request to be notified of an API capability change related to an identified wireless device, the request identifying a set of one or more APIs to be monitored; receiving a notification that the identified wireless device has changed from a first type of core network to a second type of core network; determining an API capability change from the first type of core network to the second type of core network for the identified set of one or more APIs to be monitored; and reporting the API capability change for the identified set of one or more APIs to be monitored and not reporting the API capability change for APIs not in the identified set.

Abstract: Methods and systems are disclosed herein for managing software operations in a computer system. A software operation may include many tasks. The tasks may be grouped together based on the tasks' dependencies on output generated from other tasks. Each group of tasks may be placed in a block of a blockchain based on the dependencies. If the output of a block fails to pass a validation test, the tasks in each block may be undone in an organized order (e.g., starting with the most recently performed task and using the one or more rollback functions associated with each task), which may prevent problems that could occur when some asynchronous tasks complete and others fail. Use of the blockchain may allow the computer system to determine more precisely where an operation failed and may allow the computer system to determine more information about the failure.

Abstract: A method includes receiving signaling indicative of performance of a reset operation involving a first physical function associated with a controller of a memory device and initiating a first timer that corresponds to an amount of time available for the first physical function associated with the controller of the memory device to complete execution of pending commands. The method further includes initiating a second timer that corresponds to an amount of time available for a second physical function associated with the controller of the memory device to complete execution of pending commands and initiating a third timer that corresponds to an amount of time available for the second physical function associated with the controller of the memory device to join a recovery operation that is instigated as a result of performance of the reset operation.

Abstract: A method for protecting a reconfigurable digital integrated circuit includes multiple parallel processing channels each comprising an instance of a functional logic block and an error detection unit, the method comprising the successive steps of: activating the error detection unit in order to detect an error in at least one processing channel, executing the data replay mechanism, and then activating the error detection unit in order to detect an error in at least one processing channel, if an error is detected again, executing a self-test on each processing channel, for each processing channel, if the self-test does not detect any error, executing the data replay mechanism for this processing channel, if the self-test detects an error, reconfiguring that part of the configuration memory associated with this processing channel.

Abstract: A method is disclosed for requesting data in a cloud gaming system that includes a cloud storage system and a cloud compute system, each of which has a respective peripheral component interconnect express (PCIe) interface and a respective computer memory. The cloud gaming system includes a PCIe switch connected to both the PCIe interface of the cloud storage system and the PCIe interface of the cloud compute system. The PCIe switch exposes a doorbell register that is monitored by the cloud storage system. The cloud compute system writes to the doorbell register, which causes an interrupt to fire on the cloud storage system. The cloud storage system handles the interrupt, which directs the cloud storage system to read a message from a specified computer memory location. The message directs the cloud storage system to read requested data from a storage device accessible by the cloud storage system.

Abstract: A system, method and apparatus to record data relevant to hardware errors identified by microprocessors. For example, in response to a hardware error, a microprocessor can store first data about the error in registers in the microprocessor and start to execute instructions configured in firmware and/or in an operating system. Execution of the instructions in response to the hardware error causes the microprocessor to: generating second data about the error based at least in part on the first data in the registers; and store the second data at a location not affected by restarting execution of an operating system in the processor. For example, the execution of the instructions can cause the microprocessor to decode the first data to obtain a temperature of the computing device as part of the second data.

Abstract: A method and digital signage player for managing display of a distributed digital signage content. The digital signage player stores the distributed digital signage content, and a local placement target for the distributed digital signage content. The digital signage player displays the distributed digital signage content in accordance with the local placement target. The digital signage player exchanges messages with a neighbor digital signage player, for increasing the local placement target of the distributed digital signage content at the request of the neighbor digital signage player. The neighbor digital signage player also displays the distributed digital signage content in accordance with its own placement target, which needs to be decreased. The digital signage player ultimately increases the local placement target of the distributed digital signage content based on the messages exchanged with the neighbor digital signage player.

Abstract: The present disclosure includes apparatuses, methods, and systems for increase of a sense current in memory. An embodiment includes a memory having a plurality of memory cells, and circuitry configured to count a number of program operations performed on the memory cells of the memory during operation of the memory, and increase a magnitude of a current used to sense a data state of the memory cells of the memory upon the count of the number of program operations reaching a threshold count.

Abstract: A system for monitoring job execution includes an interface and a processor. The interface is configured to receive an indication to start a cluster processing job. The processor is configured to determine whether processing a data instance associated with the cluster processing job satisfies a watchdog criterion; and in the event that processing the data instance satisfies the watchdog criterion, cause the processing of the data instance to be killed.

Abstract: Embodiments of the present systems and methods may provide the capability ensure that data is persisted and accessed correctly without depending on eventually consistent list operations on the object store. For example, in an embodiment, a computer-implemented method for data distribution may comprise attempting to persist a plurality of data parts from a plurality of processing tasks, generating a manifest including information indicating those attempts to persist data parts that have succeeded, and persisting the manifest with the data parts that have been successfully persisted.

Abstract: The machine learning device comprises a training part configured to train a machine learning model used in a vehicle; and a detecting part configured to detect replacement of a vehicle part mounted in the vehicle. The training part is configured to retrain the machine learning model using training data sets corresponding to a vehicle part after replacement when a vehicle part relating to input data of the machine learning model is replaced.

Abstract: A computer-implemented method for bytecode class verification includes: encountering a class requiring verification of its bytecode during a run of an application; determining whether class relationship data for the class exists in a shared classes cache; in response to a determination that the class relationship data for the class does not exist in the shared classes cache: performing a linear bytecode walk of the bytecode to identify relationship data for the class and verify that the bytecode is well-formed; and storing the identified relationship data as the class relationship data for the class in the shared classes cache; in response to a determination that the class relationship data for the class does exist in the shared classes cache: retrieving the class relationship data for the class from the shared classes cache; and processing the class relationship data.

Abstract: An apparatus includes a selection data generation circuit configured to generate selection data from fuse data or generate the selection data having a preset test input pattern, depending on whether a failure test is entered; and a failure flag generation circuit configured to generate latch data by latching the selection data, and generate a failure flag by detecting whether the latch data has a preset test pattern.

Abstract: A method of memory deallocation across a trust boundary between a first software component and a second software component is described. Some memory is shared between the first and second software components. An in-memory message passing facility is implemented using the shared memory. The first software component is used to deallocate memory from the shared memory which has been allocated by the second software component. The deallocation is done by: taking at least one allocation to be freed from the message passing facility; and freeing the at least one allocation using a local deallocation mechanism while validating that memory access to memory owned by data structures related to memory allocation within the shared memory are within the shared memory.

Abstract: An information handling system may include at least one processor, and a non-transitory memory coupled to the at least one processor. The information handling system may be configured to execute a configuration procedure to set up a plurality of information handling resources of the information handling system, and wherein the configuration procedure includes a plurality of logical groups related to different types of configuration. Each logical group may include one or more atomic groups, each atomic group including a plurality of logically related atomic operations. In response to a failure of a particular atomic operation of a particular atomic group, the information handling system may be configured to roll back the particular atomic operation and allow the configuration procedure to be restarted at a beginning of the particular atomic group.

Abstract: Systems, methods, and apparatuses relating to operations in a configurable spatial accelerator are described. In one embodiment, a configurable spatial accelerator includes a first processing element that includes a configuration register within the first processing element to store a configuration value that causes the first processing element to perform an operation according to the configuration value, a plurality of input queues, an input controller to control enqueue and dequeue of values into the plurality of input queues according to the configuration value, a plurality of output queues, and an output controller to control enqueue and dequeue of values into the plurality of output queues according to the configuration value.