Of Processor Patents (Class 714/10)
  • Patent number: 11144374
    Abstract: Example implementations relate to preserving data availability in a constrained deployment of an HA system (e.g., an HA storage system) in the presence of pending faults. According to an example, a first arbiter, acting as a witness to facilitate maintaining quorum for the HA system, and a first node are provided within a first failure domain; and a second arbiter, serving as a backup arbiter, and a second node are provided within a second failure domain. Responsive to receipt of an indication of a pending fault impacting the first failure domain by a member of the current configuration of the HA system, establishment of a new configuration, excluding the first arbiter and including the second arbiter, is initiated. Responsive to a majority of the current configuration installing the new configuration, the second arbiter is enabled to serve as the active arbiter by transferring state information to the second arbiter.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: October 12, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Bradford Glade, Peter Corbett
  • Patent number: 11126573
    Abstract: Systems and methods of managing variable size load units of application codes in a processing system include identifying pages of a random access memory (RAM) device to store copies of load units from an external memory device upon request by a bus master in the processing system. The RAM device is internal to an integrated circuit device that includes the bus masters, and the external memory device is external to the integrated circuit device. The bus masters execute the application codes, and each of the application codes comprise one or more load units that include executable program instructions. At least some of the load units have different sizes from one another. A page type indicator is determined for an identified page. A first page type indicates whether the identified page is a split page to store a segment of each of two different load units.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: September 21, 2021
    Assignee: NXP USA, Inc.
    Inventors: Michael Rohleder, Cristian Macario, Dirk Moeller
  • Patent number: 11108883
    Abstract: Systems and methods are disclosed herein for obtaining data about a network having at least a first node and a second node. A server transmits to the first node a first request for the first node to send a communication to the second node. The server is outside of the network, and the first request includes a first address of the first node and a second address of the second node. The server receives, from the first node, an indication of whether the communication to the second node is successful. The server receives, from the first node, a second request for access to a file stored on the server, determines that the file is stored locally at the second node, and transmits, to the first node, an instruction to retrieve the file from the second node, when the communication to the second node is successful.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: August 31, 2021
    Assignee: Google LLC
    Inventors: Nicholas Mark Vasic Cooper, Max Ward-Graham
  • Patent number: 11086746
    Abstract: A node in network is configured to buffer data received from other nodes across multiple channels. The node process a portion of the buffered data associated with a subset of those channels. When the node receives data on that subset of channels that includes a notification, the node then processes a larger portion of the buffered data associated with a larger number of channels. In doing so, the node may identify additional notifications include within data that was buffered but not previously processed. The node may also coordinate with other nodes in order to process buffered data upon identification of a notification.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: August 10, 2021
    Assignee: ITRON NETWORKED SOLUTIONS, INC.
    Inventor: Elad Gottlib
  • Patent number: 11068348
    Abstract: This application discloses a method and an enable apparatus for starting a physical device, where the physical device includes N central processing units (CPUs) and at least one platform controller hub (PCH), N is greater than one. Each of the N CPUs is electrically coupled to a PCH in the at least one PCH. The method includes determining a second CPU in the N CPUs as the primary CPU when a fault occurs in a first CPU, where the first CPU is the primary CPU configured to start the physical device before the fault occurs in the first CPU, and triggering the second CPU as the primary CPU and in cooperation with a first PCH to start the physical device, where the first PCH is one PCH in the at least one PCH.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: July 20, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Ben Chen
  • Patent number: 11061674
    Abstract: Apparatuses and methods are disclosed for an FPGA architecture that may improve processing speed and efficiency in processing less complex operands. Some applications may utilize operands that are less complex, such as operands that are 1, 2, or 4 bits, for example. In some examples, the DSP architecture may skip or avoid processing all received operands or may process a common operand more frequently than other operands. An example apparatus may include configurable logic blocks including DSP slices and an interconnected coupling the configurable logic blocks. An operand register of a DSP slice may include an operand input that is coupled to an output of that DSP slice.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: July 13, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Gregory Edvenson, David Hulton, Jeremy Chritz
  • Patent number: 11055363
    Abstract: A method for distributed multi-choice voting/ranking in a network with a plurality of nodes associated to a set of choices is disclosed. The method includes setting a plurality of value sets for a plurality of nodes, setting a plurality of collections of memory sets for the plurality of nodes, and updating the plurality of value sets. In addition, the method includes updating the plurality of collections of memory sets, calculating a majority vote for the set of choices, and calculating a rank set for the set of choices.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: July 6, 2021
    Inventors: Saber Salehkaleybar, Arsalan Sharifnassab, S. Jamaloddin Golestani
  • Patent number: 11048570
    Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and a computer system are provided. The computer system includes an initialization component of a host. The initialization component obtains health data indicating that at least one hardware component of the host is in one of one or more predetermined health conditions when executed in a system management mode of the host. The initialization component then sends, to a service processor of the host, a message in accordance with a management protocol. The message includes the health data.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: June 29, 2021
    Assignee: AMERICAN MEGATRENDS INTERNATINOAL, LLC
    Inventors: Manickavasakam Karpagavinayagam, Manish Jha, Harikrishna Doppalapudi, Purandhar Nallagatla, Chandrasekar Rathineswaran
  • Patent number: 11023290
    Abstract: A processing system comprising an arrangement of tiles and an interconnect between the tiles. The interconnect comprises synchronization logic for coordinating a barrier synchronization to be performed between a group of the tiles. The instruction set comprises a synchronization instruction taking an operand which selects one of a plurality of available modes each specifying a different membership of the group. Execution of the synchronization instruction cause a synchronization request to be transmitted from the respective tile to the synchronization logic, and instruction issue to be suspended on the respective tile pending a synchronization acknowledgement being received back from the synchronization logic. In response to receiving the synchronization request from all the tiles in the group as specified by the operand of the synchronization instruction, the synchronization logic returns the synchronization acknowledgment to the tiles in the specified group.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: June 1, 2021
    Assignee: Graphcore Limited
    Inventors: Daniel John Pelham Wilkinson, Simon Christian Knowles, Matthew David Fyles, Alan Graham Alexander, Stephen Felix
  • Patent number: 11017032
    Abstract: Systems and methods for the presentation content on client computing devices. A processing component serializes browser data as a set of serialized data portions that can be incorporated into a serialization file. The serialized data portions can be prioritized to determine an order of priority and the serialized data portions can further be processed in parallel. As the serialized data portions are processed, they can be added to the serialized data file with a completion marker. If the serialization process is interrupted before all the browser information is serialization, the browser is still able to utilize any portions in the serialized data file that are accompanied by a completion marker.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: May 25, 2021
    Assignee: Amazon Technologies, Inc.
    Inventor: Jari Juhani Karppanen
  • Patent number: 10990462
    Abstract: Disclosed herein are various embodiments that perform application-aware input/output (I/O) fencing operations, certain of which embodiments include, in response to detection of a network partition event in a cluster, determining a first application weight, determining whether the first one or more application instances should be delayed in a cumulative fencing race, performing the cumulative fencing race (in response to a determination that the first one or more application instances should be delayed in the cumulative fencing race), and performing the cumulative fencing race without introducing the delay with regard to the first one or more application instances (in response to a determination that the first one or more application instances should not be delayed in the cumulative fencing race).
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: April 27, 2021
    Assignee: Veritas Technologies LLC
    Inventors: Jai Gahlot, Abhijit Toley
  • Patent number: 10976793
    Abstract: A rack computer system can provide data indicating electrical power consumption by separate sets of the mass storage devices, including separate individual mass storage devices, of the rack computer system. A power sensor can be electrically coupled to a power transmission line for each mass storage device. The power sensor can be coupled to the power transmission line externally to the mass storage device. The power sensor can be an internal power sensor of the mass storage device, where a mass storage device microcontroller transmits internally-generated data to an external power monitoring system. A microcontroller can transmit the data to a baseboard management controller via a side-band connection between the mass storage device and the controller. The data can be transmitted via an in-band connection between a baseboard management controller and an instance of firmware which accesses internally-generated data from mass storage device microcontrollers.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: April 13, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Felipe Enrique Ortega Gutierrez, Jason Alexander Harland, Roey Rivnay, David Edward Bryan, Christopher Strickland Beall
  • Patent number: 10956288
    Abstract: A device may provision two or more servers, each of the servers including a network interface. In addition, the device may enable the network interface in each of the provisioned servers, create a shared volume, assign the shared volume to each of the provisioned servers, and enable a clustering application on each of the provisioned servers to form a cluster comprising the provisioned servers, the cluster having a heartbeat via the network interfaces.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: March 23, 2021
    Assignee: salesforce.com, inc.
    Inventors: Emily Katherine Witt, Richard Cooke, William Thomas Everhart, Jr., Jinendrakumar J. Patel, Vijay Kumar
  • Patent number: 10949213
    Abstract: A computer system, processor, and method for processing information is disclosed that includes partitioning a logical register in the processor into a plurality of ranges of logical register entries based upon the logical register entry, assigning at least one recovery port of a history buffer to each range of logical register entries, initiating a flush recovery process for the processor, and directing history buffer entries to the assigned recovery port based upon the logical register entry associated with the history buffer entry.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: March 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: Steven J. Battle, Salma Ayub, Brian D. Barrick, Joshua W. Bowman, Susan E. Eisen, Brandon Goddard, Christopher M. Mueller, Dung Q. Nguyen
  • Patent number: 10904339
    Abstract: Various embodiments are generally directed to techniques for reducing the time required for a node to take over for a failed node or to boot. An apparatus includes an access component to retrieve a metadata from a storage device coupled to a first D-module of a first node during boot, the metadata generated from a first mutable metadata portion and an immutable metadata portion, and the first metadata specifying a first address of a second D-module of a second node; a replication component to contact the second data storage module at the first address; and a generation component to, in response to failure of the contact, request a second mutable metadata portion from a N-module of the first node and generate a second metadata from the second mutable metadata portion and the immutable metadata portion, the second mutable metadata portion specifying a second address of the second D-module.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: January 26, 2021
    Assignee: NetApp Inc.
    Inventors: Paul Yuedong Mu, Manoj Sundararajan, Paul Ngan
  • Patent number: 10896146
    Abstract: A system and method for determining reliability-aware runtime optimal processor configuration can integrate soft and hard error data into a single metric, referred to as the balanced reliability metric (BRM), by using statistical dimensionality reduction techniques. The BRM can be used to not only adjust processor voltage to optimize overall reliability but also to adjust the number of on-cores to further optimize overall processor reliability. In some implementations, both coarse-grained actuations, based on optimal core count, and fine-grained actuations, based on optimal processor voltage (Vdd), may be used, where feedback control can recursively re-compute soft and hard error data based on a new configuration, until convergence at an optimal configuration.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: January 19, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik V. Swaminathan, Ramon Bertran Monfort, Alper Buyuktosunoglu, Pradip Bose, Nandhini Chandramoorthy, Chen-Yong Cher
  • Patent number: 10887382
    Abstract: Methods, apparatuses, and systems for cloud-based disaster recovery are provided. The method, for example, includes receiving, at a cloud-based computing platform, backup information associated with a backup vendor used by a client machine, storing, at the cloud-based computing platform, the backup information associated with the backup vendor, receiving, at the cloud-based computing platform from the client machine, a failure indication for a server associated with the backup vendor, and creating a virtual server corresponding to the server using the stored backup information at the cloud-based computing platform.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: January 5, 2021
    Assignee: Storage Engine, Inc.
    Inventors: Trevor Savino, James Patrick Hart, Justin Furniss, Charles Wooley
  • Patent number: 10884796
    Abstract: Systems and methods are described herein for job execution using system critical threads. An in-memory database system having pages loaded into a memory and having associated physical disk storage generates a safety critical thread pool. The safety critical thread pool has one or more safety critical threads associated with flushing the pages to the physical disk storage. Execution of the one or more safety critical threads is initiated within the safety critical thread pool. A job request to access data stored within the physical disk storage is received. Utilization levels of the one or more safety critical threads are monitored. Execution of the job request is permitted based on the utilization levels associated with the one or more safety critical threads.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: January 5, 2021
    Assignee: SAP SE
    Inventors: Tobias Scheuer, Dirk Thomsen
  • Patent number: 10877859
    Abstract: A system for monitoring a virtual machine executed on a host. The system includes a processor that receives an indication that a failure caused a storage device to be inaccessible to the virtual machine, the inaccessible storage device impacting an ability of the virtual machine to provide service, and applies a remedy to restore access to the storage device based on a type of the failure.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: December 29, 2020
    Assignee: VMware, Inc.
    Inventors: Joanne Ren, Igor Tarashansky, Keith Farkas, Elisha Ziskind, Manoj Krishnan
  • Patent number: 10877858
    Abstract: Described is a system, method, and computer program product for identifying communication failures between nodes of database cluster system where each member node within the cluster constantly monitors itself. Upon detection of a node communication failure by a particular node, the particular node notifies other member nodes of the cluster that the particular node is having communication problems with other nodes of the database cluster by communicating through a different communication channel with the other nodes so that the particular node may be evicted from the cluster efficiently.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: December 29, 2020
    Assignee: Oracle International Corporation
    Inventors: Ming Zhu, Andrey Gusev
  • Patent number: 10812622
    Abstract: A system includes a management data store configured to store configuration information for a service and reboot information for a server that hosts the service. The system also includes an execution module configured to: generate (i) a configuration file and (ii) a reboot script and push (i) the configuration file and (ii) the reboot script out to the server. The configuration file includes a location of at least one management script (i) associated with the service and (ii) stored on the server. The execution module is configured to obtain a status of the service on the server by executing the at least one management script on the server. The system also includes an operator portal configured to create a first user interface for display to a user. The first user interface includes a name of the service, a name of the server, and the status of the service.
    Type: Grant
    Filed: March 31, 2019
    Date of Patent: October 20, 2020
    Assignee: TD Ameritrade IP Company, Inc.
    Inventors: Glenn Jared Komsky, Chibo Qian
  • Patent number: 10782767
    Abstract: The present disclosure relates to a method for reducing power consumption. Embodiments include providing an electronic design of a device under test having a plurality of flip-flops associated therewith. Embodiments also include selecting a first set of flip-flops from the plurality of flip-flops and disabling a first clock associated with the first set of flip-flops without changing a value of the first set of flip-flops. Embodiments may further include selecting a second set of flip-flops from the plurality of flip-flops and disabling a second clock associated with the second set of flip-flops without changing a value of the second set of flip-flops. Embodiments may further include determining whether a first output from the first set of flip-flops and a second output from the second set of flip-flops have converged.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: September 22, 2020
    Assignee: Cadence Design Systems, Inc.
    Inventors: Karam Abd Elkader, Doron Bustan, Habeeb Farah, Yaron Schiller
  • Patent number: 10778326
    Abstract: A disaggregated network element of an optical transport network, addressable at a single IP address, includes an active management and control unit (MCU) communicatively coupled to a standby MCU by physical cables and multiple tributary units, each of which performs a function in a data plane that carries user traffic and is communicatively coupled to both MCUs by respective physical cables. The MCUs host respective copies of configuration information for the network element and synchronize the information between them. In response to a loss of communication between the MCUs, a tributary unit designated as a witness tributary unit is consulted to determine the status of the MCUs, after which actions are taken to provide control plane redundancy. In response to a failure of an MCU, a backup copy of the configuration information is stored on the witness tributary unit and subsequently synchronized with a copy stored on the remaining MCU.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: September 15, 2020
    Assignee: Fujitsu Limited
    Inventors: Maitreya Mukhopadhyay, David W. Terwilliger, Edwin Jay Burger, Sridevi Palacharla, Qiang Li
  • Patent number: 10771318
    Abstract: Providing high availability in a distributed networking platform includes detecting that an original primary service engine is unavailable, wherein: the original primary service engine and a plurality of secondary service engines are configured to provide one or more network applications associated with a virtual Internet Protocol (VIP) address; the original primary service engine and the plurality of secondary service engines are in active-active configuration mode; and the original primary service engine is configured to respond to Address Resolution Protocol (ARP) requests designating the VIP address. Additionally, providing high availability in a distributed networking platform further includes determining that a controller is unavailable; and configuring a selected secondary service engine as the next primary service engine.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: September 8, 2020
    Assignee: VMWARE, INC
    Inventors: Kiron Haltore, Srinivas Srikanth Podilla, Vivek Kalyanaraman
  • Patent number: 10761926
    Abstract: A method and system for automatically managing a fault event occurring in a datacenter system provided. The method includes collecting hardware fault event analysis corresponding with the hardware fault event. The hardware fault event analysis is organized into a report for a server device suffering from the hardware fault event. The method also includes processing statistical data received from the report for the server device. The method also includes performing hardware recovery based on the evaluated statistical data.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: September 1, 2020
    Assignee: QUANTA COMPUTER INC.
    Inventor: Wei-Yu Chien
  • Patent number: 10761916
    Abstract: A method for executing programs (P) in an electronic system for applications with functional safety that comprises a single-processor or multiprocessor processing system (10) and a further independent control module (15), including: carrying out a decomposition of a program (P) that includes a safety function (SF) to be executed via said system (10) into a plurality of parallel subprograms (P1, . . . , Pn); assigning execution of each parallel subprogram (P1, . . . , Pn) to a respective processing module (11) of the system, in particular a processor (C1, . . . , Cm) of said multiprocessor architecture (10) or a virtual machine (V1, . . . , Vn) associated to one of said processors (C1, . . . , Cm); carrying out in the system (10), periodically according to a cycle frequency (fcyc) of the program (P) during normal operation of said system (10), in the context of said safety function (SF), self-test operations (Astl, Asys, Achk) associated to each of said subprograms (P1, . . .
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: September 1, 2020
    Assignee: Intel Corporation
    Inventor: Riccardo Mariani
  • Patent number: 10754740
    Abstract: A processing system tags read and write transaction packets that are functionally safe and suppresses redundant processing and error checking for functionally safe tagged transaction packets. The processing system includes compute elements that are interconnected via an interconnect fabric that includes resources to route operations. The interconnect fabric includes redundant resources to execute the same routing operations and comparator elements to indicate an error in response to detecting a mismatch between the output of a resource and its corresponding duplicate resource. The interconnect fabric selectively activates the duplicate resources and comparator elements in response to a tag associated with a transaction packet indicating that the transaction packet is safety-critical.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: August 25, 2020
    Assignee: NXP USA, Inc.
    Inventors: Anis Mahmoud Jarrar, Nancy Hing-Che Amedeo, John F. West
  • Patent number: 10747656
    Abstract: A computerized method of testing a mobile application stored on a mobile test device includes executing, by a computing device, a test script stored in memory of the computing device; running, by the computing device, according to the test script, a human behavior simulation module; retrieving, by the computing device, an event list stored in a server, the event list including one or more electronic human behavior simulations; receiving, by the computing device an electronic human behavior simulation from the event list; providing, by the computing device, selected data of the electronic human behavior simulation to memory of the server for recordation; executing, by the computing device, the electronic human behavior simulation on a mobile test device in electronic communication with the computing device; and executing, by the computing device, according to the test script, a test case stored in memory of the computing device on the mobile test device.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: August 18, 2020
    Assignee: FMR LLC
    Inventors: Ke Yang, Hongbing Gu, Yanyu Xu, Pengrui Sun
  • Patent number: 10747744
    Abstract: A snapshot of a distributed ledger is generated, wherein the distributed ledger is stored by a plurality of node computing entities. A first node computing entity reads current states of one or more domain objects from a local cache stored by the node computing entity and corresponding to an application operating on the node computing entity. A snapshot record comprising the current states of the one or more domain objects is generated and written to a segment data file. The snapshot record is posted to the distributed ledger as part of a block.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: August 18, 2020
    Assignee: AlphaPoint
    Inventors: Giuseppe Ventura, Jeffrey Tangowski
  • Patent number: 10721335
    Abstract: A method, system, and non-transitory computer readable medium are disclosed to regarding remote procedure call (RPC) functionality from a requestor node to a processing node using a quorum state store communication protocol. Records from a quorum state store may be augmented to include an indication of both the processing node and the requestor node; remote procedure call (RPC) request information; and information including RPC coordination information. Heartbeat messages may propagate updated quorum state store records throughout the quorum. Requestor nodes and processing nodes may perform requested functions and supply status information via updates to their own quorum state store records. Quorum state store records may be propagated throughout the quorum even when direct communication between requestor nodes and processing nodes may not be available.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: July 21, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Manan Gupta, Tomasz Barszczak
  • Patent number: 10666565
    Abstract: The systems and methods discussed herein provide for relative QoS gain measurement, and reduction in variance of QoS during bandwidth contention. In some implementations, the system measures relative QoS gains of, or penalties to, similar connections or network flows due to different factors that affect the transmission throughput and QoS. The system provides scheduling of packets on different connections or flows according to ratios of QoS penalties or gains on the connections or flows, preventing a well-performing connection or flow from cannibalizing throughput from under-performing connections or flows.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: May 26, 2020
    Assignee: Citrix Systems, Inc.
    Inventors: Praveen Raja Dhanabalan, Deepti Kubair
  • Patent number: 10664351
    Abstract: Apparatus and methods related to recovering a computing device are provided. A computing device can determine that the computing device has entered into a corrupted state after being initialized at least a pre-determined number of times during a pre-determined interval of time. The computing device can store at least system data and information about a plurality of changes to the system data. After determining that the computing device has entered into the corrupted state, the computing device can identify untrusted changes to the system data from the plurality of changes, wherein the untrusted changes are made by untrusted entities. The computing device can reset the untrusted changes to the system data to default values. After resetting the untrusted changes to the system data to default values, the computing device can be initialized.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: May 26, 2020
    Assignee: Google LLC
    Inventors: Jeffrey Sharkey, Svetoslav Ganov
  • Patent number: 10657010
    Abstract: An apparatus 2 comprises at least three processing circuits 4 to perform redundant processing of a common thread of program instructions. Error detection circuitry 16 is provided comprising a number of comparators 22 for detecting a mismatch between signals on corresponding signal nodes 20 in the processing circuits 4. When a comparator 22 detects a mismatch, this triggers a recovery process. The error detection circuitry 16 generates an unresolvable error signal 36 indicating that a detected area is unresolvable by the recovery process when, during the recovery process, a mismatch is detected by one of the proper subset 34 of the comparators 22. By considering fewer comparators 22 during the recovery process than during normal operation, the chances of unrecoverable errors being detected can be reduced, increasing system availability.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: May 19, 2020
    Assignee: ARM Limited
    Inventors: Xabier Iturbe, Emre Ozer, Balaji Venu
  • Patent number: 10642702
    Abstract: A network device may detect an event associated with a first control plane component included in the network device. The network device may, based on detecting the event, deactivate a first master control plane address configuration stored in a first cache on the first control plane component, and activate a second master control plane address configuration that was stored, prior to the event being detected, in a second cache on a second control plane component included in the network device. The network device may establish, using the activated second master control plane address configuration stored in the second cache on the second control plane component, a connection between the second control plane component and a data plane component included in the network device.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: May 5, 2020
    Assignee: Juniper Networks, Inc.
    Inventors: Tabrez Ahmed Khan, Manoj Nayak
  • Patent number: 10635538
    Abstract: A semiconductor device and method includes a configuration information storage memory that stores a plurality of configuration information items, a state transition management unit that selects any one of the plurality of configuration information items, and a data path unit that dynamically reconfigures a circuit according to the configuration information item selected by the state transition management unit. When a detection of a failure or no failure is made in any one of a plurality of logic circuit groups provided in the data path unit, the state transition management unit selects the configuration information item depending on a result of the detection.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: April 28, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yoshitaka Izawa, Katsumi Togawa, Takao Toi, Taro Fujii
  • Patent number: 10628377
    Abstract: A processing system comprising an arrangement of tiles and synchronization logic in the form of hardware logic for coordinating between a group of some or all of said tiles. The instruction set comprises a synchronization instruction which causes an instance of a synchronization request to be transmitted from the respective tile to the synchronization logic, and suspends instruction issue on the respective tile pending a synchronization acknowledgement. In response to receiving an instance of the synchronization request from all of the tiles of the group, the synchronization logic returns the synchronization acknowledgment back to each of the tiles in the group to allow the instruction issue to resume. The instruction set further comprises an abstain instruction, which sends an instance of the synchronization request but does not suspend instruction issue on the respective tile pending the synchronization acknowledgement, instead allowing the instruction issue on the respective tile to continue.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: April 21, 2020
    Assignee: Graphcore Limited
    Inventors: Daniel John Pelham Wilkinson, Richard Luke Southwell Osborne, Matthew David Fyles, Alan Graham Alexander, Stephen Felix
  • Patent number: 10631214
    Abstract: A method for performing a switch from a first mobile network to a second mobile network by a mobile terminal comprising a secure element includes the following steps: attaching to the first mobile network using a first subscription profile; downloading a second subscription profile from a subscription management server including a command script defining a sequence of commands; attaching to the second mobile network; and executing the sequence of commands defined by the command script.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: April 21, 2020
    Assignee: GIESECKE+DEVRIENT MOBILE SECURITY GMBH
    Inventors: Ulrich Huber, Thomas Larsson
  • Patent number: 10615865
    Abstract: A satellite repeater system for a ship or barge includes a rack having dimensions that are substantially equal to a standard shipping container; and a satellite communication system located on the rack. The satellite communication system includes a first antenna located on the rack, the first antenna being configured to send and receive data from a communication satellite; and a second antenna located on the rack, the second antenna being configured to send and receive data from one or more electronic components located on the ship or barge remotely from the second antenna.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: April 7, 2020
    Assignee: Crowley Liner Services, Inc.
    Inventor: David H. Waldhauer, Jr.
  • Patent number: 10606704
    Abstract: A method, computer program product, computing system, and system for backing up a virtual machine by creating consistent copies of application data are described. The method may include creating a snapshot of a virtual machine running on a host system. The method may further include determining if the snapshot has a snapshot ID and creating the snapshot ID if the snapshot does not have the snapshot ID. The method may also include creating a virtual machine restoration script configured to roll back the virtual machine to a state corresponding to the snapshot based on the snapshot ID. The method may additionally include backing up the host system in a backup archive while the virtual machine continues operating.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: March 31, 2020
    Assignee: ACRONIS INTERNATIONAL GMBH
    Inventors: Dmitry Chepel, Stanislav Protasov, Serguei M. Beloussov
  • Patent number: 10592454
    Abstract: A system-on-chip (SoC) to perform a deadlock control on a processor of the SoC, the SoC including the processor including a plurality of central processing unit (CPU) cores, a first bus connected to the processor, a graphic processing unit (GPU) connected to the first bus, a memory controller connected to the first bus, a second bus connected to the processor, an isolation cell including a logic circuit configured to retain a signal value input to the processor according to an isolation signal, and a deadlock controller connected to the first bus and the second bus. The deadlock controller is configured to isolate the processor, which is in a deadlock state, from the first bus by applying the isolation signal on the isolation cell, and to extract, via the second bus, state information of the isolated processor in the deadlock state.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: March 17, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Youl Kim, Chih Jen Lin, Jinook Song, Sungjae Lee, Hyun-ki Koo, Donghyeon Ham
  • Patent number: 10574509
    Abstract: In one or more embodiments, one or more systems, method, and/or processes may receive an event from an operating system and provide the event to a management controller configured to perform out-of-band tasks. The management controller may provide information based on the event to at least one subscriber. In one example, the information may include a status of an information handling system (e.g., an impairment, a hardware failure, a progress of an update, etc.). In another example, the management controller may provide information utilizing a protocol that provides a measure of reliability. For instance, the protocol may include a transmission control protocol. In one or more embodiments, the protocol may include one or more of a hypertext transfer protocol (HTTP) and a HTTP secure (HTTPS).
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: February 25, 2020
    Assignee: Dell Products L.P.
    Inventors: Srikanth Kondapi, Nathan F. Martell, Joseph Kozlowski, Jr., Abeye Teshome
  • Patent number: 10565056
    Abstract: Techniques for parallel data collection and recovery for a failing virtual processing system are disclosed. According to aspects of the present disclosure, an example method includes: detecting that the virtual processing system experiences an irreparable error; saving, by each of a plurality of processors of the physical processing system, a corresponding context and data stored in an allocated portion of a memory of the physical processing system to a data store; selecting one of the plurality of processors as a recovery processor; initializing, by the recovery processor, a pre-determined reserved portion of the memory; initiating, by the recovery processor, a new instance of the virtual processing system on the reserved portion of the memory while each remaining processor of the plurality of processors continues the saving; and dynamically adding each remaining processor of the plurality of processors to the new instance of the virtual processing system.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: February 18, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bryan P. Davidson, Michael E. Gildein, Angelo M. Quadara
  • Patent number: 10552740
    Abstract: Embodiments of the present invention relate to providing fault-tolerant power minimization in a multi-core neurosynaptic network. In one embodiment of the present invention, a method of and computer program product for fault-tolerant power-driven synthesis is provided. Power consumption of a neurosynaptic network is modeled as wire length. The neurosynaptic network comprises a plurality of neurosynaptic cores connected by a plurality of routers. At least one faulty core of the plurality of neurosynaptic cores is located. A placement blockage is modeled at the location of the at least one faulty core. A placement of the neurosynaptic cores is determined by minimizing the wire length.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: February 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles J. Alpert, Pallab Datta, Myron D. Flickner, Zhuo Li, Dharmendra S. Modha, Gi-Joon Nam
  • Patent number: 10528110
    Abstract: A method in a wireless communication device for diagnosing power supply failure in the wireless communication device is provided. The wireless communication device detects (301) an indication of power supply failure in the wireless communication device. When the indication of the power supply failure further indicates a non-active state of the wireless communication device or when the wireless communication device enters an error handling mode, the wireless communication device collects (302) diagnostic data from the PMU by means of a diagnostic engine (215) in the PMU. The wireless communication device then stores (303) the collected diagnostic data to a memory in the PMU. The data is related to the event resulting in the non-active state and/or to the latest event in a system of the wireless communication device or when the wireless communication device enters an error handling mode.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: January 7, 2020
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Joni Jäntti, Joakim Andersson, Markus Littow, Tarmo Ruotsalainen, Saila Tammelin
  • Patent number: 10503405
    Abstract: A processing device receives a request to provide a hardware device with direct memory access to a contents of a virtual memory location in application memory of an application. Responsive to the request, the processing device locks the virtual memory location. The processing device makes a determination to reclaim a physical memory location mapped to the virtual memory location. The processing device then determines whether the hardware device has completed the access to a physical memory location mapped to the virtual memory location. Responsive to determining that the hardware device has not completed the access to the physical memory location, the processing device implements a copy-on-write policy for the virtual memory location.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: December 10, 2019
    Assignee: Red Hat Israel, Ltd.
    Inventor: Michael Tsirkin
  • Patent number: 10502782
    Abstract: A system and method for using unreachable states of a circuit design in a testing mode to increase random testability of a random resistant logic circuit. Control-improving logic circuitry is integrated into a logic circuit design to improve its testability and will not affect behavior of the design in its functional mode (by remaining “inactive” in the functional mode of the integrated circuit). The control-improving logic circuitry is automatically activated in testing mode. The control improving logic circuit is generated selectively for random resistant logic circuit regions that exhibit limited controllability in the functional mode and improves controllability of random resistant logic in the testing mode. The improved controllability results from activating test circuitry in the states that are not reachable during normal functionality.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: December 10, 2019
    Assignee: International Business Machines Corporation
    Inventors: Victor N. Kravets, Haoxing Ren, Mary P. Kusko, Spencer K. Millican
  • Patent number: 10504606
    Abstract: A memory device that supports a built-in self-test (BIST) operation includes: a plurality of memory cells; a page buffer group including page buffer circuits respectively coupled to the plurality of memory cells through bit lines; a built-in self-test (BIST) controller configured to generate pattern data to be stored in the page buffer circuits and reference data to be compared with sensed data obtained from the page buffer circuits, and to compare the reference data with the sensed data; and an input/output control circuit configured to input the pattern data to the page buffer circuits and to transfer the sensed data from the page buffer circuits to the BIST controller.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: December 10, 2019
    Assignee: SK hynix Inc.
    Inventors: Kyoung Han Kwon, Seung Wan Chai
  • Patent number: 10503725
    Abstract: A method for maintaining consistency in distributed databases includes receiving, by a coordinator from an application server, a transaction initiation message for a transaction. Additionally, the method includes determining whether to generate a distributed transaction identifier (DXID) for the transaction, including determining whether the transaction will be performed on a single data node or on multiple data nodes, determining to generate the DXID in response to determining that the transaction will be performed on the multiple data nodes, and generating, by the coordinator, the DXID corresponding to the transaction in response to determining to generate the DXID for the transaction. The method also includes sending, by the coordinator directly to a first data node, the DXID, sending, by the coordinator directly to a second data node, the DXID, and performing the transaction using the DXID.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: December 10, 2019
    Assignee: Futurewei Technologies, Inc.
    Inventor: Mason Sharp
  • Patent number: 10496335
    Abstract: In one embodiment, a storage device comprises non-volatile storage media; a controller to receive, from a host, an object definition command that identifies a first data object and a second data object and a transformation to apply to the first data object and the second data object to generate a first transformed object and store the first transformed object in the non-volatile storage media; and a transformation engine to apply the transformation to the first data object and the second data object.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: December 3, 2019
    Assignee: Intel Corporation
    Inventors: Jawad Basit Khan, Peng Li, Sanjeev Trika
  • Patent number: 10496499
    Abstract: An improved approach for disaster recovery is provided, along with corresponding systems, methods, and computer readable media. In the improved approach, a set of applications are assigned one or more application weightings (e.g., based upon asset type, a recovery time objective, a recovery time capability, a criticality to key business functions, vendor hosting, interfaces with other systems), etc. The one or more application weightings are utilized for ranking the applications, and the ranked set of applications is utilized to generate a disaster recovery boot sequence whereby specific recovery tasks and infrastructure device requirements are arranged temporally to achieve one or more recovery time conditions.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: December 3, 2019
    Assignee: ROYAL BANK OF CANADA
    Inventors: Elton Yuen, Jacqueline Kirkland, Michael Stoyke