Of Processor Patents (Class 714/10)
  • Patent number: 11487632
    Abstract: Improved techniques for disaster recover within storage area networks are disclosed. Embodiments include replicating a LIF of a primary cluster on a secondary cluster. LIF configuration information is extracted from the primary cluster. A peer node from a secondary cluster is located. One or more ports are located on the located peer node that match a connectivity of the LIF from the primary cluster. One or more ports are identified based upon one or more filtering criteria to generate a candidate port list. A port from the candidate port list is selected based at least upon a load of the port. Other embodiments are described and claimed.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: November 1, 2022
    Assignee: NetApp Inc.
    Inventors: Raj Lalsangi, Pramod John Mathew, Subramanian Natarajan, Santosh Rao
  • Patent number: 11472420
    Abstract: The machine learning device includes a predicting part configured to use a machine learning model to predict predetermined information, an updating part configured to update the machine learning model, and a part information acquiring part configured to detect replacement of a vehicle part and acquire identification information of the vehicle part after replacement. The updating part is configured to receive a new machine learning model trained using training data sets corresponding to the vehicle part after replacement from a server and apply the new machine learning model to the vehicle, if a vehicle part relating to input data of the machine learning model is replaced with a vehicle part of a different configuration.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: October 18, 2022
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Daiki Yokoyama, Yohei Hareyama
  • Patent number: 11457507
    Abstract: The present disclosure relates to a communication system for serial communication. The communication system may include a master communication device; and at least one slave communication device comprising a unique identifier, wherein the master communication device is connected to the at least one slave communication device via a signal line configured for communications, wherein the master communication device is configured to read at least a part of the unique identifier via the signal line, and assign an address to the at least one slave communication device based at least in part on the unique identifier, and transmit the address to the at least one slave communication device via the signal line.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: September 27, 2022
    Assignee: Phoenix Contact GmbH & Co. KG
    Inventors: Daniel Knoop, Irene Berthold
  • Patent number: 11443340
    Abstract: A method and digital signage player for managing display of a distributed digital signage content. The digital signage player stores the distributed digital signage content, and a local placement target for the distributed digital signage content. The digital signage player displays the distributed digital signage content in accordance with the local placement target. The digital signage player exchanges messages with a neighbor digital signage player, for increasing the local placement target of the distributed digital signage content at the request of the neighbor digital signage player. The neighbor digital signage player also displays the distributed digital signage content in accordance with its own placement target, which needs to be decreased. The digital signage player ultimately increases the local placement target of the distributed digital signage content based on the messages exchanged with the neighbor digital signage player.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: September 13, 2022
    Assignee: BROADSIGN SERV INC.
    Inventor: Bryan Mongeau
  • Patent number: 11440559
    Abstract: The machine learning device includes a predicting part configured to use a machine learning model to predict predetermined information, an updating part configured to update the machine learning model, and a part information acquiring part configured to detect replacement of a vehicle part and acquire identification information of the vehicle part after replacement. The updating part is configured to receive a new machine learning model trained using training data sets corresponding to the vehicle part after replacement from a server and apply the new machine learning model to the vehicle, if a vehicle part relating to input data of the machine learning model is replaced with a vehicle part of a different configuration.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: September 13, 2022
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Daiki Yokoyama, Yohei Hareyama
  • Patent number: 11442773
    Abstract: An equipment management method comprises a step A of registering, in a database, an alert that includes content of an equipment error, a step B of registering, in the database, a processing status that includes processing of the error, a step C of managing a thread for managing the alert and the processing status in a one-to-one relationship, and a step D of transmitting, to a user terminal, an error notification that includes information indicating generation of the error. The step D includes a step of, when two or more errors do not satisfy a predetermined condition, not integrating the two or more errors in one error notification, and, when the two or more errors satisfy the predetermined condition, integrating the two or more errors in one error notification.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: September 13, 2022
    Assignee: KYOCERA CORPORATION
    Inventors: Kei Iwata, Taku Nakayama, Takashi Furukawa
  • Patent number: 11443824
    Abstract: A memory device includes a memory cell array, an input/output circuit, a test register circuit, and a test control block. The memory cell array is suitable for storing data. The input/output circuit is suitable for inputting and outputting the data stored in the memory cell array. The test register circuit is suitable for testing the input/output circuit. The test control block includes a replica circuit having a replica configuration of the test register circuit by modeling the test register circuit, and is suitable for generating the data to test the test register circuit.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: September 13, 2022
    Assignee: SK hynix Inc.
    Inventors: Yucheon Ju, Hosung Cho
  • Patent number: 11442718
    Abstract: A non-volatile memory includes a first block and a second block. The first block is used to store first firmware. The second block is used to store second firmware. A method of controlling the non-volatile memory includes comparing a version of the first firmware and a version of the second firmware, if a comparison result between the version of the first firmware and the version of the second firmware indicates that the second firmware is newer than the first firmware, employing the second firmware to perform a boot process, and if the boot process is successful, upgrading a portion of a firmware image to the first block whenever there is a firmware upgrade request after the boot process.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: September 13, 2022
    Assignee: Realtek Semiconductor Corp.
    Inventor: Sheng-Kai Hung
  • Patent number: 11436186
    Abstract: An algorithmic matching pipelined compiler and a reusable algorithmic pipelined core comprise a high throughput processor system. The reusable algorithmic pipelined core is a reconfigurable processing core with a pipelined structure comprising a processor with a setup interface for programming any of a plurality of operations as determined by setup data, a logic decision processor for programming a look up table, a loop counter and a constant register, and a block of memory. This can be used to perform functions. A reconfigurable, programmable circuit routes data and results from one core to another core and/or IO controller and/or interrupt generator, as required to complete an algorithm without further intervention from a central or peripheral processor during processing of an algorithm.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: September 6, 2022
    Assignee: ICAT LLC
    Inventors: Robert D Catiller, Daniel Roig, Gnanashanmugam Elumalai
  • Patent number: 11429451
    Abstract: Examples are disclosed that relate to managing workloads provided by a plurality of clients to a shared resource. One example provides a computing device comprising a processor and a storage device storing instructions executable by the processor. The instructions are executable to provide a first workload from a first client and a second workload from a second client to a shared memory accessible by the first client, the second client, and a resource configured to process the first workload and the second workload. The computing device is configured to determine that an exception has occurred while processing the first workload, and to take an action to prevent execution of at least some additional work from the first client. The instructions are further executable to receive a result of processing the second workload after taking the action to prevent the execution of the additional work.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: August 30, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Chad R. Heinemann, Alexander Robert Paul Grenier, Ziyad Ahmad Ibrahim
  • Patent number: 11422876
    Abstract: A computer system includes a bus interface having error correction capability. The bus interface includes an error register that is configured to provide error information related to correctable errors. System software within the computer system is configured to obtain the error information from the error register and calculate a bit error metric based on the error information. A baseboard management controller within the computer system is configured to take an action in response to obtaining the bit error metric from the system software and determining that a condition related to the bit error metric has been satisfied.
    Type: Grant
    Filed: August 2, 2019
    Date of Patent: August 23, 2022
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Jeffrey Matthew Shuey, Neeraj Ladkani, Tao Liu, Subhasish Chakraborty
  • Patent number: 11418382
    Abstract: A method for cooperative active-standby failover between service routers based on health of services configured on the service routers is presented. In an embodiment, a method comprises determining, by a first service router (“SR”) of a SR cluster, a plurality of aggregate score values for a plurality of SRs of the SR clusters. The SR cluster comprises the first SR which is active, and a second SR. An aggregate score value, of the plurality of aggregate score values, indicates health of one or more services configured on a SR. The method further comprises determining, based on the plurality of aggregate score values, whether the first SR, of the SR cluster, is healthier than the second SR. In response to determining that the first SR is healthier than the second SR, the first SR continues to operate in the active mode; otherwise, the first SR switches to a standby mode.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: August 16, 2022
    Assignee: VMware, Inc.
    Inventors: Haihua Luo, Jerry Cheng, Kai-Wei Fan, Michael Hu
  • Patent number: 11403162
    Abstract: An information handling system includes a first memory with a video framebuffer, which in turn includes a regular video framebuffer and a diagnostic video framebuffer. Detected errors within the information handling system are stored within the diagnostic video framebuffer. In response to the error log data being stored within the diagnostic video framebuffer, a processing unit provides a notification signal. In response to the notification signal, a baseboard management controller reads the error log data from the diagnostic framebuffer, and stores the error log data in a second memory of the baseboard management controller.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: August 2, 2022
    Assignee: Dell Products L.P.
    Inventor: Andrew Butcher
  • Patent number: 11360846
    Abstract: Apparatuses of systems that provide Safety Integration Levels (SILs) and Hardware Fault Tolerance (HFT) include a first die, the first die including first processing logic connected to a first connection and the first connection connected to second processing logic of a second die. The first die may further include a second connection to an input/output (I/O) channel where the second connection is coupled to the first processing logic. The apparatuses may further include a second die, the second die including second processing logic and a third connection from a secondary device coupled to the second processing logic. The secondary device is outside the system. The second processing logic is configured to select among three configurations based on signals from the second processing logic and the secondary device: sending first output data on the I/O output channel, sending second output data on the I/O output channel, or de-energizing the I/O channel.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: June 14, 2022
    Assignee: Intel Corporation
    Inventors: Gabriele Boschi, Roger May, Gabriele Paoloni, Nabajit Deka, Matteo Salardi
  • Patent number: 11356362
    Abstract: Example methods and systems for a network management entity to perform adaptive packet flow monitoring. One example method may comprise receiving a request to monitor a packet flow between a first virtualized computing instance supported by a first host and a second virtualized computing instance supported by a second host. The method may also comprise activating a first set of checkpoints by instructing the first host and/or the second host to monitor the packet flow using the first set of checkpoints. The method may further comprise: in response to detecting a predetermined event based on first performance metric information associated with the packet flow, activating a second set of checkpoints by instructing the first host and/or the second host to monitor the packet flow using the second set of checkpoints.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: June 7, 2022
    Assignee: VMWARE, INC.
    Inventors: Ming Shu, Wenyu Zhang, Qiong Wang, Donghai Han
  • Patent number: 11354299
    Abstract: Described is a system, method, and computer program product to handle unresponsive node communications between two nodes of a database cluster. A high availability monitoring module is provided to address unresponsive node communications before having to automatically evict nodes from the cluster simply for exceeding a communications timeout period threshold.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: June 7, 2022
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Ming Zhu, Cheng-Lu Hsu
  • Patent number: 11340957
    Abstract: Techniques for managing computing devices involve: determining an associated weight of each storage device based on a mapping relationship between each storage device in storage devices and partitions included in a switch, the partitions being respectively associated with the computing devices, the storage devices being respectively connected to downstream physical ports of the switch; determining a total associated weight of a storage pool based on the associated weight of each storage device, the storage pool being created based on the storage devices; and if it is determined that the total associated weight does not satisfy a predetermined balance condition, adjusting the mapping relationship between the partitions and the downstream physical ports. Accordingly, such techniques can dynamically adjust the mapping between the partitions of the switch and downstream physical ports, thereby balancing the workloads on the computing devices and buses.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: May 24, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Min Zhang, Yechen Huang
  • Patent number: 11320797
    Abstract: Methods and apparatus to virtualize a process control system are described. A described process control system includes a server cluster including one or more servers. When operating, the server cluster provides a virtual workstation or virtual server, a virtual controller to interoperate with the virtual workstation or server and to implement process control operations, and a virtual input/output device to interoperate with the virtual controller and coupled to one or more field devices within the process control system.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: May 3, 2022
    Assignee: FISHER-ROSEMOUNT SYSTEMS, INC
    Inventors: Mark Nixon, John Mark Caldwell
  • Patent number: 11321259
    Abstract: A network architecture including network storage. The network architecture includes a plurality of streaming arrays, each streaming array including a plurality of compute sleds, wherein each compute sled includes one or more compute nodes. The network architecture includes a PCI Express (PCIe) fabric configured to provide direct access to the network storage from compute nodes of each of the plurality of streaming arrays, the PCIe fabric including a plurality of array-level PCIe switches, each array-level PCIe switch communicatively coupled to compute nodes of compute sleds of a corresponding streaming array and communicatively coupled to the storage server. The network storage is shared by the plurality of streaming arrays.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: May 3, 2022
    Assignee: Sony Interactive Entertainment Inc.
    Inventor: Roelof Roderick Colenbrander
  • Patent number: 11307921
    Abstract: One embodiment provides for a data processing system comprising multiple independent processors to execute multiple operating system environments of the data processing system, the multiple operating system environments to enable operation of multiple regions of a computing device associated with the data processing system. The multiple operating system environments are interconnected via a transport agnostic communication link. In response to detection of a fatal error in one or more of the multiple operating system environments, the multiple operating system environments coordinate performance of multiple separate error handling operations within the multiple operating system environments to generate a combined error log. The combined error log includes operational states of the multiple operating system environments.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: April 19, 2022
    Assignee: Apple Inc.
    Inventors: Christopher J. Noe, Joshua H. Berlin, Joseph J. Castro, Hardik K. Doshi, Joel N. Kerr, Kerry J. Kopp, Michael J. Smith
  • Patent number: 11256580
    Abstract: A failure detection circuit for a motor vehicle electronic computer, including: a main microcontroller having at least two microcontroller cores configured to execute the same instructions in parallel, and at least one first software module providing a critical function of a motor vehicle. The first software module includes a predetermined input point and a predetermined output point a supervision microcontroller and a synchronous communication interface for coupling the main microcontroller and the supervision microcontroller so as to enable mutual supervision. The detection circuit makes it possible to detect systematic and random failures.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: February 22, 2022
    Inventor: Vincent Egger
  • Patent number: 11228201
    Abstract: A power generating apparatus includes a power supply, a first sub-end circuit, a second sub-end circuit and an integrated signal generator. The first and second sub-end circuits respectively generate first and second sub-end standby power. The first sub-end circuit receives a first integrated control signal. The second sub-end circuit receives a second integrated control signal. The first sub-end circuit cuts off the first sub-end standby power according to the first integrated control signal and turns on the first sub-end standby power again after a first delay time. The second sub-end circuit cuts off the second sub-end standby power according to the second integrated control signal, and turns on the second sub-end standby power again after a second delay time. The integrated signal generator generates the first and second integrated control signals.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: January 18, 2022
    Assignee: Wistron Corporation
    Inventors: Zh-Wei Zhang, Syu-Siang Lee
  • Patent number: 11223515
    Abstract: The present disclosure is to more reliably determine whether an active-system server appropriately provides a service to a client. A cluster system (1) includes an active-system server (2) that provides a predetermined service to a client device through a network (4) and a standby-system server (3) that provides the predetermined service to the client device in place of the active-system server (2) when an abnormality occurs in the active-system server (2). The standby-system server (3) includes a monitoring unit (6) that accesses the predetermined service provided by the active-system server (2) through the network (4) to monitor whether the predetermined service is normally accessible. The active-system server (2) includes a cluster controlling unit (5) that performs a failover when the monitoring unit (6) of the standby-system server (3) determines that the predetermined service provided by the active-system server (2) is not normally accessible.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: January 11, 2022
    Assignee: NEC CORPORATION
    Inventor: Ryosuke Osawa
  • Patent number: 11204833
    Abstract: A method and apparatus for allocation of back-end (BE) logic resources between NVM sets. When a controller detects that an NVM set is in an idle state, it deallocates the BE logic from the originally assigned NVM set and provides the BE logic resource to another NVM set. An NVM set controller matrix maps interconnections between the BE logic resource and the new NVM set to enable use of the BE logic resource and the new NVM set. When a new command arrives for the originally assigned NVM set, the BE logic resources is re-allocated to the originally assigned NVM set.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: December 21, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Amir Rozen, Shay Benisty, Vitali Linkovsky
  • Patent number: 11183261
    Abstract: A testing device for memory includes a memory array and a test apparatus. The test apparatus includes a controller and a pattern generator. The pattern generator generates a background data, a first pattern data, and a second pattern data. The controller sets up the background data to a to-be-tested memory sub-array of the memory sub-arrays, performs a first memory test operation with the to-be-tested memory sub-array according to the first pattern data for detecting an occurrence of a hardware failure of the to-be-tested memory sub-array is occurred during the first memory test operation. The controller performs a second memory test operation with the to-be-tested memory sub-array according to the second pattern data for detecting the occurrence of the hardware failure of the to-be-tested memory sub-array during the second memory test operation in response to the hardware failure of the to-be-tested memory sub-array is not occurred during the first memory test operation.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: November 23, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hiroki Noguchi, Ku-Feng Lin, Yih Wang
  • Patent number: 11182175
    Abstract: The apparatus for workflow capture and display is provided with a plurality of modules configured to functionally execute the necessary steps of capturing task workflow information, storing the task workflow information captured by the capture module in a data storage device, retrieving a portion of the task workflow information from the data storage device in response to a first event, and presenting the task workflow information in response to a second event. These modules in the described embodiments include a capture module, a storage module, an assembly module, and a presentation module.
    Type: Grant
    Filed: September 18, 2008
    Date of Patent: November 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey John Smith, David Thomas Windell
  • Patent number: 11176002
    Abstract: Methods, apparatuses and systems for cloud-based disaster recovery are provided. The method, for example, includes configuring, at a cloud-based computing platform, workloads including servers used by a client machine, the workloads configured based on user information provided at the client machine, determining if the workloads are compliant with one or more objectives, if the configured workloads are compliant with the one or more objectives, merging the workloads for creating a declaration comprising generated steps to which the servers are added, restoring the servers for each of the generated steps of the declaration upon receiving, from the client machine, a failure indication associated with the servers.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: November 16, 2021
    Assignee: Storage Engine, Inc.
    Inventors: Trevor Savino, James Patrick Hart, Justin Furniss, Charles Wooley
  • Patent number: 11176012
    Abstract: Briefly, example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, to determine indicators of potential errors in a multi-processing core lockstep computing device comprising a plurality of processing cores, based, at least in part, on observations of output signals generated by at least two processing cores of the plurality of processing cores. A built-in self-test (BIST) procedure may then be based, at least in part, on the determining indicators.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: November 16, 2021
    Assignee: Arm Limited
    Inventors: Emre Ozer, Xabier Iturbe, Balaji Venu
  • Patent number: 11169840
    Abstract: A method includes, with a Virtual Network Function (VNF) manager, managing a VNF that includes a plurality of VNF components running on a plurality of virtual machines, the virtual machines running on a plurality of physical computing machines, and with the VNF manager, causing a Network Function Virtualization Infrastructure (NFVI) to have a total number of virtual machines provisioned, the total number being equal to a number of virtual machines capable of providing for a current demand for VNF components plus an additional number of virtual machines equal to the highest number of virtual machines being provided by a single one of the plurality of physical computing machines.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: November 9, 2021
    Assignee: GENBAND US LLC
    Inventor: Paul Miller
  • Patent number: 11163667
    Abstract: A method is provided comprising: storing one or more tickets in a ticket database, each of the tickets being associated with a corresponding test system, and each of the tickets being associated with an error that is generated as a result of executing one of a plurality of tests on the ticket's corresponding test system; executing a reclamation agent that is configured to: retrieve a plurality of tickets from a ticket database, detect if each of the tickets satisfies a predetermined condition, and return the ticket's corresponding test system to a pool of available test systems when the predetermined condition is satisfied by the ticket.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: November 2, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Ilan Yosef, Shay Goldshmidt
  • Patent number: 11160052
    Abstract: Provided are a method for adjusting a broadcast receiver queue, an apparatus, a storage medium, and an electronic device. The method may include: acquiring a historical parameter of a broadcast receiver; determining whether the historical parameter meets a first predefined condition; when the historical parameter of a first target broadcast receiver in a first broadcast receiver queue meets the first predefined condition, generating a second broadcast receiver queue; and moving the first target broadcast receiver to the second broadcast receiver queue, such that broadcast receivers other than the first target broadcast receiver in the first broadcast receiver queue and the first broadcast receiver in the second broadcast receiver queue may process the broadcast messages in parallel.
    Type: Grant
    Filed: September 9, 2019
    Date of Patent: October 26, 2021
    Assignee: GUANGDONG OPPO MOBILE TELECOMMUNICATIONS CORP., LTD.
    Inventors: Liangjing Fu, Runsheng Pei, Zhiyong Lin, Ruyu Wu, Jun Zhang
  • Patent number: 11144374
    Abstract: Example implementations relate to preserving data availability in a constrained deployment of an HA system (e.g., an HA storage system) in the presence of pending faults. According to an example, a first arbiter, acting as a witness to facilitate maintaining quorum for the HA system, and a first node are provided within a first failure domain; and a second arbiter, serving as a backup arbiter, and a second node are provided within a second failure domain. Responsive to receipt of an indication of a pending fault impacting the first failure domain by a member of the current configuration of the HA system, establishment of a new configuration, excluding the first arbiter and including the second arbiter, is initiated. Responsive to a majority of the current configuration installing the new configuration, the second arbiter is enabled to serve as the active arbiter by transferring state information to the second arbiter.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: October 12, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Bradford Glade, Peter Corbett
  • Patent number: 11126573
    Abstract: Systems and methods of managing variable size load units of application codes in a processing system include identifying pages of a random access memory (RAM) device to store copies of load units from an external memory device upon request by a bus master in the processing system. The RAM device is internal to an integrated circuit device that includes the bus masters, and the external memory device is external to the integrated circuit device. The bus masters execute the application codes, and each of the application codes comprise one or more load units that include executable program instructions. At least some of the load units have different sizes from one another. A page type indicator is determined for an identified page. A first page type indicates whether the identified page is a split page to store a segment of each of two different load units.
    Type: Grant
    Filed: July 29, 2020
    Date of Patent: September 21, 2021
    Assignee: NXP USA, Inc.
    Inventors: Michael Rohleder, Cristian Macario, Dirk Moeller
  • Patent number: 11108883
    Abstract: Systems and methods are disclosed herein for obtaining data about a network having at least a first node and a second node. A server transmits to the first node a first request for the first node to send a communication to the second node. The server is outside of the network, and the first request includes a first address of the first node and a second address of the second node. The server receives, from the first node, an indication of whether the communication to the second node is successful. The server receives, from the first node, a second request for access to a file stored on the server, determines that the file is stored locally at the second node, and transmits, to the first node, an instruction to retrieve the file from the second node, when the communication to the second node is successful.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: August 31, 2021
    Assignee: Google LLC
    Inventors: Nicholas Mark Vasic Cooper, Max Ward-Graham
  • Patent number: 11086746
    Abstract: A node in network is configured to buffer data received from other nodes across multiple channels. The node process a portion of the buffered data associated with a subset of those channels. When the node receives data on that subset of channels that includes a notification, the node then processes a larger portion of the buffered data associated with a larger number of channels. In doing so, the node may identify additional notifications include within data that was buffered but not previously processed. The node may also coordinate with other nodes in order to process buffered data upon identification of a notification.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: August 10, 2021
    Assignee: ITRON NETWORKED SOLUTIONS, INC.
    Inventor: Elad Gottlib
  • Patent number: 11068348
    Abstract: This application discloses a method and an enable apparatus for starting a physical device, where the physical device includes N central processing units (CPUs) and at least one platform controller hub (PCH), N is greater than one. Each of the N CPUs is electrically coupled to a PCH in the at least one PCH. The method includes determining a second CPU in the N CPUs as the primary CPU when a fault occurs in a first CPU, where the first CPU is the primary CPU configured to start the physical device before the fault occurs in the first CPU, and triggering the second CPU as the primary CPU and in cooperation with a first PCH to start the physical device, where the first PCH is one PCH in the at least one PCH.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: July 20, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Ben Chen
  • Patent number: 11061674
    Abstract: Apparatuses and methods are disclosed for an FPGA architecture that may improve processing speed and efficiency in processing less complex operands. Some applications may utilize operands that are less complex, such as operands that are 1, 2, or 4 bits, for example. In some examples, the DSP architecture may skip or avoid processing all received operands or may process a common operand more frequently than other operands. An example apparatus may include configurable logic blocks including DSP slices and an interconnected coupling the configurable logic blocks. An operand register of a DSP slice may include an operand input that is coupled to an output of that DSP slice.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: July 13, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Gregory Edvenson, David Hulton, Jeremy Chritz
  • Patent number: 11055363
    Abstract: A method for distributed multi-choice voting/ranking in a network with a plurality of nodes associated to a set of choices is disclosed. The method includes setting a plurality of value sets for a plurality of nodes, setting a plurality of collections of memory sets for the plurality of nodes, and updating the plurality of value sets. In addition, the method includes updating the plurality of collections of memory sets, calculating a majority vote for the set of choices, and calculating a rank set for the set of choices.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: July 6, 2021
    Inventors: Saber Salehkaleybar, Arsalan Sharifnassab, S. Jamaloddin Golestani
  • Patent number: 11048570
    Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and a computer system are provided. The computer system includes an initialization component of a host. The initialization component obtains health data indicating that at least one hardware component of the host is in one of one or more predetermined health conditions when executed in a system management mode of the host. The initialization component then sends, to a service processor of the host, a message in accordance with a management protocol. The message includes the health data.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: June 29, 2021
    Assignee: AMERICAN MEGATRENDS INTERNATINOAL, LLC
    Inventors: Manickavasakam Karpagavinayagam, Manish Jha, Harikrishna Doppalapudi, Purandhar Nallagatla, Chandrasekar Rathineswaran
  • Patent number: 11023290
    Abstract: A processing system comprising an arrangement of tiles and an interconnect between the tiles. The interconnect comprises synchronization logic for coordinating a barrier synchronization to be performed between a group of the tiles. The instruction set comprises a synchronization instruction taking an operand which selects one of a plurality of available modes each specifying a different membership of the group. Execution of the synchronization instruction cause a synchronization request to be transmitted from the respective tile to the synchronization logic, and instruction issue to be suspended on the respective tile pending a synchronization acknowledgement being received back from the synchronization logic. In response to receiving the synchronization request from all the tiles in the group as specified by the operand of the synchronization instruction, the synchronization logic returns the synchronization acknowledgment to the tiles in the specified group.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: June 1, 2021
    Assignee: Graphcore Limited
    Inventors: Daniel John Pelham Wilkinson, Simon Christian Knowles, Matthew David Fyles, Alan Graham Alexander, Stephen Felix
  • Patent number: 11017032
    Abstract: Systems and methods for the presentation content on client computing devices. A processing component serializes browser data as a set of serialized data portions that can be incorporated into a serialization file. The serialized data portions can be prioritized to determine an order of priority and the serialized data portions can further be processed in parallel. As the serialized data portions are processed, they can be added to the serialized data file with a completion marker. If the serialization process is interrupted before all the browser information is serialization, the browser is still able to utilize any portions in the serialized data file that are accompanied by a completion marker.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: May 25, 2021
    Assignee: Amazon Technologies, Inc.
    Inventor: Jari Juhani Karppanen
  • Patent number: 10990462
    Abstract: Disclosed herein are various embodiments that perform application-aware input/output (I/O) fencing operations, certain of which embodiments include, in response to detection of a network partition event in a cluster, determining a first application weight, determining whether the first one or more application instances should be delayed in a cumulative fencing race, performing the cumulative fencing race (in response to a determination that the first one or more application instances should be delayed in the cumulative fencing race), and performing the cumulative fencing race without introducing the delay with regard to the first one or more application instances (in response to a determination that the first one or more application instances should not be delayed in the cumulative fencing race).
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: April 27, 2021
    Assignee: Veritas Technologies LLC
    Inventors: Jai Gahlot, Abhijit Toley
  • Patent number: 10976793
    Abstract: A rack computer system can provide data indicating electrical power consumption by separate sets of the mass storage devices, including separate individual mass storage devices, of the rack computer system. A power sensor can be electrically coupled to a power transmission line for each mass storage device. The power sensor can be coupled to the power transmission line externally to the mass storage device. The power sensor can be an internal power sensor of the mass storage device, where a mass storage device microcontroller transmits internally-generated data to an external power monitoring system. A microcontroller can transmit the data to a baseboard management controller via a side-band connection between the mass storage device and the controller. The data can be transmitted via an in-band connection between a baseboard management controller and an instance of firmware which accesses internally-generated data from mass storage device microcontrollers.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: April 13, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Felipe Enrique Ortega Gutierrez, Jason Alexander Harland, Roey Rivnay, David Edward Bryan, Christopher Strickland Beall
  • Patent number: 10956288
    Abstract: A device may provision two or more servers, each of the servers including a network interface. In addition, the device may enable the network interface in each of the provisioned servers, create a shared volume, assign the shared volume to each of the provisioned servers, and enable a clustering application on each of the provisioned servers to form a cluster comprising the provisioned servers, the cluster having a heartbeat via the network interfaces.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: March 23, 2021
    Assignee: salesforce.com, inc.
    Inventors: Emily Katherine Witt, Richard Cooke, William Thomas Everhart, Jr., Jinendrakumar J. Patel, Vijay Kumar
  • Patent number: 10949213
    Abstract: A computer system, processor, and method for processing information is disclosed that includes partitioning a logical register in the processor into a plurality of ranges of logical register entries based upon the logical register entry, assigning at least one recovery port of a history buffer to each range of logical register entries, initiating a flush recovery process for the processor, and directing history buffer entries to the assigned recovery port based upon the logical register entry associated with the history buffer entry.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: March 16, 2021
    Assignee: International Business Machines Corporation
    Inventors: Steven J. Battle, Salma Ayub, Brian D. Barrick, Joshua W. Bowman, Susan E. Eisen, Brandon Goddard, Christopher M. Mueller, Dung Q. Nguyen
  • Patent number: 10904339
    Abstract: Various embodiments are generally directed to techniques for reducing the time required for a node to take over for a failed node or to boot. An apparatus includes an access component to retrieve a metadata from a storage device coupled to a first D-module of a first node during boot, the metadata generated from a first mutable metadata portion and an immutable metadata portion, and the first metadata specifying a first address of a second D-module of a second node; a replication component to contact the second data storage module at the first address; and a generation component to, in response to failure of the contact, request a second mutable metadata portion from a N-module of the first node and generate a second metadata from the second mutable metadata portion and the immutable metadata portion, the second mutable metadata portion specifying a second address of the second D-module.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: January 26, 2021
    Assignee: NetApp Inc.
    Inventors: Paul Yuedong Mu, Manoj Sundararajan, Paul Ngan
  • Patent number: 10896146
    Abstract: A system and method for determining reliability-aware runtime optimal processor configuration can integrate soft and hard error data into a single metric, referred to as the balanced reliability metric (BRM), by using statistical dimensionality reduction techniques. The BRM can be used to not only adjust processor voltage to optimize overall reliability but also to adjust the number of on-cores to further optimize overall processor reliability. In some implementations, both coarse-grained actuations, based on optimal core count, and fine-grained actuations, based on optimal processor voltage (Vdd), may be used, where feedback control can recursively re-compute soft and hard error data based on a new configuration, until convergence at an optimal configuration.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: January 19, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karthik V. Swaminathan, Ramon Bertran Monfort, Alper Buyuktosunoglu, Pradip Bose, Nandhini Chandramoorthy, Chen-Yong Cher
  • Patent number: 10884796
    Abstract: Systems and methods are described herein for job execution using system critical threads. An in-memory database system having pages loaded into a memory and having associated physical disk storage generates a safety critical thread pool. The safety critical thread pool has one or more safety critical threads associated with flushing the pages to the physical disk storage. Execution of the one or more safety critical threads is initiated within the safety critical thread pool. A job request to access data stored within the physical disk storage is received. Utilization levels of the one or more safety critical threads are monitored. Execution of the job request is permitted based on the utilization levels associated with the one or more safety critical threads.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: January 5, 2021
    Assignee: SAP SE
    Inventors: Tobias Scheuer, Dirk Thomsen
  • Patent number: 10887382
    Abstract: Methods, apparatuses, and systems for cloud-based disaster recovery are provided. The method, for example, includes receiving, at a cloud-based computing platform, backup information associated with a backup vendor used by a client machine, storing, at the cloud-based computing platform, the backup information associated with the backup vendor, receiving, at the cloud-based computing platform from the client machine, a failure indication for a server associated with the backup vendor, and creating a virtual server corresponding to the server using the stored backup information at the cloud-based computing platform.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: January 5, 2021
    Assignee: Storage Engine, Inc.
    Inventors: Trevor Savino, James Patrick Hart, Justin Furniss, Charles Wooley
  • Patent number: 10877858
    Abstract: Described is a system, method, and computer program product for identifying communication failures between nodes of database cluster system where each member node within the cluster constantly monitors itself. Upon detection of a node communication failure by a particular node, the particular node notifies other member nodes of the cluster that the particular node is having communication problems with other nodes of the database cluster by communicating through a different communication channel with the other nodes so that the particular node may be evicted from the cluster efficiently.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: December 29, 2020
    Assignee: Oracle International Corporation
    Inventors: Ming Zhu, Andrey Gusev