Abstract: A fault-tolerant data storage system associates durability requirements of service level agreements (SLAs) for volumes stored in the fault-tolerant data storage system with volume partitions stored in the fault-tolerant data storage system. For a given volume partition, volume data is stored in two or more replicas on two or more different system components and/or erasure encoded across multiple other system components. The fault-tolerant data storage system uses the respective durability requirements of the SLAs and failure statistics of the system components to allocate bandwidth for replacing lost instances of redundantly stored volume data such that the lost data is replaced within a target time calculated to guarantee the durability requirements of the SLAs are satisfied.

Abstract: A method for determining a clock drift comprises determining a drift of a clock relative to a reference clock based on two signals from the reference clock and a further signal. The method can be used for time synchronization and is suitable for implementation on resource-constrained devices. An anchor point implementing the method and a real-time locating system comprising such an anchor point are also disclosed.

Abstract: A method, an apparatus and a device for detecting an optical module, and a storage medium are provided. The method includes: constructing insertion loss ranges meeting an insertion loss specification that respectively correspond to different signal frequencies in a predetermined signal frequency range, to construct a target insertion loss region; acquiring a microstripline length, a stripline length, a via number and a connector number of a to-be-detected optical module; inputting the microstripline length, the stripline length, the via number and the connector number to a pre-constructed first model, to determine an insertion loss curve of the to-be-detected optical module in the signal frequency range; and determining that the to-be-detected optical module is unqualified if a part of the insertion loss curve is outside the target insertion loss region.

Abstract: Technologies for accelerated edge data access and physical data security include an edge device that executes services associated with endpoint devices. An address decoder translates a virtual address generated by a service into an edge location using an edge translation table. If the edge location is not local, the edge device may localize the data and update the edge translation table. The edge device may migrate the service to another edge location, including migrating the edge translation table. The edge device may monitor telemetry and determine on a per-tenant basis whether a physical attack condition is present. If present, the edge device instructs a data resource to wipe an associated tenant data range. The determinations to localize remote data, to migrate the service, and/or whether the physical attack condition is present may be performed by an accelerator of the edge device. Other embodiments are described and claimed.

Abstract: In one embodiment, a network device includes frequency generation circuitry configured to generate a clock signal, a phase-locked loop (PLL) configured to generate a local clock based on the clock signal, a plurality of receivers configured to receive respective data streams from respective remote clock sources, each receiver of the plurality of receivers being configured to recover a remote clock from a respective data stream, and a controller configured to identify the remote clock recovered by one of the plurality of receivers as a master clock, find a clock differential between the identified remote clock and the local clock, and provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuitry to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential.

Abstract: An information processing system includes a plurality of information processing apparatuses each of which includes hardware, a control processor, and a switch circuit wherein when a failure of a first control processor in a first information processing apparatus of the plurality of information processing apparatuses is detected, a first switch circuit in the first information processing apparatus is configured to generate a connection of first hardware in the first information processing apparatus to a signal line between the first information processing apparatus and a second information processing apparatus of the plurality of information processing apparatuses, a second switch circuit in the second information processing apparatus is configured to generate a connection of a second control processor in the second information processing apparatus to the signal line, and the second control processor is configured to acquire information transmitted from the first hardware via the signal line.

Abstract: Methods and apparatus for a synchronized multi-directional transfer on an inter-processor communication (IPC) link. In one embodiment, the synchronized multi-directional transfer utilizes one or more buffers which are configured to accumulate data during a first state. The one or more buffers are further configured to transfer the accumulated data during a second state. Data is accumulated during a low power state where one or more processors are inactive, and the data transfer occurs during an operational state where the processors are active. Additionally, in some variants, the data transfer may be performed for currently available transfer resources, and halted until additional transfer resources are made available. In still other variants, one or more of the independently operable processors may execute traffic monitoring processes so as to optimize data throughput of the IPC link.

Abstract: In order to facilitate automatic roll-forward updates, embodiments include detecting a failure in a software package. In response to the failure, data indicative of a current version of a software package is extracted from a release directory. In response to the application data, a base repository with a version history of the application is cloned. In response to the cloning, a prior set of changes from the base repository in the temporary directory, where the prior set of changes form an old application version of the application, is imported. In response to the import of the prior set of changes, the current version is overwritten with the prior set of changes to generate a new version. The new version is pushed directly to the base repository and a deployment API causes the new version to replace the current version.

Abstract: In order to efficiently transmit measurement packets to a plurality of receiving devices at a constant transmission interval, provided is a packet transmission method that comprises a procedure in which transmission requests for a packet sequence composed of a plurality of packets transmitted at a first time interval are grouped every first time interval, and the packet sequence is transmitted on the basis of a transmission request for a group for which the number of transmission requests is at least a specified value.

Abstract: Disclosed are methods, systems, and processes to improve extent map performance A request for a data block is received. In response to detecting a cache miss, a temporary table is searched for the data block. If the data block is not found in the temporary table, a base table is searched for the data block.

Abstract: Methods, apparatuses and systems for cloud-based disaster recovery are provided. The method, for example, includes receiving, at a cloud-based computing platform, backup information associated with backup vendors used by a client machine; storing, at the cloud-based computing platform, the backup information associated with the backup vendors; periodically updating, at the cloud-based computing platform, the backup information associated with each of the backup vendors at a predetermined polling interval for each of the backup vendors; receiving, at the cloud-based computing platform from the client machine, a failure indication for a server associated with at least one of the backup vendors; and restoring the server using the stored backup information at the cloud-based computing platform.

Abstract: A receiver for receiving data in a broadcast system comprises a broadcast receiver configured to receive, via said broadcast system, a receiver input data stream comprising a plurality of channel symbols represented by constellation points in a constellation diagram. A demodulator demodulates said channel symbols into codewords and a decoder decodes said codewords into output data words. A redundancy unit selects or requests, if demodulation of a channel symbol and/or decoding of a codeword is erroneous or likely to fail, redundancy data for demodulation of future channel symbols and/or decoding of future codewords via a broadband system and a broadband receiver obtains said redundancy data via said broadband system. Said demodulator and/or said decoder is configured to use the obtained redundancy data to demodulate the respective future channel symbols and to decode the respective future codewords, respectively.

Abstract: A method for diagnosing a root cause of failure using automated test equipment is disclosed. The method comprises monitoring data traffic associated with testing a device under test (DUT) in the automated test equipment using a plurality capture modules, wherein the plurality of capture modules are programmed onto a programmable logic device, wherein the programmable logic device is controlled by a system controller and is operable to generate commands and data to test the DUT, wherein the plurality of capture modules are operable to selectively capture the data traffic to be monitored, and wherein the data traffic monitored comprises a flow of traffic between the DUT and the system controller. The method further comprises saving results associated with the monitoring in respective memories associated with each of the plurality of capture modules. Further, the method comprises transmitting the results upon request to an application program executing on the system controller.

Abstract: An apparatus has two or more processing elements to redundantly process a same processing workload; and divergence detection circuitry to detect divergence between the plurality of processing elements. When a correctable error is detected by error detection circuitry of an erroneous processing element, the erroneous processing element signals detection of the correctable error to another processing element, to control the other processing element to delay processing to maintain a predetermined time offset between the erroneous processing element and the other processing element.

Abstract: A virtual memory including virtual addresses may be generated. A first virtual address of the virtual memory may be mapped to a first physical address of a one-time programmable (OTP) memory of a device. Furthermore, a second virtual address of the virtual memory may be mapped to a second physical address of a static memory of the device. The virtual memory that is mapped to the OTP memory and the static memory may be provided for accessing of the data of the OTP memory of the device.

Abstract: An example method to provide a storage service in a virtualized computing environment may include obtaining network latency information associated with various hosts in the virtualized computing environment. In response to identifying a first network latency value that exceeds a threshold, wherein the first network latency is between the first host and a second host in the virtualized computing environment, the method includes placing the second host in a first cohesive cluster consisting of the second host. In response to identifying a second network latency value being less than or equal to the threshold, wherein the second network latency value is between the first host and a third host in the virtualized computing environment, the method includes grouping the first host and the third host in a second cohesive cluster. The method includes initiating configuration of resources in the first cohesive cluster and the second cohesive cluster to support the storage service.

Abstract: A method to check for redundancy in two or more data lines comprises receiving data on a first data line, computing a first cyclic redundancy check (CRC) value on the data of the first data line, performing an exclusive OR (XOR) function on the first CRC value with a stored memory value, and updating the stored memory value with a result of the XOR function, and repeating on additional data lines until a last line is processed such that an error is indicated if a final stored memory value is not zero. An apparatus to check that two cores are operating in lockstep comprises a first core comprising a first data checker, a second core comprising a second data checker, and a lockstep checker to compare an output of the first data checker with an output of the second data checker.

Abstract: An artificial intelligence system and method securely stores all executable binary object code of a client/user's computer-based software applications in a separate and impenetrable Sealed-off Central Processing Unit (SCPU). The SCPU is shielded from any external communication interface by having no input ports or devices able to receive external transmissions. The SCPU executes four primary functions: 1. constantly reads all the primary object code in the client/user's application system; 2. simultaneously compares and matches the application system executable object code to the shielded executable object code copy stored in the SCPU; 3. permanently blocks the unmatched object code section(s) pending internal IT security team review of the unmatched object code; and, 4. notifies the client/user's authorized IT security authority of the blocked object code section(s) and submits to them a copy of the potentially invalid object code.

Abstract: A method for updates in a storage system is provided. The method includes writing identifiers, associated with data to be stored, to storage units of the storage system and writing trim records indicative of identifiers that are allowed to not exist in the storage system to the storage units. The method includes determining whether stored data corresponding to records of identifiers is valid based on the records of the identifiers and the trim records.

Abstract: An object of the present invention is to reduce a time taken for updating of firmware data using unrecoverable data in an apparatus having a plurality of nonvolatile memories. The present invention is an apparatus having a plurality of nonvolatile memories, the apparatus including: an acquisition unit configured to acquire firmware updating data for updating firmware data saved in each of the plurality of nonvolatile memories; and a control unit configured to perform control so as to perform in parallel updating of the firmware data saved in a first nonvolatile memory by unrecoverable data included in the acquired firmware updating data and updating of the firmware data saved in a second nonvolatile memory by the unrecoverable data.

Abstract: Fault detection devices, systems and methods are provided which implement identical processors. A first processor is configured to receive a first set of variables, execute a first firmware based on the first set of variables, and output a first result of the executed first firmware. A second processor, identical to the first processor, is configured to receive a second set of variables, execute a second firmware based on the second set of variables, and output a second result of the executed second firmware. The first firmware and the second firmware provide a same nominal function in a diverse manner for calculating the first result and the second result, respectively, such that the first result and the second result are expected to be within a predetermined margin. Thus, a fault can be detected by comparing the first and the second results.

Abstract: The management computer has a memory which stores management information and management programs, and a CPU which refers to the management information and executes the management programs; the management information includes storage management information for allowing determination as to whether the plurality of storage resources can be paired in a redundant configuration, and couplable configuration management information for determining whether the plurality of storage resources and the plurality of server resources can be connected to each other; and when the CPU deploys a virtual machine, the CPU first determines, by reference to the storage management information, storage resources to be paired in a redundant configuration, then selects, by reference to the couplable configuration management information, server resources each of which can be connected to a respective one of the storage resources that are to be paired in a redundant configuration, and pairs the selected server resources in the redundant c

Abstract: An efficient facility for determining resource usage, such as a processor time used by tasks. The determination is performed on behalf of user applications that do not require a call to operating system services. The facility includes an instruction that determines elapsed time and reports it to the user as a single unit of operation.

Abstract: An electronic device capable of placing restrictions on processor usage is disclosed. The electronic device may include: a memory; and a processor including a first core and a second core. The memory may store instructions that, when executed by the processor, cause the first core to transition from an active state to an idle state in response to a restriction signal for the first core, and cause the first core to transition to a power save state when the first core remains in the idle state for at least a preset time. For hot-unplugging, as the electronic device does not transition a core to an offline state, it does not have to perform cleanup operation on the memory and variables. Hence, it is possible to reduce the latency time due to hot-unplugging.

Abstract: To checkpoint a shared state in a distributed system, a node may first isolate itself from communication with other nodes of a distributed system. The node may then store a checkpoint of the shared state. The node then restarts and attempts to initialize its operating state from the stored checkpoint. In response to successfully initializing its operating state, the node restores communication with one or more other nodes of the distributed system. The node then indicates to the one or more other nodes that the stored checkpoint of the shared state is valid.

Abstract: A data storage system and method are provided for storing data in non-volatile memory devices. Binary data is received for storage in a non-volatile memory device. The binary data is converted into non-binary data comprising base-X values, where X is an integer greater than two. The non-binary data is encoded to generate a codeword and the codeword is written to a wordline of the non-volatile memory device.

Abstract: Techniques for system recovery using a failover processor are disclosed. A first processor, with a first instruction set, is configured to execute operations of a first type; and a second processor, with a second instruction set different from the first instruction set, is configured to execute operations of a second type. A determination is made that the second processor has failed to execute at least one operation of the second type within a particular period of time. Responsive to determining that the second processor has failed to execute at least one operation of the second type within the particular period of time, the first processor is configured to execute both the operations of the first type and the operations of the second type.

Abstract: A computer-implemented method for channel switching in a mesh network is described. In one embodiment, a beacon is sent. The beacon includes a channel change request in both proprietary and standard formats. The channel change request includes an instruction to change to a particular channel and a timing synchronization function identifying when the change to the particular channel should occur. The timing synchronization function is used to determine that the time has arrived to change to the particular channel. The particular channel is changed to synchronously with all other access points in a mesh network.

Abstract: Provided is a processor system including a first processor driven by a first driving voltage and a first driving clock, a second processor driven by a second driving voltage and a second driving clock and configured to perform an identical task to the first processor, and a defect detector configured to perform level synchronization or clock domain synchronization on a first output signal provided from the first processor and a second output signal provided from the second processor to compare the first and second output signals, wherein the first and second driving voltages are respectively provided from mutually independent power supply sources and the first and second driving clocks are respectively provided from mutually independent clock generators.

Abstract: A method for executing an executable file. The method includes executing instructions in the executable file by a first process, receiving a write request from a second process to write to the executable file, generating an anonymous file from the executable file in response to the write request, executing the anonymous file by the first process, and accessing the executable file by the second process.

Abstract: Example pin electronics includes driver circuitry to output a first optical signal to a UUT. The first optical signal is based on a first signal representing first informational content and one or more second signal representing first parametric information. Receiver circuitry receives a second optical signal from the UUT. The second optical signal is related to a third signal representing second informational content and one or more fourth signal representing second parametric information. Comparison circuitry obtains parametric data representing at least one of the first parametric information or the second parametric information, and compares, based on the parametric data, the at least one of the first parametric information or the second parametric information to one or more thresholds. Control circuitry adjusts at least some of the first parametric information prior to output of the first optical signal, and one or more of the thresholds.

Abstract: A processor system includes a master processor that successively processes a plurality of tasks, a checker processor that successively processes at least one of the plurality of tasks, and a control circuit that performs control so that the checker processor operates when the master processor and the checker processor perform a lock-step operation, and the checker processor stops its operation when the master processor and the checker processor do not perform the lock-step operation, the lock-step operation being an operation in which each of the master and checker processors processes the same task, in which the control circuit performs control so that a period from when a task is processed by the lock-step operation to when another task is processed in the next lock-step operation is equal to or shorter than a maximum test period, the maximum test period being a test period acceptable to the processor system.

Abstract: Conventional semiconductor devices are problematic in that an operation cannot be continued in the event of a failure of one of CPU cores performing a lock step operation and, as a result, reliability cannot be improved. The semiconductor device according to the present invention includes a computing unit including a first CPU core and a second CPU core that perform a lock step operation, wherein the first CPU core and the second CPU core respectively diagnose failures of internal logic circuits, and a sequence control circuit switches the CPU core that outputs data to a shared resource, in the computing unit based on the diagnosed result.

Abstract: A storage device includes a nonvolatile memory, a cache memory, and a processor configured to load, from the nonvolatile memory into the cache memory, a fragment of each layer of an address mapping corresponding to a target logical address, and access the nonvolatile memory at a physical address mapped from the target logical address, by referring to the fragments of the layers of the address mapping loaded into the cache memory. The layers are arranged in a hierarchy and each layer of the address mapping except for the lowermost layer indicates correspondence between each of segmented logical address ranges mapped in the layer and a physical location of an immediately-lower layer in which said each segmented logical address range is further mapped in a narrower range. The lowermost layer indicates correspondence between each logical address mapped therein and a physical location of the nonvolatile memory associated therewith.

Abstract: One or more techniques and/or systems are provided for mirror vote synchronization. For example, a first storage device is located at a first storage site, and a second storage device is located at a second storage site. The second storage device is configured according to a data mirroring configuration where data from the first storage device is mirrored to the second storage device. Mirror vote metadata is generated based upon an up-to-date state of the data mirroring configuration. The mirror vote metadata indicates whether the first storage device and/or the second storage device are up-to-date or not. The mirror vote metadata may be replicated between the first storage site and the second storage site. If the first storage site fails, then the second storage site may provide switchover operation using the second storage device based upon the mirror vote metadata.

Abstract: Techniques are provided for dependency-aware transaction batching for data replication. A plurality of change records corresponding to a plurality of transactions is read. Inter-transaction dependency data is generated, the inter-transaction dependency data including at least one inter-transaction dependency relationship between a plurality of pending transactions. Each inter-transaction dependency relationship indicates that a first transaction is dependent on a second transaction. A batch transaction is generated based on the inter-transaction dependency data. The batch transaction includes at least one pending transaction of the plurality of pending transactions. The batch transaction is assigned to an apply process of a plurality of apply processes configured to apply batch transactions in parallel.

Abstract: One embodiment of the present invention sets forth a technique for efficiently performing voting operations within a multi-threaded parallel-processing system. A group of related parallel program threads executes within a processor core together in parallel. A new instruction, called a “vote” instruction, is introduced that enables a parallel program thread to post an individual vote within the context of the group of related threads and to receive the result of the vote. In this fashion, the vote instruction advantageously reduces overhead associated with inter-thread communication, thereby improving overall system performance.

Abstract: The disclosure relates to an apparatus and method for false pass detection in lockstep dual processing core systems, triple modular redundancy (TMR) systems, or other redundant processing systems. A false pass occurs when two processing cores generate matching data outputs, both of which are in error. A false pass may occur when the processing core are both subjected to substantially the same adverse condition, such as a supply voltage drop or a sudden temperature change or gradient. The apparatus includes processing cores configured to generate first and second data outputs and first and second timing violation signals. A voter-comparator validates the first and second data outputs if they match and the first and second timing violation signals indicate no timing violations. Otherwise, the voter comparator invalidates the first and second data outputs. Validated data outputs are used for performing additional operations, and invalidated data outputs may be discarded.

Abstract: Metadata can be provided to multiple processing units of a database system by using local storages respectively provided for the processing units, such that a local storage is accessible only to its respective processing unit. As a result, processing units can access metadata when needed (e.g., when needed to process a database request at runtime) without having to access a source external to the database system. In addition, metadata (e.g., an XML object, XML schema, XSLT stylesheets, XQuery modules) can be provided using a database request or command, for example, by using a register statement.

Abstract: Fault detection devices, systems and methods are provided which implement identical processors. A first processor is configured to receive a first measurement, execute a first firmware based on the first measurement, and output a first result of the executed first firmware. A second processor, identical to the first processor, is configured to receive a second measurement, execute a second firmware based on the second measurement, and output a second result of the executed second firmware. The first firmware and the second firmware provide a same nominal function in a diverse manner for calculating the first result and the second result, respectively, such that the first result and the second result are expected to be within a predetermined margin. Thus, a fault can be detected by comparing the first and the second results.

Abstract: A method, apparatus, and device for locating a software failure are disclosed. The method comprises: determining a locating start time; obtaining a system environment at the locating start time; reproducing a running state of the software from the locating start time to an occurrence time of a software failure in the system environment at the locating start time; determining a cause of the software failure based on the reproduced running state. The apparatus comprises: a determination module, an obtaining module, a reproduction module, and an analysis module. Through this approach, automatic locating of a software failure is implemented, which helps the user to be aware of the operation problem and facilitates a software developer to find a deficiency in the software design.

Abstract: Techniques are provided for performing automated operations to enable first-failure data capture functionality during initialization of multiple lockstep processors. Following a hardware reset of two lockstep processors, an indication is received of one or more crosscheck errors regarding the operation of the two lockstep processors. In response to the crosscheck errors, crosscheck first-failure data capture (FFDC) data is saved to one or more memory areas that are persistent across a hardware reset, and it is determined whether a predefined reset threshold has been satisfied. Responsive to determining that the predefined reset threshold has been satisfied, the crosscheck FFDC data from the one or more persistent memory areas is analyzed and one or more crosscheck initialization codes are responsively generated. An additional hardware reset is initiated.

Abstract: The present invention relates to a distributed fault-tolerant control system for a modularized wind turbine or wind power plant system comprising sub-assemblies, the control system comprising 1) fault-tolerant control means adapted to generate control set-points and/or data values, said fault-tolerant control means being distributed in sub-assemblies in accordance with the modularization of the wind turbine or wind power plant system, and 2) fault-tolerant communication network for transmitting control set-points and/or data values at essentially the same time to a plurality of nodes in the distributed control system, said plurality of distributed nodes being capable of selecting a valid transmission package out of two or more transmission packages provided on the fault-tolerant communication network.

Abstract: Embodiments enable distributed data processing with automatic caching at multiple system levels by accessing a master queue of data processing work comprising a plurality of data processing jobs stored in a long term memory cache; selecting at least one of the plurality of data processing jobs from the master queue of data processing work; pushing the selected data processing jobs to an interface layer including (i) accessing the selected data processing jobs from the long term memory cache; and (ii) saving the selected data processing jobs in an interface layer cache of data processing work; and pushing at least a portion of the selected data processing jobs to a memory cache of a first user system for minimizing latency in user data processing of the pushed data processing jobs.

Abstract: One embodiment of the present invention discloses a shared non-volatile memory (“NVM”) system using a distributed flash translation layer (“FTL”) scheme capable of facilitating data storage between multiple hosts and NVM devices. A process of shared NVM system includes an NVM management module or memory controller able to receive a request from a host for reserving a write ownership. The write ownership allows a host to write information to a portion of storage space in an NVM device. Upon identifying availability of the write ownership associated with the NVM device in accordance with a set of predefined policy stored in the NVM management module, the request is granted to the host if the write ownership is available. The host is subsequently allowed to fetch the FTL snapshot from the NVM device for the write operation.

Abstract: In a storage system, first and second controllers have respective first and second buffer and cache areas. The first controller stores write data in accordance with a write request in the first cache area without involving the first buffer area and to transfer the stored write data to the second cache area without involving the second buffer area. The first controller is configured to determine which of the first and second cache areas is to be used as a copy source and to be used as a copy destination depending on whether the storing of the first write data in the first cache area had been successful or on whether the transfer of the write data from the first cache area to the second controller had been successful, and by copying data from the copy source to the copy destination, recovers data in an area related to a transfer failure.

Abstract: Generating instructions, in particular for mailbox verification in a simulation environment. A sequence of instructions is received, as well as selection data representative of a plurality of commands including a special command. Repeatedly selecting one of the plurality of commands and outputting an instruction based on the selected command. The outputting of an instruction includes outputting a next instruction in the sequence of instructions if the selected command is the special command, and outputting an instruction associated with the command if the selected command is not the special command.

Abstract: A translation lookaside buffer (TLB) stores translation entries. The translation entries include a virtual address, a physical address and a memory local/not-local flag. When a processor is in a low power/local memory mode a virtual address is received. A matching translation entry has a local/not-local flag. Upon the local/not-local flag indicating the physical address of the matching translation entry being outside the local memory, an out-of-access-range memory access exception is generated.

Abstract: In one embodiment, an integrated circuit has one or more multi-channel transmitters, each transmitter having synchronization circuitry that synchronizes different copies of a reset signal used to reset different sets of TX channel circuitry used to generate the multiple TX signals, to reduce the skew between the different TX signals. Each set of synchronization circuitry has (at least) two synchronization stages that re-time different copies of the reset signal to a selected clock signal. In one implementation, the integrated circuit has (at least) two quads, each of which can generate four different TX signals, where both quads can be configured to use the same clock signal to re-time different copies of the reset signal such that the eight different TX signals are all synchronized to one another.

Abstract: A method for updates in a storage system is provided. The method includes writing identifiers, associated with data to be stored, to storage units of the storage system and writing trim records indicative of identifiers that are allowed to not exist in the storage system to the storage units. The method includes determining whether stored data corresponding to records of identifiers is valid based on the records of the identifiers and the trim records.