Abstract: A method for expanding a cluster system is provided. The cluster system includes at least one Cluster Central Chassis (CCC), and a newly-added Cluster Line-card Chassis (CLC) connected with the CCC to form the cluster system. The method includes the following steps. A control plane is established. An equipment management right is switched to the CCC, so that the CCC manages the newly-added CLC. Meanwhile, a cluster line-card device, a cluster central exchange device, and a cluster system are further provided. In implementation, smooth expansion can be achieved without interrupting running equipment services in the CLC current network and without interrupting data services. Moreover, during the expansion process, hardware equipment needs not to be replaced, thus investment of users on the equipment is reduced.

Abstract: Systems and methods enable a virtual machine, including any applications executing thereon, to quickly start executing and servicing users based on pre-staged data blocks supplied from a backup copy in secondary storage. An enhanced media agent may pre-stage certain backed up data blocks which may be needed to launch the virtual machine, based on predictive analysis pertaining to the virtual machine's operational profile. The enhanced media agent may also pre-stage backed up data blocks for a virtual-machine-file-relocation operation, based on the operation's relocation scheme. Servicing read requests to the virtual machine may take priority over ongoing pre-staging of backed up data. Read requests may be tracked so that the media agent may properly maintain the contents of an associated read cache. Some embodiments of the illustrative storage management system may lack, or may simply not require, the relocation operation, and may operate in a “live mount” configuration.

Abstract: In an approach for determining a location of failure between interconnects/controller, a computer collects debug information simultaneously at a plurality of nodes coupled to an interconnect. Subsequent to collecting debug information, the computer analyzes the debug information collected simultaneously thereby determining which end of the interconnect caused the failure.

Abstract: Methods and apparatus are disclosed to capture error conditions in lightweight virtual machine managers. A disclosed example method includes defining a shared memory structure between the VMM and a virtual machine (VM), when the VM is spawned by the VMM, installing an abort handler on the VM associated with a vector value, in response to detecting an error, transferring VMM state information to the shared memory structure, and invoking the abort handler on the VM to transfer contents of the shared memory structure to a non-volatile memory.

Abstract: A method for transition of control from a first controller to a second controller includes communicatively coupling the first controller and the second controller, such that at least one input signal received by one controller is mutually provided to the other controller and such that at least one output signal generated by one controller is mutually provided to the respective other controller. The method includes disconnecting at least one output line from the first controller, connecting the at least one output line to the second controller, and supplying an output signal to the at least one output line. The method includes, before disconnecting at least one output line from the first controller, supplying a logical high signal to the output line by an external voltage source if the first output signal is a logical high signal or if the output line is at a logical high state during normal operation.

Abstract: A method and system for maintaining release consistency in shared memory programming on a computing device having multiple processing units includes, in response to a page fault, initiating a transfer, from one processing unit to another, of data associated with more than one but less than all of the pages of shared memory.

Abstract: A method of providing high integrity communication in a high integrity processing system having at least two redundant application processors in a non-lockstep configuration where the redundant application processors are running the same application and where the redundant application processors are connected to at least one input/output processor by a communication channel.

Abstract: A system includes a safety relevant component that generates a data packet in response to receiving a request to perform a task and that communicates the data packet. The system further includes a first fail-safe chassis (FSC) that continuously generates a first and second chassis health signals, that determines whether the data packet is valid, and that selectively determines whether to de-assert the first and second chassis health signals based on the determination. The system also includes a second FSC that continuously generates a third a fourth chassis health signals, that determines whether a data packet is valid, and that selectively determines whether to de-assert the third and fourth chassis health signals based on the determination. The system includes a direct connect algorithm state machine that determines whether to instruct the one of the first and second FSCs to operate in a predetermined mode based on the chassis health signals.

Abstract: Exemplary controllers in a system are associated with technical entities and are configured to selectively execute tasks in a primary mode when the controllers interact with the associated technical entities with respect to the tasks, and to execute tasks in a secondary mode when the controllers do not interact with the associated technical entities with respect to the task. The system distributes task instructions of a first task to a first controller that is configured to execute the first task in the primary mode, and to distribute the task instructions of the first task to a second controller that is configured to execute the first task in the secondary mode. The system distributes task instructions of a second task to the second controller that is configured to execute the second task in the primary mode.

Abstract: A system and methodology to monitor system resources for a cluster computer environment and/or an application instance allows user to defined failover policies that take appropriate corrective actions when a predefined threshold is met. An engine comprising failover policies and mechanisms to define resource monitoring, consumption, allocation, and one or more thresholds for a computer server environment to identify capable servers and thereafter automatically transition an application between multiple servers so as to ensure the application is continually operating within the defined metrics.

Abstract: Executing each portion of a stream of program instructions as a transaction for reliability, a computer system supporting transactional execution mode processing is provided. Included is determining that an instruction in a portion of the stream of program instructions begins a transaction; based on beginning the transaction, saving a snapshot of system state information and executing the portion of the stream of program instructions as a transaction until an end-mode test point in the stream of program instruction is reached. Based on reaching the end-mode test point, committing store data of the transaction to memory; and based on the stream of program instructions not being complete, automatically beginning a new transaction of a next portion of the stream of program instructions or based on aborting the transaction, re-executing the transaction based on the saved snapshot of the system state information.

Abstract: Systems and methods for increasing robustness of a system with a remote server are provided. Some methods can include a first system remotely controlling a second system, detecting a failure in the first system or in a communication link between the first system and the second system, and temporarily removing control of the second system from the first system.

Abstract: A method of testing a multi-core network processor comprises placing the multi-core network processor in an online environment. A test is performed on a core of the multi-core network processor when the core is idle, and the core is released from the test when it is completed and resumes processing data in the online environment. In another embodiment, a network processor comprises a computer readable instructions module and a processing core. The computer readable instructions module is configured to store test instructions, and the processing core is configured to operate in an online environment and execute the test instructions to test the processing core when the processing core is idle. In yet another embodiment, an apparatus comprises a multi-core network processor that is configured to execute test instructions to perform a test on a core of the multi-core network processor when the core is idle.

Abstract: Embodiments of the invention relate to dynamically routing instructions to execution units based on detected errors in the execution units. An aspect of the invention includes a computer system including a processor having an instruction issue unit and a plurality of execution units. The processor is configured to detect an error in a first execution unit among the plurality of execution units and adjust instruction dispatch rules of the instruction issue unit based on detecting the error in the first execution unit to restrict access to the first execution unit while leaving un-restricted access to the remaining execution units of the plurality of execution units.

Abstract: The present invention relates to a storage device that uses a flash memory that performs power loss recovery, and to a method of power loss recovery by using the storage device using the flash memory. The storage device stores change information on metadata in physical pages in which one or more logical pages are compressed and stored. The change information on the metadata is information representing how the metadata is changed in association with data in the one or more logical pages. The storage device may synchronize the metadata in the flash memory and recover the metadata by applying the change information on the metadata to the synchronized metadata when a power supply is disrupted.

Abstract: Data processing system efficiency is improved by automatically determining whether to adjust for a next time interval a number N of processors running within the system for processing a workload. The automatically determining includes obtaining a measure of operating system overhead by evaluating one or more characteristics of processor time of the N processors consumed within the system for a time interval, and obtaining a measure of system utilization of the N processors running within the system for processing the workload for the time interval. The automatically determining further includes automatically ascertaining whether to adjust the number N of processors running within the system for the next time interval to improve system efficiency using the obtained measure of operating system overhead and the obtained measure of system utilization of the N processors.

Abstract: A nonvolatile storage device in accordance with the inventive concepts includes a nonvolatile memory device comprising a first memory area, a second memory area, and a memory controller. The memory controller includes a first register configured to store reliable mode information, and a second register configured to store operating system (OS) image information. The memory controller is configured to receive a command from a host based on the reliable mode information; determine whether the command is a write request for an OS image and whether OS image information accompanying the command matches the OS image information stored in the second register; write the OS image to the first memory area if the OS image information accompanying the command matches the OS image information stored in the second register, and block data migration of the OS image from the first memory area to the second memory area.

Abstract: A method for managing resources of a processor device configured to control an automation installation includes using at least one first operating system and at least one second operating system, which preferably differs from the first operating system, to operate the processor device. The processor device includes at least two processor cores configured to operate the operating systems. The method further includes using at least one processor core to operate each operating system and freely selecting a number of processor cores used to operate the first operating system and a number of processor cores used to operate the second operating system.

Abstract: A storage apparatus is provided with a virtualization mechanism which manages first and second LPARs (logical partitions) assigned respectively with first and second logical resources acquired by logically partitioning physical resources in the storage apparatus. The virtualization mechanism provides a shared memory area which is an area based on a memory and can be accessed by the first and second LPARs. The first LPAR stores information required for taking over a data input/output process handled by the first LPAR to the second LPAR, in the shared memory area. When detecting that a fault occurs in the first LPAR, the second LPAR acquires the information required for taking over from the shared memory area and takes over and executes the data input/output process formerly handled by the first LPAR on the basis of the information required for taking over.

Abstract: A fan-out wafer comprises a first IC die having at least a first boundary scan cell (BSC) and a second BSC. The first BSC is coupled to a first demultiplexer. The second BSC is coupled to a first pad. A second IC die has at least a third BSC coupled to a second demultiplexer, and a second pad connected to the first pad. A first master path connects the first demultiplexer to the second demultiplexer. A first slave path connects the first demultiplexer to the second demultiplexer. The first pad and second pad are located between the first master path and the first slave path.

Abstract: Input filters correlate to target components. For a given target component, the input filter defines input validation information. The input filter might also define conversions or transformations to be applied to valid input prior to being provided to the target component. At build time, code is accessed that contains the input validation, conversion and transformation and that identifies the associated target component. The information is then used to construct an input filter. At run time, when an input processing component receives an input, the input processing component identifies the target component, accesses the associated input filter, and uses the information contained in the input filter to determine whether the input is valid, and whether and how to convert and transform the value.

Abstract: The existence of errors and bugs in device drivers and other software operating in kernel space may be difficult to find and eliminate. A system and method for debugging computer programs may involve the use of several different modules. Running in the kernel space is an event monitor. Running in the user space is an event collector, an event player, and a concurrency error detector. This setup allows one to debug device driver software and other software that executes in kernel space using existing user space error detectors.

Abstract: To have a problem of occurrence of the same failure in failure detection of a microcontroller. A microcontroller has a CPU and a data access control circuit. The data access control circuit performs two types of accesses: an individual access in which a data access of the CPU is performed for each thread, and a shared access in which a data access of the CPU is performed by executing two threads. The data access control circuit detects a failure of the CPU by making a comparison between the command and the address, respectively, in the shared access generated by executing the two threads.

Abstract: Embodiments relate to multithreading in a computer. An aspect is a computer including a configuration having a core which includes physical threads and is operable in single thread (ST) and multithreading (MT) modes. The computer also includes a host program configured to execute in the ST mode on the core to issue a start-virtual-execution (start-VE) instruction to dispatch a guest entity which includes a guest virtual machine (VM). The start-VE instruction is executed by the core and includes obtaining a state description, having a guest state, from a location specified by the start-VE instruction. The execution includes determining, based on the guest state, whether the guest entity includes a single guest thread or multiple guest threads, and starting the guest threads in the MT mode or ST mode based on the guest state and a determination of whether the guest entity includes a single guest thread or multiple guest threads.

Abstract: An approach to determine whether errors associated with transmitted data are associated with a transmitting device, a receiving device, and/or a connecting device that connects the transmitting device to the receiving device. The approach includes a method that includes receiving transmitted data with a buffer. The approach further includes analyzing the transmitted data which includes an error correcting process to detect errors and determine that the transmitted data has an error that requires additional analysis. The approach further includes determining that the error is associated with a receiving device, the transmitting device, or a connecting device that connects the receiving device and the transmitting device.

Abstract: In a hardware-based virtualization system, a hypervisor switches out of a first function into a second function. The first function is one of a physical function and a virtual function and the second function is one of a physical function and a virtual function. During the switching a malfunction of the first function is detected. The first function is reset without resetting the second function. The switching, detecting, and resetting operations are performed by a hypervisor of the hardware-based virtualization system. Embodiments further include a communication mechanism for the hypervisor to notify a driver of the function that was reset to enable the driver to restore the function without delay.

Abstract: According to one aspect, a computer system includes a configuration with a machine enabled to operate in a single thread (ST) mode and a multithreading (MT) mode. In addition, the machine includes physical threads. The machine is configured to perform a method that includes issuing a start-virtual-execution (start-VE) instruction to dispatch a guest entity having multiple logical threads on the core. The guest entity includes all or a part of a guest virtual machine (VM), and issuing is performed by a host running on one of the physical threads on the core in the ST mode. The executing of the start-VE instruction by the machine includes mapping each of the logical threads to a corresponding one of the physical threads, initializing each of the mapped physical threads with a state of the corresponding logical thread, and starting execution of the guest entity on the core in MT mode.

Abstract: A disclosed information processing method is executed by a computer and includes: storing context representing a state of a processor in the computer into a certain area of plural areas included in a memory of the computer, wherein same data is stored in each of the plural areas by memory mirroring; performing a setting to switch a type of the certain area from a type of an area for which the memory mirroring is performed to a type of an area for securing data; and upon detecting that reset of the computer was performed, recovering, by using the computer, the state of the processor by using data stored in the certain area.

Abstract: A computer-implemented method for managing failover clusters. The method may include maintaining a failover cluster comprising first and second cluster nodes, identifying a first instance of a service group on the first cluster node, and initiating failover of the first cluster node to the second cluster node. The method may also include bringing at least a portion of a second instance of the service group online before taking the first instance of the service group completely offline. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A computer-implementable method. In one embodiment, the method includes the step of initializing operation of a physical service processor to communicatively couple to a remote file system over a communications link. The remote file system has a computer-executable development module for modifying at least one network configuration setting for the physical service processor. The method also includes the step of causing the development module to modify at least one network configuration setting on a virtual service processor that is operative to emulate operation of the physical service processor, and the step of initializing operation of the virtual service processor with the at least one modified network configuration setting. The method further includes the step of verifying that the virtual service processor, when initialized with the at least one modified network configuration setting, operates without error.

Abstract: This disclosure describes different ways to improve the operation of a device's 1149.1 TAP to where the TAP can perform at-speed Update & Capture, Shift & Capture and Back to Back Capture & Shift operations. In a first embodiment of the disclosure the at-speed operations are achieved by time division multiplexing CMD signals onto the TMS input to the TAP. The CMD signals are input to a CMD circuit that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit. In a second embodiment of the disclosure the at-speed operations are achieved by detecting the TAP's Exit1DR state as a CMD signal that is input to the CMD circuit that operates in conjunction with a Dual Port Router to execute the at-speed operations of a circuit.

Abstract: In an example embodiment, a method of performing a health check on a process integration (PI) component is provided. A PI health check scenario is loaded into the PI component, the PI health check scenario including a reference to a list of checks. The PI health check scenario is then executed using the PI component, causing one or more checks in the list of checks to be performed at a predetermined frequency. The system can then automatically determine if one or more of the one or more checks fail.

Abstract: A bridge receives a power down command and in response converts the power down command to a data hardening command. The bridge issues the data hardening command to a solid state disk. In response to the data hardening command, data stored on the solid state disk is hardened. The hardening comprises writing data in volatile memory to non-volatile memory. The data that is hardened comprises user data and protected data. The data hardening command optionally comprises one or more of a flush cache command, a sleep command, and a standby immediate command.

Abstract: A computer program execution record and replay system providing recorded execution event breakpoints is described. In one embodiment, for example, in the record and replay system, a method for providing recorded execution event breakpoints, the method comprising: recording information about one or more execution events that occur during a recorded execution of a computer program; during a replay execution of the computer program in which a particular execution event of the one or more execution events is faithfully reproduced, determining whether a breakpoint is to be set in the replay execution of the computer program based on the recorded information about the particular execution event; and if the breakpoint is to be set, then setting a breakpoint in the replay execution of the computer program such that the replay execution breaks at a point corresponding to the faithful reproduction of the particular execution event.

Abstract: The invention relates to a method of enabling multiple operating systems to run concurrently on the same computer, the method comprising: scheduling a plurality of tasks for execution by at least first and second operating systems, wherein each task has one of a plurality of priorities; setting the priority of each operating system in accordance with the priority of the next task scheduled for execution by the respective operating system; and providing a common program arranged to compare the priorities of all operating systems and to pass control to the operating system having the highest priority. Accordingly, the invention resides in the idea that different operating systems can be run more efficiently on a single CPU by changing the priority of each operating system over time. In other words, each operating system has a flexible priority.

Abstract: A method of testing the coherency of data storage in a memory shared by multiple processor cores through core interconnects in a device under test (DUT) includes running test patterns including data transactions between the processor cores and the shared memory, and comparing the results of the data transactions with expected results. The test patterns include false sharing operations and irritator operations causing memory thrashing.

Abstract: Cascading failover of blade servers in a data center implemented by transferring by a system management server a data processing workload from a failing blade server to an initial replacement blade server, with the data processing workload characterized by data processing resource requirements and the initial replacement blade server having data processing resources that do not match the data processing resource requirements; and transferring by the system management server the data processing workload from the initial replacement blade server to a subsequent replacement blade server, where the subsequent replacement blade server has data processing resources that better match the data processing resource requirements than do the data processing resources of the initial replacement blade server.

Abstract: Cascading failover of blade servers in a data center implemented by transferring by a system management server a data processing workload from a failing blade server to an initial replacement blade server, with the data processing workload characterized by data processing resource requirements and the initial replacement blade server having data processing resources that do not match the data processing resource requirements; and transferring by the system management server the data processing workload from the initial replacement blade server to a subsequent replacement blade server, where the subsequent replacement blade server has data processing resources that better match the data processing resource requirements than do the data processing resources of the initial replacement blade server.

Abstract: A simulation environment verifies processor-sparing functions in a simulated processor core. The simulation environment executes a first simulation for a simulated processor core. During the simulation, the simulation environment creates a simulation model dump file. At a later point in time, the simulation environment executes a second simulation for the simulated processor core. The simulation environment saves the state of the simulated processor core. The simulation environment then replaces the state of the simulated processor core by loading the previously created simulation model dump file. The simulation environment then sets the state of the simulated processor core to execute processor-sparing code and resumes the second simulation.

Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for aggregating source code metric values. One of the methods includes obtaining data representing a directed graph, wherein one or more nodes of the graph are associated with a respective set of one or more metric instances, wherein each set of metric instances for each node includes all metric instances occurring in sets of any node descendant from the node in the graph, wherein each metric instance identifies a location in a source code base, and wherein each metric instance has a respective metric value, a respective identifier, and a respective attribute type. An attribute value is computed for a first node in the graph from the respective metric value of each metric instance in a first set of metric instances associated with the first node.

Abstract: An apparatus for accelerating communications over the Ethernet between a first processor and a second processor where the communications include CIP messages, the apparatus comprising a network accelerator that includes memory locations, the accelerator associated with the first processor and programmed to, when the second processor transmits a data packet to the first processor over the Ethernet, intercept the data packet at a first processor end of the Ethernet, extract a CIP message from the data packet, parse the CIP message to generate received data, store the received data in the memory locations and provide a signal to the first processor indicating that data for the first processor in stored in the memory locations.

Abstract: It is a purpose of the invention to provide a fault detection system, etc., having improved fault coverage with a reduced number of test patterns to be input to a logic circuit. The fault detection system detects a fault in a logic circuit based on multiple output logic values of the logic circuit after a test input pattern is input. The output logic values are input to the logic circuit as an updated test input pattern. The system comprises: a first acquisition unit which acquires a part of or all of the output logic values; a comparison unit which compares the logic values acquired by the first acquisition unit with those predicted for when there are no faults, or for when there is a specific fault; and a fault judgment unit which judges whether or not there is a fault based on the comparison result obtained by the comparison unit.

Abstract: A system allowing for path monitoring and notification in a system of switching elements and processing elements is provided. An exemplary technique uses a monitoring and notification module configured to generate and output monitoring messages across multiple paths defined by the plurality of switching elements and the plurality of processing elements, detect a fault in the system based on the monitoring messages, and generate and output multiple alert messages across the multiple paths to initiate recovery from the fault As such, a single element (or group of elements) does not become isolated from the rest of the elements in the system.

Abstract: The invention aims to provide a method and a system on chip able to detect at once hardware and software errors to prevent manipulations for retrieving cryptographic keys, inserting or suppressing instructions to bypass security processes, modifying programs or memory content etc. The system on chip comprises a core including at least two processors, registers, and a data consistency check module. The core is connected to at least one set of memories containing zones for instructions of a first program and of a second program, said instructions being to be executed respectively by the first and second processor, which respectively produce and store result data into the registers and the memories.

Abstract: A data maintenance device includes: a first storage including volatile storage media; a second storage including nonvolatile storage media; an electronic circuit unit including at least one volatile register; and a selector configured to select one of the first and the second storage to be accessed by the electronic circuit unit. The selector selects the first storage in a state where data processing performed by the electronic circuit unit is ongoing, and the second storage in a state where the data processing is stopped for a shutdown of electric power of the data processing apparatus. The electronic circuit unit stores register data in the storage selected by the selector, the register data being stored in the register at the time when the data processing is stopped for the shutdown.

Abstract: An active network system for a host device with a host processor, comprises a wireless port including a first physical layer/medium access control (PHY/MAC) device. A first wired port includes a second PHY/MAC device. A secondary processor communicates with the wireless port, the first wired port and the host processor. The secondary processor, the wireless port and the first wired port support network functionality when the host processor is an inactive mode. The network functionality includes at least one of access point functionality, router functionality, repeater functionality, point-to-point functionality and point-to-multipoint functionality.

Abstract: In a processor, a decode unit identifies instructions needing a checkpoint and enables selected checkpoints. A register file unit includes a plurality of architectural registers. A first set of checkpoint registers correspond to a first checkpoint. Each checkpoint register corresponds to a corresponding architectural register. A first set of indicators correspond to the first set of checkpoint registers to indicate whether the corresponding architectural register has been modified or is intended to be modified prior to enabling of the first checkpoint. A second set of indicators correspond to the first set of checkpoint registers and indicate whether the corresponding architectural register has been modified or is intended to be modified after enabling the first checkpoint.

Abstract: An apparatus is provided comprising a detector, a memory, and a logic component. The detector is configured to receive a rotary motion input signal and a counter signal and to send a plurality of time values based on the input signal and the counter signal. The memory stores the plurality of time values in an ordered sequence and is coupled to the detector. The logic component selects time values stored in the memory by skipping a predefined number of time values in the ordered sequence, reads the selected time values to determine a coherent set of data values, and sends the coherent set of data values.

Abstract: Mechanism for consistent core hang detection on a processor with multiple processor cores, each having one or more instruction execution pipelines. Each core may also include a hang detection unit with a counter unit that may generate a count value based on a clock source having a frequency that is independent of a frequency of a processor core clock. The hang detection unit may also include a detector logic unit that may determine whether a given instruction execution pipeline has ceased processing a given instruction based upon a state of the processor core and whether or not the given instruction has completed execution prior to the count value exceeding a predetermined value.

Abstract: A partition manager relocates a logical partition from a primary shared processor pool to a secondary shared processor pool in response to a predetermined condition, such as a hardware failure. The relocated logical partition is allocated a smaller quantity of processing units from the secondary pool than it was allocated from the primary pool. A quantity of processing units reserved for a second logical partition is identified in the secondary shared processor pool, and a portion of those reserved processing units are allocated to the relocated logical partition. The reserved processing units may be redistributed among multiple relocated logical partitions.