Abstract: A system and method for test generation for system level verification using parallel algorithms are provided. The present invention generates test patterns for system level tests by exploiting the scalability of parallel algorithms while allowing for data set coloring and expected result checking. Based on the characteristics of the system being tested an iterative parallel algorithm is selected from a plurality of possible parallel algorithms. The selected parallel algorithm is then separated into separate program statements for execution by a plurality of processors. A serial version of the selected algorithm is executed to generate a set of expected results. The devised parallel version of the selected algorithm is then run to generate a set of test result data which is compared to the set of expected results. If the two sets of data match, it is determined that the system is operating correctly.

Abstract: A computer cluster includes a network plane and a processing plane. In the cluster, the network plane is formed by at least one network computer, which is configured to assign a time tag to incoming request data. The processing plane is composed of at least two processing computers, which are supplied in parallel with the request data from the network plane. Each processing computer is configured to process the request data in a subsequent processing step, if the current value of the time tag falls within a respective significant value range. An “implicit synchronisation” of the computers is thus achieved in a simple manner.

Abstract: The present invention is directed to a system and method for actively auditing a software system to determine the status. The software system includes a plurality of processes executed in an active processor domain. An active message is generated for processing in the active processor domain. Each process receiving the message modifies it by adding an active time indicator to it; thereby creating a modified active message. The status of the active processor domain is determined in response to the modified active message.

Abstract: A method, apparatus, and computer instructions for managing processors in a data processing system. Monitoring is performed for a failed processor in the processors. Responsive to detecting a failed processor, a spare processor from the set of spare processors is identified. The set of spare processors are located on different modules and wherein the spare processor is identified as minimizing degradation in processing performance.

Abstract: Disclosed herein are a system and method for designing digital circuits. In some embodiments, the digital circuits include processors having dedicated messaging hardware that enable processor cores to minimize interrupt activity related to inter-core communications. The messaging hardware receives and parses any message in its entirety prior to passing the contents of the message on to the digital circuit. In other embodiments, the digital circuit functionalities are partitioned across individual cores to enable parallel execution. Each core may be provided with standardized messaging hardware that shields internal implementation details from all other cores. This modular approach accelerates development and testing, and renders parallel circuit design to more efficiently attain feasible speedups. These digital circuit cores may be homogenous or heterogeneous.

Abstract: A method and system for restoring basic functionality to a portable computer system via a server accessed remotely by telephone. A user of a portable computer system which has lost data and software which was held in volatile memory may connect to a server to restore basic functionality to the portable computer system. The server may be an enterprise or a web-based server. The connection may be made, for instance, over a 1-800 or a 1-900 telephone line. The server transfers sufficient software to the RAM of the portable computer for it to regain basic functionality. For example, synchronization software may be transferred to the portable computer. The portable computer may then use the synchronization software to synchronize via the server or host connection more fully in order to restore lost data or lost software applications that were stored on a server or on a host computer system.

Abstract: A distributed computing system can be operated in a fault tolerant manner using a collection of auxiliary computing devices and more main computing devices than the number of faults the system can tolerate. A quorum of all of the main computing devices can be used. In the event of a failure, an alternative quorum from a selected set of quorums, comprising at least one main computing device and some or all of the auxiliary computing devices, can be used to complete pending operations and to select a new set of quorums. Alternatively, another state machine, comprising at least one main computing device and some or all of the auxiliary computing devices, can select a new quorum comprising the currently operating main computing devices, and the new quorum can then complete pending operations and can continue to select proposals using the proposal number assigned by the other state machine.

Abstract: Multiple Array Management Functions (AMFs) are connected to multiple redundancy groups over a storage area network (SAN), such as a fiber-channel based SAN. The multiple AMFs share management responsibility of the redundancy groups, each of which typically includes multiple resources spread over multiple disks. The AMFs provide concurrent access to the redundancy groups for associated host systems. When a host requests an AMF to perform an operation on a resource, the AMF synchronizes with the other AMFs sharing control of the redundancy group that includes the resource to be operated on, so as to obtain a lock on the resource. While performing the operation, the AMF send replication data and state information associated with the resource such that if the AMF fails, any of the other AMFs are able to complete the operation and maintain data reliability and coherency.

Abstract: A system is provided which includes a microprocessor comprising a first processing unit to generate a first output signal and a second processing unit to generate a second output signal, and comparison means, coupled to the microprocessor, to detect whether the first output signal differs from the second output signal.

Abstract: A system and method for replicating a multithreaded application program using a semi-active or passive replication strategy, wherein the application program executes under the control of an operating system having a thread library. The method comprises piggybacking mutex ordering information at the Primary replica onto regular multicast messages specifying the order in which threads in the Primary replica have been granted their claims to mutexes; and receiving the multicast messages at a Backup replica containing the mutex ordering information which determines the order in which threads in the Backup replica are granted mutexes. Thread library interpositioning is preferably utilized to intercept calls to functions in the operating system's thread library, so that the system and method of the invention may be implemented transparently. The invention enforces strong replica consistency without the need to count instructions, add significant messaging overhead, or modify application code.

Abstract: A method in a computer system for enabling a process to manage the execution of a periodic, single-execution (PSE) task is disclosed. The process represents one of a plurality of processes executing on the computer system, and the PSE task represents a task to be performed once by one of the plurality of processes for each rotation of a periodic schedule. Each of the plurality of processes is capable of performing the PSE task and scheduled to perform the PSE task during the each rotation of the periodic schedule. The method ensures that the PSE task is performed only once by one of a plurality of processes during each rotation of the periodic schedule.

Abstract: A system automatically adaptively modifies a fail-over configuration priority list of back-up devices of a group (cluster) of processing devices to improve availability and reduce risks and costs associated with manual configuration. A system is used by individual processing devices of a group of networked processing devices, for managing operational failure occurrences in devices of the group. The system includes an interface processor for maintaining transition information identifying a second processing device for taking over execution of tasks of a first processing device in response to an operational failure of the first processing device and for updating the transition information in response to a change in transition information occurring in another processing device of the group. An operation detector detects an operational failure of the first processing device.

Abstract: A lock-step synchronism fault-tolerant computer system includes a plurality of computing modules having a processor and a memory in which each computing module processes the same instruction string in synchronization with each other. When disagreement in a state of access to an external bus among the respective processors in each computing module is detected, if no fault is detected in the system including the respective computing modules, an interruption is notified to all of said processors. Synchronization among each computing module is recovered by adjusting timing of a response to an access which each processor executes by an interruption.

Abstract: A plurality of local network groups of computers (102) are coupled together by a network (104). Independent processing systems that execute a single operating system are coupled together by a network (220) to form the local network groups. The independent processing systems may have more than one CPU (202). One or more of the independent processing systems may share power, cooling and a housing, thereby forming a common fault processor group (200). An application is written to execute across multiple independent processing systems and common fault processor groups. That is, the application runs in many instances that each run on independent processing systems. The multiple instances of the application provide some measure of high availability by using N+K sparing or the like. The application is for example, call processing or radio control. A processor notification list (304) keeps track of the independent processing systems that cooperatively provide an application.

Abstract: An information processing apparatus capable of running properly, with automatically executing a backup OS program or a default OS program, from an automatic judgment in a case that a current OS program does not run properly, in which a state flag is disposed in a flash ROM in order to indicate whether or not the current OS program runs properly at the previous time, and a state of the state flag is checked when the current OS program is executed, the current OS program is executed in the case that the current OS program runs properly at the previous time, and the backup OS program is executed in the case that the current OS program does not run properly at the previous time.

Abstract: In a network that includes a first database located on a first client and a second database located on a second client, a user or administrator initiates a restore operation. A dynamic mirror relationship existing between the first and second clients is terminated and a backup version of a database which the user or administrator wishes to recreate is identified. One of the first or second clients receives information concerning the location of the backup version of the database, as well as the role designation of the database at the time the backup operation was performed, from a restore server. The backup version of the database is retrieved from the storage location and recreated on each of the first and second clients, and the dynamic mirror relationship is reestablished between the first and second clients.

Abstract: A method and mechanisms for checkpointing objects, processes and other components of a multithreaded application program, based on the leader-follower strategy of semi-active or passive replication, where it is not possible to stop and checkpoint all of the threads of the object, process or other component simultaneously. Separate checkpoints are generated for the local state of each thread and for the data that are shared between threads and are protected by mutexes. The invention enables different threads to be checkpointed at different times in such a way that the checkpoints restore a consistent state of the threads between the existing replicas and a new or recovering replica, even though the threads operate concurrently and asynchronously. The checkpoint of the shared data is piggybacked onto regular messages along with ordering information that determines the order in which the mutexes are granted to the threads.

Abstract: Techniques and apparatus are disclosed for detecting and responding to the malfunction of a host coupled to a communications bus through a bus transceiver.

Abstract: A received data recovering device that can follow a rapid change in phase of data in data communication, thereby to prevent lowering of the data transmission efficiency, samples a baseband signal in a shift register group of a clock phase detecting circuit using an N-times (N is an integer equal to or greater than 2) frequency relative to the baseband signal, and outputs to a field phase detecting circuit the number of bits required by each of fields per N, the field phase detecting circuit detecting not only a synchronization word, but also error data with respect to fields of a packet header and a Forward Error Correction (FEC) code depending on existence of data and outputting optimum clock phase information to a First In First Out (FIFO).

Abstract: Methods and apparatus to reinitiate failed processors in multiple-processor systems are described herein. In an example method, a failure associated with a first processor of a plurality of processors in a multiple-processor system is detected by a second processor of the plurality of processors. In response to detection of the failure associated with the first processor, the second processor restores the first processor.

Abstract: A network device may be configured with a primary control element and a second control element. Both the primary and secondary control elements may receive information from one or more forwarding elements. Both the primary and secondary control elements may send control information to the forwarding element. The control information from the secondary control element, however, may be discarded either at the forwarding element or at a blocking agent between the secondary control element and the forwarding element. In this manner, the secondary control element may be synchronized with the primary control element in a stateless manner. If a failure condition is detected, control plane operations may be performed using the secondary control element. As a result, the network device may become fault tolerant, and experience reduced amounts of down time due to failure of one or more elements within the network device.

Abstract: A “high availability” system comprises one or more switches under the control of multiple control processors (“CPs”). One of the CPs is deemed to be “active,” while the other CP is kept in a “standby” mode. Each CP generally has the same software load including a fabric state synchronization (“FSS”) facility. The FSSs of each CP communicate with each other. The state information pertaining to an active “image” is continuously provided to a standby copy of the image (“standby image”). The CPs' FSSs perform the function of synchronizing the standby image to the active image. The state information generally includes configuration and operational parameters and other information regarding the active image. By keeping the standby image synchronized to the active image, the standby image can be rapidly transitioned to the active mode if the active image experiences a fault and continue where the previous active image left off.

Abstract: A controller that receives an input of a status of an apparatus, executes predetermined arithmetic and logical operations, and outputs a control signal of the apparatus, and is equipped with a plurality of processors for executing the arithmetic and logical operations; a plurality of data storage elements for storing respective results of the arithmetic and logical operations of the plurality of the processors; a comparator for comparing the results of the arithmetic and logical operations of the plurality of the processors stored in the plurality of the data storage elements; and a comparison record storage element for storing a record of the comparison results of the comparator.

Abstract: An apparatus for and method of enhancing throughput within a cluster lock processing system having a relatively large number of commodity cluster instruction processors which are arranged in redundant fashion to improve reliability. Because the commodity processors have virtually no system viability features such as memory protection, failure recovery, etc., the cluster/lock processors assume the responsibility for providing these functions. The low cost of the commodity cluster instruction processors makes the system almost linearly scalable. The cluster/locking, caching, and mass storage accessing functions are fully integrated into a single hardware platform which performs the role of the cluster/lock master. Upon failure of this hardware platform, a second redundant hardware platform converts from slave to master role. The logic for the failure detection and role swapping is placed within software, which can run as an application under a commonly available operating system.

Abstract: Application software on a fault tolerant system having an active engine and a standby engine is upgraded. As part of the upgrade, the system determines if the active engine and the standby engine are executing different versions of the application software. The system sends a description of work units from the active engine to the standby engine and sends database activities from the active engine to the standby engine.

Abstract: A fault tolerant computer includes a plurality of CPU modules that process the same instruction string while maintaining clock synchronization; and a plurality of I/O modules each having a plurality of device controllers executing input/output control processing for a device. A transaction synchronization controller, which checks if the sequences of I/O transactions issued from the plurality of CPU modules match, is provided in each device controller. If the sequences of I/O transactions issued from the plurality of CPU modules to each device controller match, a judgment is made that an out-of-synchronization condition is not caused.

Abstract: An apparatus for and method of providing failure recovery from redundancy, notwithstanding that the failed subsystem and its replacement have differing capacities. This is especially useful when implementing a cluster lock processing system having a relatively large number of commodity instruction processors which are managed by a highly scalable, cluster lock manager. Reliability is built into the managing communication processor by dividing the system into master and slave subsystems. The master has primary responsibility for system management and coordination, whereas the slave has primary responsibility to backup the master and be prepared to assume management responsibility. Upon the need to transfer responsibility from the master to the slave, whether it be manual (e.g., maintenance) or automatic (e.g., failure), the only concern is that the slave has sufficient capacity to accept the current level of processing, even though it does not have the same level of capacity as the master.

Abstract: One or more master CHN 21AM and one or more back-up CHN 21AC are provided. In each of the one or more back-up CHNs 21AC, the I/O processor 504 is in a power on state, and the NAS processor is in a power off state. The I/O processor 504 accesses a shared memory 25 periodically, and if the fact that a problem has occurred in any master CHN 21AM has been written to the shared memory 25, then the power supply of the NAS processor 506 is turned on, and processing is carried out for switching the back-up CHN 21AC in which the I/O processor 504 is installed, to a master CHN 21 AM.

Abstract: Improved techniques are provided for detecting and correcting errors and skew in inter-cluster communications within computer systems having a plurality of multi-processor clusters. The local nodes of each cluster include a plurality of processors and an interconnection controller. Intra-cluster links are formed between the local nodes, including the interconnection controller, within a cluster. Inter-cluster links are formed between interconnection controllers of different clusters. Intra-cluster packets may be serialized and encapsulated as inter-cluster packets for transmission on inter-cluster links, preferably with link-layer encapsulation. Each inter-cluster packet may include a sequence identifier and error information computed for that packet. Clock data may be embedded in symbols sent on each bit lane of the inter-cluster links. Copies of transmitted inter-cluster packets may be stored until an acknowledgement is received.

Abstract: A plurality of local network groups of computers (102) are coupled together by a network (104). Independent processing systems that execute a single operating system are coupled together by a network (220) to form the local network groups. The independent processing systems may have more than one CPU (202). One or more of the independent processing systems may share power, cooling and a housing, thereby forming a common fault processor group (200). An application is written to execute across multiple independent processing systems and common fault processor groups. That is, the application runs in many instances that each run on independent processing systems. The multiple instances of the application provide some measure of high availability by using N+K sparing or the like. The application is for example, call processing or radio control. A processor notification list (304) keeps track of the independent processing systems that cooperatively provide an application.

Abstract: A receiver for clock and data recovery includes n sampling latches (SL1 . . . SLn) for determining n sample values (SV1 . . . SVn) of a reference signal (Ref2) at n sampling phases (?1a . . . (?na) having sampling latch inputs and sampling latch outputs. The receiver further includes a phase position analyzer (5) connected to the sampling latch outputs for generating an adjusting signal (AS) for adjusting the sampling phase (?1a . . . ?na), if the sample value (SV1 . . . SVn) deviates from a set point and a phase interpolator (9) for generating sampling phases (?1u . . . ?nu). A sampling phase adjusting unit (6) connected with its inputs to the phase position analyzer (5) and the phase interpolator (9) and with its outputs to the sampling latches (SL1 . . . SLn) is provided for generating adjusted sampling phases (?1a . . . ?na) depending on the sampling phases (?1u . . . ?nu) and said adjusting signal (AS).

Abstract: A method and system for associating instrumentation data with a simulation model within a batch simulation farm in which a simulation client communicates with an instrumentation server to process simulation data with respect to the simulation model. In accordance with the method of the present invention, an instrumentation eventlist is delivered from the simulation client to the instrumentation server. The eventlist contains instrumentation event information for the simulation model. Next, within the instrumentation server, a digital signature is computed that uniquely identifies contents of the instrumentation eventlist as being associated with the simulation model. Responsive to receiving simulation data from the simulation client, the digital signature is utilized to associate the simulation data with the simulation model.

Abstract: A journaling method is provided for supporting a recovery when a system is abnormally terminated in a shared disk environment. When a system call operation to take part in a journaling is generated, in order to guarantee a recovery, a transaction is started and new transaction region is assigned. Then, a system is initialized and a transaction type is set up. Lock information on modified data is acquired and added to the transaction so that a transaction manages lock information. A reflection to a disk during a modification of metadata is prevented. Modified metadata added to the transaction and modified information on principal general data are recorded. Then, lock information connected to the transaction is released.

Abstract: In a load testing apparatus, before the load test, three processor elements are combined, without overage or shortage, with a source processor element and a destination processor element as one pair, and the transmission time between the processor elements for each pair is measured. During the load test, packets are sent at a time from the source processor element to the corresponding destination processor element in the same pair, and the transmission time for each pair is measured. The transmission time measured for each pair in the load test is compared with a corresponding expected value data so as to evaluate the performance.

Abstract: A control system, which is capable of performing a fault-tolerant function realized in the manner of duplication by merely transferring memory ownership from one processor module to another with the use of a method of extending a memory bus, is provided. Each processor module in the control system includes an A-port memory and a B-port memory which store memory data of their own processor module (the self processor module) or memory data of the other processor module and a memory bus switch which performs switching-over to selectively store data of the self processor module or data transmitted from the other processor module in the A-port or B-port memory, depending on whether the self processor module or the other processor module has memory ownership.

Abstract: A method and system provides an increased robustness and protection against the occurrence of soft errors in parallel connect functional redundancy checking processors. This is achieved by predicting in advance the likely occurrence of a soft error and its impact on the resulting instruction flow and using already existing circuit implementations to hide the transient error.

Abstract: A plurality of local network groups of computers (102) are coupled together by a network (104). Independent processing systems that execute a single operating system are coupled together by a network (220) to form the local network groups. The independent processing systems may have more than one CPU (202). One or more of the independent processing systems may share power, cooling and a housing, thereby forming a common fault processor group (200). An application is written to execute across multiple independent processing systems and common fault processor groups. That is, the application runs in many instances that each run on independent processing systems. The multiple instances of the application provide some measure of high availability by using N+K sparing or the like. The application is for example, call processing or radio control. A processor notification list (304) keeps track of the independent processing systems that cooperatively provide an application.

Abstract: A plurality of local network groups of computers (102) are coupled together by a network (104). Independent processing systems that execute a single operating system are coupled together by a network (220) to form the local network groups. The independent processing systems may have more than one CPU (202). One or more of the independent processing systems may share power, cooling and a housing, thereby forming a common fault processor group (200). An application is written to execute across multiple independent processing systems and common fault processor groups. That is, the application runs in many instances that each run on independent processing systems. The multiple instances of the application provide some measure of high availability by using N+K sparing or the like. The application is for example, call processing or radio control. A processor notification list (304) keeps track of the independent processing systems that cooperatively provide an application.

Abstract: In a multiprocessor, access to shared resources is provided by a semaphore control mechanism, herein disclosed. The semaphore control mechanism provides for a high degree of programmable firmware reuse requiring relatively few modifications from a uniprocessor. A machine check abort (MCA) handling mechanism is disclosed, which works with the semaphore control mechanism in the multiprocessor to provide improved system availability and reliability. The MCA handling mechanism provides for synchronization of multiple processors and shared resources and for timely execution resumption within the processors that remain on-line.

Abstract: A clock recovery method is disclosed wherein the FIFO delay of data words and the phase difference between a data word and a receiver clock are used to time data transmissions from a transmitter. The phase difference between the data word and the receiver clock is determined by the offset of a word relative to a desired position in a storage buffer. The FIFO delay is determined either by measuring the difference between a read pointer and a write pointer in the FIFO or, alternatively, by calculating the difference between a timestamp of the time a data word entered the FIFO and the current time as the data word is read from the FIFO.

Abstract: A fault tolerant computing system is provided comprising two or more processing sets that operate in synchronism with one another. The two processing sets are joined by a bridge, and there is a communications link for each processing set for transmitting data from the processing set to the bridge. Data transmissions are initiated in synchronism with one another from the respective processing sets to the bridge but are then subject to variable delay over the communications link. Accordingly, a buffer is included in the bridge for storing the data transmissions received from the processing sets for long enough to compensate for the variable delay. The data transmissions can then be fed out from the buffer to a comparator that verifies that the data transmissions received from the two or more processing sets properly match each other. Likewise, a buffer is included in each processing set for storing the data transmissions received from the bridge for long enough to compensate for the variable delay.

Abstract: Disclosed are systems and methods for determining time-outs with respect to a plurality of transactions comprising utilizing a first time-out clock for simultaneously determining time-out states with respect to a first set of transactions of the plurality of transactions, and determining when transactions of the first set of transactions have reached a timed-out state of the time-out states.

Abstract: A method, apparatus and program storage device for maintaining data consistency and cache coherency during communications failures between nodes in a remote mirror pair. A link between a mirror pair of storage systems is monitored. During a link failure between a first storage system and a second storage systems, reads and writes on the first and second storage systems are independently performed and write data and associated timestamps are maintained for the write data for each write in a queue on the first and second storage system. After link reestablishment, volume sets on the first and second storage systems are resynchronized using write data and associated timestamps.

Abstract: In a first microcomputer, a communication function is provided for outputting a data signal having a transmission period Tr that has a relation of Td<Tp/2 with a data time Td, and it sends various data processed by itself and carried on the data signal to a second microcomputer, where the received data signal is sequentially stored in a memory, and the various data are read by timing pulses for reading and processed.

Abstract: An embodiment of the invention is a multiprocessor system for detecting and recovering from errors. The multiprocessor system includes a first processor and a second processor. The first processor detects an error and initiates a recovery process. The first processor and said second processor synchronize at least one recovery action during the recovery process.

Abstract: A method for synchronizing a plurality of processors within a computer system is provided. The computer system includes a plurality of processors that are each communicatively coupled to a respective network wherein each network is independent of each other network. The method includes receiving a plurality of input signals at a first rate from at least one source, transmitting the input signals to a reference object, and transforming the input signal to a known temporal reference. The apparatus is configured to receive a plurality of input signals at a first rate from at least one source, transmit the input signals to a reference object, and transform the input signal to a known temporal reference.

Abstract: In a lock-step synchronism fault-tolerant computer system including a plurality of computing modules having a processor and a memory in which each computing module processes the same instruction string in synchronization with each other. When detecting disagreement in a state of access to an external bus among the respective processors in each computing module, if no fault is detected in the system including each computing module, processing of resuming operation in synchronization is executed with respect to each computing module after generating an interruption to all the processors to execute delay adjustment for making a state of instruction execution among computing modules be coincident.

Abstract: The present invention relates to a programmable safety system intended to be used for safety functions, in which a fault in a control circuit does not lead to a safety function being disabled, which system comprises monitoring functions containing at least two control units, input terminals separately coupled to both control units, whereby each control unit executes its own instruction set and continuously compares a result from the execution with each other. At least one control unit can access the in and output terminal status of a second control unit and/or a number of flags, and the control units are arranged to monitor the result of respectively executed instruction sets and control that the results of the executions are substantially equivalent.

Abstract: The present invention is directed at rebooting a cluster while maintaining cluster operation. Cluster operation is automatically maintained during the reboot since at least one member of the cluster stays active during the process. An administrator triggers the reboot process and then does not have to perform any other steps during the reboot process. An algorithm executes which reboots members of the cluster at different times, while always maintaining operation of at least one member of the cluster.

Abstract: Apparatus and methods for fault-tolerant computing using an asynchronous switching fabric where at least one of a plurality of redundant data processing elements executing substantially identical instructions communicates transactions to at least one target device, such as input/output device, or another data processing element. The transactions are communicated through the asynchronous switching fabric wherein each of the data processing elements and the target device are connected to the asynchronous switching fabric through a respective channel adapter.