Abstract: An industrial process control apparatus and method that includes a number of processors and a number of input/output modules. Each processor is connected to a plurality of the input/output modules by a unidirectional command line. Each input/output module is connected to a plurality of the processors by a unidirectional response line. The processors are arranged to issue an identifier request to all of the connected input/output modules and each input/output module is arranged to respond to the identifier request via the respective response line with a response that includes a unique identifier. Such a configuration allows each processor to identify the physical location of each respective input/output module.

Abstract: An engine control system is provided having a control unit and a monitoring module. The monitoring module, together with the control unit, forms one structural unit and is designed as a detachable module having an independent electromagnetic shielding.

Abstract: Provided are a method, system, and article of manufacture for synchronizing device error information among nodes. A first node performs an action with respect to a first node error counter for a device in communication with the first node and a second node. The first node transmits a message to the second node indicating the device and the action performed with respect to the first node error counter for the device. The second node performs the action indicated in the message with respect to a second node error counter for the device indicated in the message, wherein the second node error counter corresponds to the first node error counter for the device.

Abstract: In a system including multiple-slice processors and memories, a synchronization unit with race avoidance capability includes a delegated write engine that receives data and memory address information from the processors and writes data to the memory as a delegate for the processors.

Abstract: The fault-tolerant or self-correcting computer system is disclosed. The computer system that is provided with various sets of protections against failures that may be caused by space radiation, for example. Improved reliability of the system is achieved by scrubbing of the components on a regular schedule, rather than waiting for an error to be detected. Thus, errors that may go undetected for an extended period are not allowed to propagate and further damage the system. Three or more processors are provided to operate in parallel, and a controller is provided to receive signals from the processors and, using a voting logic, determines a majority signal value. In this manner, the controller can detect an error when a signal from one of the processors differs from the majority signal. The system is also provided with a scrubbing module for resynchronizing the processors after a predetermined milestone has been reached.

Abstract: A multiple redundant computer system includes three primary processor modules (PPM) and three redundant processor modules (RPM) operating synchronously. Primary and redundant processor modules are dissimilar in hardware and software for decreasing the probability of a common cause system failure. Each primary and redundant processor module receives input data from associated primary and redundant input modules respectively, executes control program and transfers output data to an output module. The output module produces a system output as the result of 2-out-of-3 voting among output data generated by PPMs. In response to PPMs hard failures, the output module still produces the system output as the result of 2-out-of-3 voting among output data generated by any combination of the PPM and the RPM. As such, the system is able to operate properly even though five-out-of six processor modules have failed.

Abstract: A method of comparing output information from dissimilar processors includes storing a task in a first memory and storing the task in a second memory at substantially the same time as the first memory. The time of the storing being is controlled by a first arbitration logic and a second arbitration logic. The method also includes receiving the task by a first processor from the first memory and receiving the task by a second processor from the memory at substantially the same time as the first processor. The time being received is controlled by a first arbitration logic and a second arbitration logic. The second processor being dissimilar to the first processor. The method further includes computing a first output by the first processor based on the task and computing a second output by the second processor based on the task. The method still further includes, synchronizing the first and second outputs so that the first and second outputs are output at substantially the same time.

Abstract: A processor includes a first field programmable gate array (FPGA) having a first central processing unit (CPU) core programmed to perform a first function, and first programmable hardware logics (PHLs) programmed to perform a second function. A second FPGA includes a second CPU core programmed to perform a third function, and second PHLs programmed to perform a fourth function. A communication interface is between the first and second CPU cores. The first and second FPGAs are diverse. A portion of the first function communicates first information from the first CPU core to the second CPU core through the interface. A portion of the third function communicates second information from the second CPU core to the first CPU core through the interface, and, otherwise, the first function is substantially the same as the third function. The second function is substantially the same as the fourth function.

Abstract: A failover method for a cluster computer system in which a plurality of computers sharing a resource are connected by a heartbeat path for providing each computer with lines for monitoring operations of the other computers and a reset path. Resetting may be conducted based upon a registered priority for resetting the computers.

Abstract: A variant of Paxos is referred to as Virtually Synchronous Paxos (VS Paxos). VS Paxos is a self-reconfigurable protocol that allows for delay only for reconfiguration decisions, without placing an artificial limit on regular decisions. In an implementation of VS Paxos, subject to any restriction on reconfiguration decisions, a leader may activate an unbounded number of consensus instances ahead. A VS Paxos technique permits unlimited progress during stability periods, in that a leader may initiate commands at any number of consensus instances without bound. VS Paxos waits for command completion only when configuration-changing commands occur.

Abstract: Server apparatuses that configure a data mirror cluster system include databases, shared memories, and memory controllers, respectively. The server apparatuses are connected by interconnects and can directly access communication partner's shared memories via the memory controllers, respectively. One of the server apparatuses operates as an operation server apparatus and the other operates as a standby server apparatus. The memory controller of the operation system updates the database and writes changed data to the shared memory of the standby system. The memory controller of the standby system updates the database of the standby system according to the changed data written to the shared memory of the standby system.

Abstract: A method and system for detecting race conditions computing systems. A parallel computing system includes multiple processor cores is coupled to memory. An application with a code sequence in which parallelism to be exploited is executed on this system. Different processor cores may operate on a given memory line concurrently. Extra bits are associated with the memory data line and are used to indicate changes to corresponding subsections of data in the memory line. A memory controller may perform a comparison between check bits of a memory line to determine if more than one processor core modified the same section of data in a cache line and a race condition has occurred.

Abstract: According to one embodiment, a method comprises, responsive to detection of loss of lockstep (LOL) for a processor module in a system, setting status information stored to the system for the processor module to indicate that the processor module has an error. The method further comprises reestablishing lockstep for the processor module without shutting down the system's operating system, and updating the status information for the processor module to indicate that the processor module no longer has the error. The method further comprises causing the system's operating system to recognize that the processor module having its lockstep reestablished is available for processing.

Abstract: Method and apparatus for sampling a high-speed digital signal include providing a data signal to a differential data input circuit, an offset control signal, and a strobe pulse. In response to the strobe pulse, the data signal is resolved into an output logic state based to a relatively greater extent on the differential data signal and to a relatively lesser extent on the offset control signal.

Abstract: A test apparatus that tests a device under test is provided, including a driver section that supplies a test signal to a corresponding pin of the device under test, a judgment section that makes a judgment concerning pass/fail of the device under test based on the response signal output by the device under test in response to the test signal, a voltage measuring section that detects a DC voltage of the signal output by the driver section, and an output side adjusting section that adjusts a duty ratio of the signal output by the driver section according to the DC voltage detected by the voltage measuring section.

Abstract: Various methods and systems for maintaining a communication protocol connection during a failover are disclosed. One method involves obtaining a first value of a parameter associated with a communication protocol connection between a primary node and a client and sending a flow control message to the client, in response to detecting that the primary node is failed. The flow control message includes the parameter.

Abstract: In a system for operating three address concentrating processors, a common clock signal is transmitted to each of the three address concentrating processors. A common data unit is transmitted simultaneously to each of the three address concentrating processors. A received data unit is received simultaneously from each of the three address concentrating processors. Each of the received data units are compared to each other. An error correcting routine is activated when the data units received from the three address concentrating processors are not all identical.

Abstract: A rapid Byzantine self-stabilizing clock synchronization protocol that self-stabilizes from any state, tolerates bursts of transient failures, and deterministically converges within a linear convergence time with respect to the self-stabilization period. Upon self-stabilization, all good clocks proceed synchronously. The Byzantine self-stabilizing clock synchronization protocol does not rely on any assumptions about the initial state of the clocks. Furthermore, there is neither a central clock nor an externally generated pulse system. The protocol converges deterministically, is scalable, and self-stabilizes in a short amount of time. The convergence time is linear with respect to the self-stabilization period.

Abstract: A method for synchronizing a transmission of information over a bus, and a device having synchronization capabilities.

Abstract: A method for optimizing the use of digital computing resources to achieve reliability and availability of the computing resources is disclosed. The method comprises providing one or more processors with a recovery mechanism, the one or more processors executing one or more applications. A determination is made whether the one or more processors needs to be reconfigured. A rapid recovery is employed to reconfigure the one or more processors when needed. A computing system that provides reconfigurable and recoverable computing resources is also disclosed. The system comprises one or more processors with a recovery mechanism, with the one or more processors configured to execute a first application, and an additional processor configured to execute a second application different than the first application. The additional processor is reconfigurable with rapid recovery such that the additional processor can execute the first application when one of the one more processors fails.

Abstract: Methods and systems are provided for recursively backing up modified data files where only modified data files are backed up and that provide a user with an efficient way to determine which original files have been modified to allow the user to readily locate original files if the user is not satisfied with any modifications to the original files. A mirror memory structure is created, but only modified files are saved to the mirror memory structure and modified files bear the same names as original files to assist in easily locating original files.

Abstract: Disclosed are “black-box leases” that protect information consistency and that allow for information sharing in a distributed file system while hiding from a client information about other clients' use of the file system. This information hiding also allows greater concurrency because changes to the file system are permitted as long as they do not affect the leases as observed by the clients. For each data field protected by a black-box lease, a client has a two-value data structure: SelfValue represents the client's intended use of the data field, and OtherValue is an aggregation of the other clients' intended uses of that data field. Knowing only this aggregate OtherValue, but without knowing any specifics of the other clients' usage patterns, the client knows how it may use the data field without adversely affecting the consistency of data in the distributed file system.

Abstract: A technique protects shared data in a local device having local memory. The technique involves observing a page table entry (PTE) on the local device. The PTE is stored in a page table used for managing virtual to physical address translations, tracking page modifications and handling page faults between semiconductor memory and magnetic disk drive memory on the local device. The technique further involves leaving a mirroring routine inactive on the local device when the PTE indicates that shared data corresponding to the PTE has not been modified on the local device. The mirroring routine is configured to copy the shared data from the local memory to a remote device. The technique further involves activating the mirroring routine to mirror the shared data from the local memory to the remote device when the PTE indicates that shared data corresponding to the PTE has been modified on the local device.

Abstract: Apparatus and methods for controlling a system that operates responsive to a plurality of input control signals are disclosed. During operation the system generates a plurality of output status/control signals. A master controller has at least first and second controllers. The first controller outputs and inputs signals over a first communication path, and the second controller outputs and inputs signals over a second communication path. The first and second controllers output signals based on input signals received over the first and second communication paths, respectively, and also based on stored control data. A plurality of input/output modules are provided. Each of the input/output modules has first and second slave controllers. The first slave controller of each of the input/output modules inputs and outputs signals over the first communication path to the first controller, and the second slave controller outputs and inputs signals over the second communication path.

Abstract: A redundancy system that can perform synchronization even if a failure occurs to an application. According to the redundancy system of the present invention, a synchronization data memory area, a management bit map table having a flag created for each segment of the synchronization data memory area, and a management memory area for storing the starting address of the segment are set in each device. In the service application process, a service is performed using one or more segments, a flag corresponding to the segment is set, and synchronization information is written to the management memory each time the segment is written or overwritten. In the read process, each flag in the management bit map table is checked, and if a flag being set exists, the synchronization data is read from the segment corresponding to the synchronization information stored in the management memory, and the flag is reset.

Abstract: Replacing a failing physical processor in a computer supporting multiple logical partitions, where the logical partitions include dedicated partitions and shared processor partitions, the dedicated partitions are supported by virtual processors having assigned physical processors, and the shared processor partitions are supported by pools of virtual processors. The pools of virtual processors have assigned physical processors.

Abstract: According to some embodiments, a multithreaded microcontroller includes a thread control unit comprising thread control hardware (logic) configured to perform a number of multithreading system calls essentially in real time, e.g. in one or a few clock cycles. System calls can include mutex lock, wait condition, and signal instructions. The thread controller includes a number of thread state, mutex, and condition variable registers used for executing the multithreading system calls. Threads can transition between several states including free, run, ready and wait. The wait state includes interrupt, condition, mutex, I-cache, and memory substates. A thread state transition controller controls thread states, while a thread instructions execution unit executes multithreading system calls and manages thread priorities to avoid priority inversion. A thread scheduler schedules threads according to their priorities.

Abstract: A feedback control device capable of continuously performing high-accuracy, stable control even in cases where any of multiple controllers for controlling a controlled system becomes incapable of control action. A controller (master controller) generates control data for stably controlling a heater by feedback control, controls the heater in accordance with the control data, and sends the control data to the other controller (slave controller). The slave controller receives the control data from the master controller but does not control the heater while the master controller is operating normally. If the master controller develops anomaly and becomes incapable of normal control action, the slave controller initiates feedback control of the heater in accordance with the control data received from the master controller immediately before the anomaly occurred, and controls the heater thereafter in accordance with control data generated thereby.

Abstract: A system, method, and computer program product for reporting and recovering from an internal processor error in a multiprocessor system supporting system management mode. In accordance with the method of the present invention one or more replacement agents are allocated such as during system startup within the multiprocessor system. Machine specific error-reporting registers are monitored for one or more active processor agents during system operation. In response to detecting a faulty agent via the monitoring, a system management interrupt (SMI) request is issued to one or both the faulty agent and a selected replacement agent. In response to receiving the SMI request, the operating state of the faulty agent is copied to the selected replacement agent in system management mode. Operating system processing is then resumed using the replacement agent.

Abstract: A high reliability system in which a plurality of apparatuses each having a variable function unit and a fixed function unit are mutually connected through an internal network. Pairs of apparatuses are constructed and spare apparatuses are allocated, thereby providing redundancy. Each apparatus has a service processing unit which executes the software for providing a peculiar service to every apparatus pair, a synchronization processing unit which synchronizes the services between the apparatus pair, a fault detecting unit which detects a fault of the pair partner apparatus, and a fault processing unit which, issues a pair request to the network and reconstructs an apparatus pair together with the apparatus to which the pair application has been made. The redundancy recovery after the exchange of the failed apparatus is executed automatically, thereby shortening a time in a non-redundant state.

Abstract: The disclosed invention relates to a re-synchronization system that operates in a switching arrangement receiving a plurality of incoming data packets. The switching arrangement is made of an active switch card that transmits the incoming data packets and a backup switch card that may be re-activated by an operator after replacement. The re-synchronization system is implemented in each switch card. When the backup switch card is re-activated, both switch cards receive the incoming data packets and the system of the invention allows to re-synchronized both switch cards by controlling the transmission of the incoming data packets out of each switch card until the same data packets are transmitted. The re-synchronization system further comprise storage for storing the incoming data packets and detector for detecting a re-synchronization information among the incoming data packets.

Abstract: Aligning execution point of duplicate copies of a user program by exchanging information about instructions executed. At least some of the exemplary embodiments may be a method of operating duplicate copies of a user program in a first and second processor, allowing at least one of the user programs to execute until retired instruction counter values in each processor are substantially the same, and then executing a number of instructions of each user program. Of the instructions executed, at least some of the instructions are decoded and the inputs of each decoded instruction determined (the decoding substantially simultaneously with executing in each processor).

Abstract: Embodiments of apparatuses and methods for reducing the uncorrectable error rate in a lockstepped dual-modular redundancy system are disclosed. In one embodiment, an apparatus includes two processor cores, a micro-checker, a global checker, and fault logic. The micro-checker is to detect whether a value from a structure in one core matches a value from the corresponding structure in the other core. The global checker is to detect lockstep failures between the two cores. The fault logic is to cause the two cores to be resynchronized if there is a lockstep error but the micro-checker has detected a mismatch.

Abstract: A system and method is disclosed for providing a robust ultra low power serial interface with a digital clock and data recovery circuit for power management systems. In one advantageous embodiment a digital clock and data recovery circuit of the invention comprises a quadruple phase clock generator circuit that generates four shifted clock signals, a decision logic circuit, a state detector circuit, and an edge detector circuit. The detected edges of data signals are used to latch the state of the four shifted clock signals. The state detector circuit selects a stable clock signal among the four shifted clock signals for use as a recovered clock signal and synchronizes the recovered clock signal at a center of the data signal. The selected recovered clock signal remains available until another data signal transition is detected.

Abstract: A method and system of determining the execution point of programs executed in lock step. At least some of the illustrative embodiments are computer systems comprising a first processor that executes a program, and a second processor that executes a duplicate copy of the program in lock step with the first processor. After receipt of a duplicate copy of an interrupt request by each processor, the first processor determines the execution point in its program relative to the execution point of the duplicate copy of the program executed by the second processor.

Abstract: A secure system has two computers that are intrinsically safe and implements a method for verifying the redundancy for the outputs where a very high level of safety is required. The method makes it possible to handle inconsistencies in the outputs of the two computers when they are working in redundant mode. Each computer receives the output states determined by the other computer and compares them to states calculated. A state of divergent operation is detected if the computers have determined two different states for a single output. If a divergence is detected for at least one output, the state of that output is determined by preventing any transition from a restrictive state to a permissive state.

Abstract: A tape library comprises: a plurality of tape media; a plurality of slots in which the plurality of tape media are respectively stored; a drive in which a tape medium extracted from any of the plurality of slots is set and which performs tape reading or writing in respect of this tape medium; and a controller by which a tape medium is extracted from a designated slot of these plurality of slots and set in the drive. The host computer comprises: a plurality of virtual computers; a first storage region in which is stored slot allocation information expressing which slot is allocated to which virtual computer; and an access control unit that specifies the slot allocated to a first virtual computer, of the plurality of the virtual computers, from the slot allocation information, and restricts access from the first virtual computer to the tape medium in the specified slot.

Abstract: Systems and methods for backing up and/or restoring data. When a backup operation is initiated, systems and methods are provided for creating a single snapshot of the backup items, including backup groupings. The single snapshot is used by a backup/recovery application to perform a save process on each backup grouping. By using the same snapshot, the backup is performed based on the same point in time so that the backed up data across the client system is consistent and synchronized. When a recovery operation is initiated, recovery items (e.g., backup groupings, writers and writer components) are selected from backup groupings of the client.

Abstract: The yield of a semiconductor device is improved which has a large-scale logic circuit or which has both a logic circuit and a memory. A basic circuit block is provided with an input/output circuit. A transmission line and a branch line connect the input/output circuits so that information can be exchanged through the input/output circuits between one basic circuit block and another basic circuit block. The memory in each basic circuit block or in each input/output circuit can be programmed from the outside to designate the destination of a signal. By thus changing the program in the memory, the transmission destination of a signal can be changed to give various functions efficiently with a limited circuit scale. Moreover, if a basic circuit block fails another basic circuit block substitutes for it to improve the yield drastically.

Abstract: A fault-tolerant computer has duplex systems each comprising a CPU subsystem for controlling access to a CPU and a storage unit, and an IO subsystem for controlling data which are input to the IO subsystem from an external circuit and output from the IO subsystem to the external circuit. Data with a transmission time assigned thereto is transmitted from one of the IO subsystems to the other IO subsystem, and is received asynchronously by the other IO subsystem. The other IO subsystem records a reception time of the data, and calculates an ideal reception time using the transmission time assigned to the data. A clock shift in the other IO subsystem with respect to the one IO subsystem is calculated from the calculated ideal reception time and the recorded reception time. Thereafter, the counter in the other IO subsystem is changed based on the calculated clock shift, and data is received using the changed counter.

Abstract: Disclosed is system and method for mirroring data from a primary data storage system on a mirroring data storage system. According to some embodiments to the present invention, prior to resynchronization of a data unit on the mirroring system with corresponding data on a primary unit, a consistent snap-shot of the data unit to be resynchronized is taken. According to some embodiments of the present invention, the snap-shop may be discarded upon completion of resynchronization.

Abstract: A method and computer program for reducing the restart time for a parallel application are disclosed. The parallel application includes a plurality of parallel operators. The method includes repeating the following: setting a time interval to a next checkpoint; waiting until the time interval expires; sending checkpoint requests to each of the plurality of parallel operators; and receiving and processing messages from one or more of the plurality of parallel operators. The method also includes receiving a checkpoint. request message on a control data stream, waiting to enter a state suitable for checkpointing, and sending a response message on the control data stream.

Abstract: An arbitration mechanism is provided for arbitrating between redundant controllers having outputs electrically connected together and provided as input to at least one device under control. The arbitration mechanism includes logic for automatically determining which controller of the redundant controllers is active controller, and a hardware output interlock for the redundant controllers to ensure that output controlled by only the active controller is enabled as input to the at least one device. The arbitration mechanism also includes logic for monitoring the active controller for failure, and upon detection of failure, for automatically switching active control to another controller of the redundant controllers transparent to the at least one device.

Abstract: A device and method for switching over in a computer system having at least two execution units are provided, in which switchover units are included which are designed in such a way that they switch between at least two operating modes, a first operating mode corresponding to a comparison mode and a second operating mode corresponding to a performance mode. A programmable interrupt controller is assigned to each execution unit, and a storage element is included, in which information is stored that describes at least parts of a configuration of at least one of these interrupt controllers.

Abstract: Performing data management operations on replicated data in a computer network. Log entries are generated for data management operations of an application executing on a source system. Consistency point entries are used to indicate a time of a known good, or recoverable, state of the application. A destination system is configured to process a copy of the log and consistency point entries to replicate data in a replication volume, the replicated data being a copy of the application data on the source system. When the replicated data represents a known good state of the application, as determined by the consistency point entries, the destination system(s) may perform a storage operation (e.g., snapshot, backup) to copy the replicated data and to logically associate the copied data with a time information (e.g., time stamp) indicative of the source system time when the application was in the known good state.

Abstract: A method of establishing and maintaining a consistent configuration state of a first processor, running on a first version of operating software, and a second processor, running on a second version of operating software, is described. The method involves determining a current configuration state of the first processor, where the configuration state comprises a list of configuration commands. The method also involves performing a syntax check for each command in the current configuration, using the second processor and the second version of operating software, with the syntax check resulting in a pass or a fail result. For every command which results in a fail result, an entry is added to a mismatched configuration list (MCL). Embodiments of this invention can be utilized to keep the configurations consistent during an upgrade or downgrade of the operating software.

Abstract: A process control system is provided having a plurality of I/O devices in communication using a bus. A primary redundant I/O device and a secondary redundant I/O device are coupled to the bus, where the secondary redundant I/O device is programmed to detect a primary redundant I/O device fault. The secondary redundant I/O device, upon detecting the primary redundant I/O device fault, publishes a primary redundant I/O device fault message on the bus. The controller may deactivate the primary redundant I/O device and activate the secondary redundant I/O device responsive to the primary redundant I/O device fault message.

Abstract: In an arbitration circuit in which a shared circuit such as a memory is used exclusively by one of a plurality of functional blocks at a time, an access reservation request is issued from one of the functional blocks, and the access request associated with the access reservation request is reserved. Thereafter, when an access request is issued from another functional block, it is determined which one of the access reservation request and the access request from these functional blocks takes precedence. For example, if the access request from the latter functional block has a low priority level, the access reservation request is selected and the circuit waits for an access request from the functional block which has issued this access reservation request. In this manner, it is possible to avoid cancellation of a once-accepted access request and waiting for a high-priority access request.

Abstract: A method, apparatus, and computer program product are disclosed for testing a data processing system's ability to recover from cache directory errors. A directory entry is stored into a cache directory. The directory entry includes an address tag and directory parity that is associated with that address tag. A cache entry is stored into a cache that is accessed using the cache directory. The cache entry includes information and cache parity that is associated with that information. The directory parity is altered to imply bad parity. The bad parity implies that the address tag that is associated with this parity is invalid. The information included in the cache entry is altered to be incorrect information. However, although the information is now incorrect, the cache parity continues to imply good parity which implies that the data is good. This good parity implies that the information that is associated with the parity is valid, even though it is not.

Abstract: Embodiments include a timeout event management system that registers timeout events and checks for and corrects inaccuracies in timing caused by hibernation or system time changes. The timeout event management system may trigger an event after an intended delay time or at an intended expiration time. A handler program may be called in response to the triggered timeout. In an additional embodiment, the timeout system may track timeout events in a priority queue data structure.