Of Power Supply Patents (Class 714/14)
  • Patent number: 6731561
    Abstract: A semiconductor memory includes a group of memory cells arrayed in a matrix, memory cell electric power source lines configured to connect the respective memory cells arrayed in a direction of rows of the group of memory cells of each of the rows, two electric power source terminals configured to be mutually independent, and switches configured to be connected between the memory cell electric power source lines and the two electric power source terminals respectively, to be controlled to turn ON/OFF by a inversion logic operation based on a test mode switching signal for switching to and from a test mode and a normal operation mode, and to connect the memory cell power source line to either of the two electric power source terminals according to the ON/OFF control.
    Type: Grant
    Filed: March 15, 2002
    Date of Patent: May 4, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mitsuhiro Abe, Kenta Kaneeda, Hiroo Ota, Hideo Niki
  • Patent number: 6731738
    Abstract: A communication hub for providing call tones in a communication network proximate the calling device. The communication hub comprises an interface coupled to a processor and a tone generator. The tone generator is configured to generate call tones. The processor is configured to process an in-band call tone request message to direct the tone generator to provide the call tones to a call device. The interface is configured to receive the call tone request message and provide the call tones to the call device.
    Type: Grant
    Filed: March 28, 2000
    Date of Patent: May 4, 2004
    Assignee: Sprint Communications Company, L.P.
    Inventors: Chaoxin Charles Qiu, Shannon P. Silvus, Richard N. Kennedy, Michael J. Gettles, William Douskalis
  • Patent number: 6728668
    Abstract: A method and apparatus for simulated error injection for processor deconfiguration design verification is provided. A simulated error condition request is received from a user through software, such as the operating system executing in the multiprocessor data processing system. In response to the requested simulated error condition, an error condition is injected into a processor of the multiprocessor data processing system via instruction execution. In response to the detection of the error condition and execution of error-path code, a processor is deconfigured. The error condition may be injected by executing an instruction to set an error condition bit in an error condition register.
    Type: Grant
    Filed: November 4, 1999
    Date of Patent: April 27, 2004
    Assignee: International Business Machines Corporation
    Inventors: Alongkron Kitamorn, Charles Andrew McLaughlin, Camvan Thi Nguyen, Jayeshkumar M. Patel
  • Publication number: 20040078655
    Abstract: A built-in type power integrated controller which stably supplies electrical power to a computer system and protects the system from various power failures which may occur in a power supply and a method therefor are provided. The power integrated controller includes a power generator that drops DC voltage generated by a first rectifier in the event of a normal power supply and by a battery in the event of a power outage to DC voltage levels that are supplied to each component of the system and inverts the DC power to AC power. Thus, the size of an inverter decreases so that it is easier to incorporate the inverter into the system. The built-in battery is employed to automatically shut down and boot the system in a case where there is a power failure while a user is away from the system. Furthermore, a power failure status is sent to a system manager and a user working at a remote location through a wired or wireless network thereby enabling them to appropriately cope with the power failure.
    Type: Application
    Filed: May 28, 2003
    Publication date: April 22, 2004
    Inventor: Si-Wook Sung
  • Patent number: 6711701
    Abstract: A synchronous flash memory includes an array of non-volatile memory cells, and has a package configuration that is compatible with an SDRAM. The memory device includes a memory array, a programmable register circuitry to store protection data, and a voltage detector to determine if a memory power supply voltage drops below a predetermined level. Control circuitry is provided to program the register circuitry and prevent erase or write operations to the memory array in response to the voltage detector. In operation, the memory monitors a power supply voltage coupled to the memory, and prohibits write or erase operations from being performed if the supply voltage drops below a predetermined value.
    Type: Grant
    Filed: August 25, 2000
    Date of Patent: March 23, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Frankie F. Roohparvar, Ebrahim Abedifard
  • Publication number: 20040039960
    Abstract: An automatic hibernation approach to recover the status and the data of the all applications running on a computer is employed after a power failure. There is a unit which monitors the power supply and detects the power failure. When a power failure occurs, the supply of power is temporarily transferred to a battery and the operating system is informed that a power failure has happened. The operating system runs a software to store the status of the drivers, the status of the operating system, and the memory. The start sequence is switched to a special start sequence and the source of power is returned to the power supply before a shutdown takes place. When the power comes back, the special start sequence restores the memory and the status of the operating system and the drivers. Finally, every operation is back to normal.
    Type: Application
    Filed: August 23, 2002
    Publication date: February 26, 2004
    Inventor: Reza Kassayan
  • Patent number: 6691248
    Abstract: An apparatus controls supply of power to an electronic device coupled thereto via one or a plurality of uninterrupted power supply units each receiving power from a corresponding external power source or including a battery unit. Each of the uninterrupted power supply units outputs power failure information when no power is received from the corresponding power source. The apparatus includes a first controller which controls input of power from the one or plurality of uninterrupted power supply units to the electronic device, and a second controller which controls the first controller in response to the power failure information received from at least one of the uninterrupted power supply units.
    Type: Grant
    Filed: August 29, 2000
    Date of Patent: February 10, 2004
    Assignee: Fujitsu Limited
    Inventors: Kazuo Nishijima, Noboru Nishimura
  • Patent number: 6684339
    Abstract: For use in a system comprising a plurality of devices that are connected together in a network, there is disclosed a system and method of transferring information from a first device in the network to a second device in the network when the first device is operating in a reduced power mode. The first device comprises a second power supply for supplying power to the first device when a first power supply fails. The first device also comprises a controller for transferring information from the first device to a second device in the network when the first device is receiving power from the second power supply. The second device in the network receives power from its own first power supply. The second device receives information that has been transferred from the first device in the network.
    Type: Grant
    Filed: September 26, 2000
    Date of Patent: January 27, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Randy C. Willig
  • Patent number: 6658597
    Abstract: A combined hardware/firmware device and method for automatic recovery of an integrated circuit avoids a disruptive power-on reset after occurrence of an electrostatic discharge which may occur during normal operations or during electromagnetic compatibility testing. The device is incorporated into the chip of the IC and includes an electromagnetic discharge sensor, a flag, and firmware to execute the recovery and reset procedures. The sensor is located between the VDD and VSS lines of the IC which itself includes one or both of a microprocessor and a microcontroller. In a power-on reset sequence, the sensor output and the flag are both set to logic 0. After an electrical transient voltage occurs, the sensor output is set to logic 1. The logic 1 output of the sensor sets the flag, which may be a D flip-flop, to a value of logic 1.
    Type: Grant
    Filed: October 22, 1999
    Date of Patent: December 2, 2003
    Assignee: Industrial Technology Research Institute
    Inventors: Ming-Dou Ker, Yu-Yu Sung
  • Patent number: 6646981
    Abstract: A transmission apparatus comprises a power-supply unit, a first detection unit for detecting a power-supply recovery of the power-supply unit, a request unit which is used for transmitting a demanding command to an adjacent transmission apparatus completing line setting based on line-setting information to request the adjacent apparatus to transmit alarm information when the first detection unit detects a power-supply recovery, wherein the alarm information includes disabled-reception and recovered-reception times, that is, times at which reception of a signal from the transmission apparatus is disabled and recovered respectively, a first reception unit for receiving the alarm information from the adjacent transmission apparatus and a second detection unit for detecting a period of time with a transmission line affected between a disabled-reception time and a recovered-reception time of the adjacent transmission apparatus included in the alarm information received by the first reception unit.
    Type: Grant
    Filed: July 27, 1999
    Date of Patent: November 11, 2003
    Assignee: Fujitsu Limited
    Inventors: Kenya Kinouchi, Takeshi Ono
  • Patent number: 6643209
    Abstract: A structure including volatile memory devices that are used by the host computer system as the storage media. The volatile memory devices include volatile memory device back up systems to provide power to both the volatile memory and non-volatile memory in the event of power failure. The volatile memory devices also connect directly to an expansion bus of the host computer system, such as a PCI bus. Therefore, the volatile memory devices of the invention include a high-speed path to the host computer system and the volatile memory devices of the invention are faster than prior art devices, use less power and are lower cost.
    Type: Grant
    Filed: August 8, 2002
    Date of Patent: November 4, 2003
    Assignee: Genatek, Inc.
    Inventor: Jason R. Caulkins
  • Publication number: 20030204776
    Abstract: A system including a processor is energized from a source which is subject to power failure. To allow the state of the system to be restored after the power failure, at least portions of the volatile data of the processor are stored in non-volatile electrically erasable programmable read-only memory (Eeprom). In order to effectuate the data transfer, storage capacitors must provide power to the Eeprom and to the processor. In order to minimize the amount of storage capacitance, the processor power is maintained only until the data to be stored is transferred to the buffer of the Eeprom. Eeprom power is maintained until after a later time at which the buffer transfers the data to non-volatile storage of the Eeprom.
    Type: Application
    Filed: January 9, 2003
    Publication date: October 30, 2003
    Inventor: William John Testin
  • Publication number: 20030204777
    Abstract: An electronics-based system (100) for power conversion and load management provides control sequencing and prognostic health monitoring and diagnostics for fault tolerant operation of the system. The system (100) includes a prognostic health monitoring and diagnostic unit (30) for identifying present out-of-range conditions, overload conditions, and trending violations, for components of the system and a decision making unit (20), which controls transitions between a plurality of operating modes to ensure fail-safe operation without unnecessary tripping, cold-starts or system resets upon the occurrence of certain fault conditions.
    Type: Application
    Filed: April 14, 2003
    Publication date: October 30, 2003
    Inventor: Hassan A. Kojori
  • Publication number: 20030200481
    Abstract: A method by which the presentation of superfluous media content requiring system activity is reduced or suspended in consideration of system power. For one embodiment, a user processing system indicates its power mode to a power mode/level determination applet embedded on a Web page. Action items within the web page respond to DC powered systems by limiting speed and/or the duration of animation for animated objects within the Web page. Additionally, or alternatively, the limitation or suspension of animation may be in response to power level. For one embodiment the superfluous media content is reduced or suspended after some period regardless of system power considerations.
    Type: Application
    Filed: April 18, 2002
    Publication date: October 23, 2003
    Inventor: Randy P. Stanley
  • Patent number: 6633998
    Abstract: A multiple communications port unit for coupling plural peripheral devices to a computer. The multiple communications port unit includes a network port for being coupled to a supervisory computer, communications ports for being coupled to the peripheral devices, and a power supply unit suitable for using the substation battery at an electric distribution substation for input power. The power supply unit includes redundant power supplies, an input conditioning circuit, and a sensing and annunciation circuit for providing a warning of a power supply malfunction.
    Type: Grant
    Filed: December 13, 1999
    Date of Patent: October 14, 2003
    Assignee: General Electric Company
    Inventor: Pui Lun Lau
  • Patent number: 6629045
    Abstract: A system and method for detecting a malfunction of a slave power supply and triggering an interlock signal in response to the detection of the malfunction. The method for activating an interlock signal on detecting a malfunction of a slave power supply, includes receiving first and second inputs. In one embodiment, the first input received represents status of a set point, and the second input represents output power. On receiving the inputs the method determines that the slave power supply system has malfunctioned when the received inputs substantially mismatch. In response to the determination of the malfunction, an interlock signal is activated. In one embodiment, the system to implement the method includes a processing unit, memory coupled to the processing unit and a program included in the memory, where the program is executable to implement the method.
    Type: Grant
    Filed: March 19, 2001
    Date of Patent: September 30, 2003
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chang-Hui Chao, Wen-Huang Chiang, Hong-Yi Chang
  • Patent number: 6618821
    Abstract: A fault tolerant network server is described. This server has a pair of processing units, each processing unit has at least one CPU, system memory, an interface for a RAID system, at least one disk drive, a network interface, a cluster network interface, a power supply, and a case. The cases of both processing units are slideably mounted in a rack-mountable server case. The server also has a RAID system mounted in the server case and powered by two, redundant, power supplies and coupled to the processing units through isolators for blocking transactions when a processing unit has insufficient power or is being serviced.
    Type: Grant
    Filed: January 12, 2000
    Date of Patent: September 9, 2003
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: James R. Duncan, Edgar Hance, David A. McAfee, Gerald J. Merits, Mike L. Pelonero, Patrick A. Raymond, Everett R. Salinas
  • Patent number: 6614708
    Abstract: A non-volatile memory device with a built-in laser indicator. The non-volatile memory device includes a connective port, a buffer, a non-volatile memory unit, a memory controller, a battery and a laser indicator. The connective port connects electrically to a host machine. The host machine transfers data and provides power to the connective port through an external bus. The buffer holds the data transmitted to the connective port temporarily. The memory controller controls the transfer of data from the buffer into the non-volatile memory unit. The battery receives host power and stores up some host power to serve as backup power. The battery also provides the power for driving the laser indicator.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: September 2, 2003
    Assignee: Ritek Corporation
    Inventors: Yu-Chuan Lin, Chun-Chieh Chen, Hung-Ju Shen, Tao-Chien Wei, Chien-Hua Wu, Sheng-Lin Chiu, Huan-Tung Wang, Hsin-Chih Hung
  • Publication number: 20030163744
    Abstract: An information processing system capable of dynamic CPU replacement regardless of the function of OS, and a method and a program for controlling the same. The information processing system comprises an information processor and a service processor. The service processor instructs MMCs of all cell boards in a partition that includes a cell board to be removed and an MMC of a replacement cell board to be incorporated to copy data from a memory of the cell board to be removed to a memory of the replacement cell board. Besides, when receiving a write instruction during the copying operation, the MMCs write the same data written to the cell board subject to replacement also to the memory of the replacement cell board. After the copying operation has been finished, the operations of CPUs in the partition are forcefully suspended. Subsequently, the service processor instructs BIOS to copy inside information of the CPU in the cell board subject to replacement into the CPU in the replacement cell board.
    Type: Application
    Filed: February 25, 2003
    Publication date: August 28, 2003
    Applicant: NEC CORPORATION
    Inventor: Shigeo Yamazaki
  • Patent number: 6598107
    Abstract: The present invention relates to a method of communicating data between at least two units (1) on a serial bus (2) in a car, wherein the units 11) have independent clocks, the data being transmitted as a sequence (3) of frames (4), each frame including an identifier field (9) and a data field (10). In order to ensure an always reliable and synchronized communication of data on a serial bus with different types of units (clocks) where randomly distributed periods of idle time may occur on the bus it is suggested that prior to any sequence (3) of frames (4), a signal pattern (7) is transmitted on the bus (2), so as to set the bus to a definite state for a predetermined period of time.
    Type: Grant
    Filed: May 4, 2000
    Date of Patent: July 22, 2003
    Assignees: Motorola, Inc., Volcano Communications Technologies, AB
    Inventors: Hans Christian von der Wense, István Horváth, Antal Rajnák
  • Patent number: 6591374
    Abstract: In a data processing system that includes redundant elements, a method for protecting system components from transients that arise on a system interconnect during switching events. The system components operate in a normal mode of operation prior to detection of the impending occurrence of a switching event wherein a first redundant element replaces a failed element. Upon detecting the impending occurrence of a switching event, an indication that the switching event is to occur is conveyed to the system components. The system components respond by entering a standby mode of operation wherein system components isolate their circuitry from the system interconnect during the switching event. The system components returning to the normal mode of operation in response to a triggering event.
    Type: Grant
    Filed: December 22, 1995
    Date of Patent: July 8, 2003
    Assignee: Cisco Technology, Inc.
    Inventors: Dirk R. Christensen, Matthew Castrigno
  • Publication number: 20030101373
    Abstract: System (100) and method for providing power supply status indications and network-originated messages on a user device interface (104) of a user device (102) coupled to an access device (110). The access device (110) receives a supply of main power from a main power supply (204), and the access device (110) is adapted to interface with a communications network (111). A backup power supply (206) is coupled to the access device (110) and is adapted to supply backup power to the access device (110) when the supply of main power (214) fails. The backup power supply (206) provides a signal indicating a power condition of the backup power supply (206) when the supply of main power (214) fails. A processor unit (208) receives the signal and generates a backup power supply status indication in response to the signal. At least one user device (102) is coupled to the access device (110) and also is adapted to receive and/or transmit information over the communications network (111) via the access unit (110).
    Type: Application
    Filed: November 27, 2001
    Publication date: May 29, 2003
    Inventors: Phillip Kent Freyman, Roger William Ady
  • Patent number: 6550017
    Abstract: A system and method for monitoring a distributed fault tolerant computer system. A hardware counter mechanism (e.g. a countdown counter) is reset repeatedly by a software reset mechanism during normal operation, thereby preventing the counter mechanism from reaching a count indicative of the existence of a fault. A unit provides a signal to a bus indicative of the status (ON or OFF) of the unit. A management subsystem defines a configuration for the distributed fault tolerant computer system. The management subsystem is responsive to status signals on the bus and selectively reconfigures a stored representation in response to changing status signals on the bus.
    Type: Grant
    Filed: June 29, 1999
    Date of Patent: April 15, 2003
    Assignee: Sun Microsystems, Inc.
    Inventors: Hossein Moiin, Peter Martin Grant Dickinson
  • Patent number: 6549977
    Abstract: A disk array controller reliably improves performance in RAID configurations without the need for a battery backup. Write completion interrupts are queued until a write cache flush has been performed and are then sent to a host system. States of ranges of disk addresses (activity bins) are stored in nonvolatile storage elements associated with the ranges. The states allow rebuild times to be reduced after power failures and drive failures. A range is in a Changing state if at least one of the addresses is the target of a write operation that has been initiated but not completed. The range is in a Stable state if no addresses are the target of an uncompleted write operation. Two additional states are used to identify ranges of disk addresses that have been zeroed or never been written to. The additional states allow substantial reductions in RAID volume creation times.
    Type: Grant
    Filed: May 23, 2001
    Date of Patent: April 15, 2003
    Assignee: 3ware, Inc.
    Inventors: Robert W. Horst, Christophe Therene
  • Publication number: 20030061536
    Abstract: A method for controlling power for a semiconductor storage device and the semiconductor storage device are provided which enable power consumption to be greatly reduced in a standby state. The power control method uses an ultra-low power consumption mode in which power control can be exerted in the standby state. In the ultra-low power consumption mode, a burst self-refresh state, power-OFF state, and power-ON state are provided. In the burst self-refresh state, memory cells are refreshed in a centralized manner. In the power-OFF state, an internal power source circuit can be partially turned OFF. In the power-ON state, internal power sources having been partially turned OFF are turned ON. Therefore, it is possible to greatly reduce power consumption in the standby state.
    Type: Application
    Filed: August 27, 2002
    Publication date: March 27, 2003
    Inventors: Kiyoshi Nakai, Yutaka Ito, Takeshi Hashimoto, Hideaki Kato
  • Patent number: 6535996
    Abstract: A method and system for protecting user data during power failures on a network-computer-class data processing system is provided. The network-computer-class data processing system is integrated with a power supply having an early power fail warning signal to ensure that unsaved changes to user data files are saved before a complete power failure strikes the data processing system. As a user employs one or more applications to create or modify data files, a table of file changes is created for each user data file that is opened by the user. This table is kept in non-volatile media, preferably on the user's network computer but possibly on a server located on a network connected to the network computer if the network computer lacks non-volatile memory. The entire contents of the table are saved to non-volatile storage in the time interval between the early power fail warning signal going active and the power completely failing.
    Type: Grant
    Filed: October 7, 1999
    Date of Patent: March 18, 2003
    Assignee: International Business Machines Corporation
    Inventors: James Arthur Brewer, Sanjay Gupta
  • Patent number: 6519720
    Abstract: A sub-net operation with increased availability and reduced power consumption is achieved in a bus system with a plurality of stations (10, 11, 12) which are coupled to one another via a system of conductors (13, 14). Each of the stations includes a transceiver (21) and a control unit (30). The stations are switched from a quiescent state to a standby state in response to the reception of a first wake-up signal and selected stations are switched to a normal operating state upon reception of a second wake-up signal, whereby stations are selected.
    Type: Grant
    Filed: November 9, 1999
    Date of Patent: February 11, 2003
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Robert Mores
  • Publication number: 20020199131
    Abstract: A power module for a CNI avionics system includes a rechargeable back-up battery (17) and a battery charger (9) in a back-up battery channel, a power conversion unit (11, 25, 27 and 29) in a power conditioning channel, and a semiconductor switch (23) for selectively coupling either the output of the power conditioning channel unit or the back-up battery channel through to the module output (24) and the electronics of external LRM's of the cryptographic section of the CNI avionics system, and a microcontroller (14) for controlling voltages and spurious signal emanations. Sensors (51, 52, 54 & 55) provide information to the microcontroller. The microcontroller senses the state of prime power, current draw on the cryptographic devices and adjusts power output between the battery and power supply in real time.
    Type: Application
    Filed: June 21, 2001
    Publication date: December 26, 2002
    Inventor: Michael J. Kocin
  • Publication number: 20020199132
    Abstract: Systems and methods for providing an “Expert” diagnostic tool for circuit breakers are disclosed. The present invention provides information management, repair and service instructions, diagnostics, troubleshooting and training. The present invention also simplifies and streamlines replacement and spare parts research as well as providing a simplified ordering mechanism.
    Type: Application
    Filed: June 22, 2001
    Publication date: December 26, 2002
    Inventors: Joseph N. Lachimia, George McCracken
  • Patent number: 6493593
    Abstract: An electronic control unit includes a first microprocessor monitoring the operation of a second microprocessor and has a monitoring operation blocking unit for preventing the second microprocessor from being reset by the first microprocessor while the second microprocessor is loading from a memory thereof so that even when a control program is loaded into the monitoring microprocessor before one is loaded into the monitored microprocessor, the control program can be loaded with certainty. Each microprocessor executes a control program stored in the memory, and when a predetermined reloading condition has been established, executes a loading process for receiving load data transmitted thereto from outside into the memory.
    Type: Grant
    Filed: March 28, 2000
    Date of Patent: December 10, 2002
    Assignee: Denso Corporation
    Inventors: Takamichi Kamiya, Takehiro Abeta
  • Patent number: 6473355
    Abstract: A structure including volatile memory devices that are used by the host computer system as the storage media. The volatile memory devices include volatile memory device back up systems to provide power to both the volatile memory and non-volatile memory in the event of power failure. The volatile memory devices also connect directly to an expansion bus of the host computer system, such as a PCI bus. Therefore, the volatile memory devices of the invention include a high-speed path to the host computer system and the volatile memory devices of the invention are faster than prior art devices, use less power and are lower cost.
    Type: Grant
    Filed: December 1, 2000
    Date of Patent: October 29, 2002
    Assignee: Genatek, Inc.
    Inventor: Jason R. Caulkins
  • Publication number: 20020138785
    Abstract: A system and method for providing critical state monitoring for a power supply, such as an uninterruptible power supply (UPS), is provided. In one embodiment, the invention includes a notification system for at least one power supply coupled to a computer network and adapted to transmit information such as a trap over the computer network when one of the power supplies undergoes the entry of a critical state, wherein the notification system includes a computer system connected to the computer network and has running on it a monitoring program, a reporting program and a database. The monitoring program monitors the network and detects the information being associated with the entry of the critical state. The database stores the information relating to the information transmitted over the network being associated with the entry of the critical state. The reporting program reports over the computer network the information relating to the duration of the critical state.
    Type: Application
    Filed: March 20, 2001
    Publication date: September 26, 2002
    Inventors: Brad Hammond, Daniel J. Redmond, Jeffrey B. Collemer, Todd Giaquinto, Diane L'Heureux
  • Patent number: 6397322
    Abstract: A method and system for performing a task in an intrinsically safe environment using an intrinsically safe, integrated module located on the safe side to convey signals to and from a field device on the hazardous side. The integrated module is configurable in order to suit the electrical characteristics and requirements of the field device. Preferably, the integrated module is software configurable, in that the module can be configured by a command signal without using switches. Furthermore, the integrated module is configurable in order to control the field device in performing the task. The integrated module includes an input/output module which is electrically connected to the field device through a Zener barrier or a galvanic isolation barrier, and a power supply to power the field device through a Zener barrier.
    Type: Grant
    Filed: March 31, 2000
    Date of Patent: May 28, 2002
    Assignee: Schneider Automation, Inc.
    Inventor: Ralph Thomas Voss
  • Patent number: 6393584
    Abstract: A method and system are disclosed for efficiently storing an operating state of a data processing system having a volatile memory within a nonvolatile mass storage device. In response to a selected input, a determination is made whether storing the operating state of the data processing system is possible. If storing the operating state is possible, scheduling of tasks to be performed by the data processing system is halted. Data not required for operation of the data processing system is then removed from the volatile memory. The operating state of the data processing system is stored within the nonvolatile mass storage device, thereby enabling the operating state of the data processing system to be efficiently restored. Thereafter, power is removed from the data processing system. In response to restoring power to the data processing system, a determination is made whether the operating state of the data processing system is stored within the nonvolatile mass storage device.
    Type: Grant
    Filed: April 26, 1995
    Date of Patent: May 21, 2002
    Assignee: International Business Machines Corporation
    Inventors: Wayne A. McLaren, Joseph C. Polimeni, Frank J. Schroeder
  • Patent number: 6385707
    Abstract: A method and system for copying files between drives of a computer system is provided. The method begins where files are selected to be copied from a first drive of the computer system to a second drive of the computer system. The selected files include operating system files, program files and data files. The method then proceeds to commencing an initial copying of the selected files. While the initial files are being copied, a list of non-copied files is generated. The list of non-copied files represent files that are locked by an operating system. A raw data copy is performed during the initial copying by referencing a FAT table of the drive from which data is copied from for each file in the list of non-copied files. A shut down of the operating system is then commenced. The operating system is configured to shut down and release the files previously locked by the operating system.
    Type: Grant
    Filed: February 23, 1999
    Date of Patent: May 7, 2002
    Assignee: Adaptec, Inc.
    Inventor: Guido Maffezzoni
  • Patent number: 6377859
    Abstract: A maintenance interface device for use in a digital, loop-powered process control network includes an interface to either a two-wire input/output port of a field device or to a two-wire communication media, a control logic for determining a simple status of the field device or communication loop, and a display for displaying the simple status. The maintenance interface device may be used for fault analysis to detect whether a field device or a communication loop is operational or nonoperational, powered or unpowered, and generating a valid communication signal or generating an invalid communication signal. The maintenance interface device is adapted to perform simple functionality tests on a plurality of devices in a process control network including a loop controller, a digital control system, an operator console, a workstation, a personal computer, and a bridge to thereby detect the functionality of those devices on a communication wire.
    Type: Grant
    Filed: December 30, 1997
    Date of Patent: April 23, 2002
    Assignee: Fisher Controls International, Inc.
    Inventors: Larry K. Brown, Brent H. Larson, Harry A. Burns
  • Patent number: 6360331
    Abstract: A method and system for transparently failing over a legacy application from a first system to a second system of a server cluster by tracking and checkpointing changes to application configuration information stored in a system's local registry. When an application running on the first system makes a change to the application configuration information in a subtree of the registry, the change is detected and a snapshot of the subtree's data is taken. The snapshot is written to a storage device shared by systems of the cluster, such as a quorum disk. When the application is failed over to a second system, the snapshot for that application is retrieved from the quorum disk and written to the registry of the second system in a corresponding subtree. The application is then run on the second system using the most-recent application configuration information as modified by the other system in the cluster.
    Type: Grant
    Filed: April 17, 1998
    Date of Patent: March 19, 2002
    Assignee: Microsoft Corporation
    Inventors: John D. Vert, Sunita Shrivastava
  • Patent number: 6347378
    Abstract: A programmable logic device having redundant sets of logic blocks which are capable of being enabled or disabled. The programmable logic device includes a plurality of sets of logic blocks, a plurality of routing resources and a programming circuit. Good logic blocks are enabled and fully operational when programmed. Nonfunctional logic blocks are disabled, powered off and invisible to the programming software. Each set of logic blocks has a corresponding routing resource. The routing resource corresponding to an enabled set of logic blocks is capable of being configured to provide input and output data paths for the enabled set of logic blocks. The routing resource corresponding to a disabled set of logic blocks is capable of being configured to bypass the disabled set of the logic blocks. The programming circuit stores the configuration data for the routing resources and is capable of providing the configuration data to a routing resource that corresponds to an enabled set of logic blocks.
    Type: Grant
    Filed: April 24, 2000
    Date of Patent: February 12, 2002
    Assignees: Quicklogic Corp., Cypress Semiconductor Corp.
    Inventors: James MacArthur, Timothy Lacey
  • Patent number: 6345309
    Abstract: A communication management node checks a condition of a complex communication terminal apparatus when the complex communication terminal apparatus is connected with a real-time-processing-system network, selects and generates control software and setting information data in accordance with the condition of the complex communication terminal apparatus, and downloads the control software and setting information data into the complex communication terminal apparatus via the real-time-processing-system network, so that the complex communication terminal apparatus acts as a terminal in the real-time-processing-system network.
    Type: Grant
    Filed: July 1, 1998
    Date of Patent: February 5, 2002
    Assignee: Fujitsu Limited
    Inventors: Noriyuki Ohsawa, Isamu Kitagawa
  • Patent number: 6345369
    Abstract: Aspects for detecting environmental faults in redundant components of a computer system are described. In an exemplary method aspect, the method includes monitoring system environment conditions, including a status for redundant power supply and cooling components. The method further includes registering a failure condition with an appropriate error type when a monitored system environment condition exceeds a design threshold, and utilizing the registered failure condition as data in an architected error log.
    Type: Grant
    Filed: November 12, 1998
    Date of Patent: February 5, 2002
    Assignee: International Business Machines Corporation
    Inventors: Alongkorn Kitamorn, Charles Andrew McLaughlin, Kanisha Patel, Donald LeRoy Thorson
  • Patent number: 6324535
    Abstract: A method and apparatus converts an original query into a sequenced query that takes into account a range of values of a variable defined by a start and end point in performing the query. The start or end points are calculated if necessary and a query to collect all of the start and end points may be generated, and a query is generated that produces a constant set of start and end points defining consecutive periods, such that all the data in the tables related to the original query is constant over each of these periods. These two queries are merged into the original query to produce a sequenced query capable of execution on various database software and capable of taking into account the range of values of the variable in performing the original query.
    Type: Grant
    Filed: December 2, 1999
    Date of Patent: November 27, 2001
    Assignee: Amazon.com, Inc.
    Inventors: John Bair, Richard T Snodgrass
  • Patent number: 6321346
    Abstract: In an external storage, an I/O process is continued without any intervention of a user or a host system at failure of a controller. When a failure occurs in a controller, a host system 10 recognizes the failure of the controller. Before the failure is notified to the user and application to stop the job, the substitutive controller reads the SCSI-ID possessed by an SCSI port of the failed controller from a shared memory, registers the SCSI-ID of the SCSI port to the SCSI port associated with the substitutive controller, and erases by a port address resetting facility 45 of the substitutive controller the SCSI-ID possessed by an SCSI port of the failed controller. Thanks to the provision, since the SCSI-ID specified at issuance of an I/O request is transferred between the controllers, the user or the host system need not alter the I/O request issuing route. Moreover, while the host system does not recognize the error, the transfer can be conducted.
    Type: Grant
    Filed: October 20, 1999
    Date of Patent: November 20, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Akira Murotani, Toshio Nakano, Hidehiko Iwasaki, Kenji Muraoka
  • Patent number: 6298449
    Abstract: An integrated reliability enhancement device for providing high reliability operation of a personal computer is preferably embodied in an add-in card for insertion into a bus slot of the personal computer. The add-in card includes monitoring circuitry for detecting an array of events associated with operational failure of the computer including failure of a cooling fan, out-of-range temperature fluctuations within the computer housing, out-of-range deviations in power supply input voltage, out-of-range deviations in power supply output voltage, and out-of-range deviations in line current consumption by the computer. Upon detection of one of the events, data associated with the failure is written into an add-in card memory which is accessed periodically by application software of the host computer.
    Type: Grant
    Filed: July 29, 1998
    Date of Patent: October 2, 2001
    Assignee: Siemens Information and Communication Networks, Inc.
    Inventor: George E. Carter
  • Patent number: 6295577
    Abstract: A disc storage system having a host computer interface adapted to coupled to a host computer, a disc storage medium having a disc surface and a spindle motor coupled to the disc adapted to rotate the disc. A transducer is positioned for reading and writing data on the disc surface. The system further includes a volatile memory write cache and a non-volatile memory write cache adapted to store data during a power loss. A method is also provided for storing data prior to writing the data in a non-volatile memory cache in a disc storage system.
    Type: Grant
    Filed: February 23, 1999
    Date of Patent: September 25, 2001
    Assignee: Seagate Technology LLC
    Inventors: David B. Anderson, Mark A. Gaertner, Monty A. Forehand, Robert W. Norman, Jr.
  • Patent number: 6289467
    Abstract: The present invention discloses a method and apparatus for checking an installation of a plurality of power supply modules in a multiprocessor system having a plurality of processor modules. A detector detects if one of the processor modules is present. A voltage monitor monitors the voltage level of one of the power supply modules which corresponds to the processor module. A control circuit generates a control signal to turn off the power if the processor module is present and the voltage level is outside an operating range.
    Type: Grant
    Filed: May 8, 1998
    Date of Patent: September 11, 2001
    Assignee: Sun Microsystems, Inc.
    Inventors: Quentin J. Lewis, James F. Mara, Alex N. Pappas
  • Patent number: 6278902
    Abstract: A DSP of a servo control circuit obtains a movement value of a servomotor for each axis for each position-speed feedback processing cycle in accordance with a move command value for each axis delivered from a main processor with every distribution cycle, and also obtains a position correction value in accordance with pressure information detected by a sensor. The DSP of the servo control circuit carries out position-speed feedback processing with the use of a move command value which is obtained by correcting the movement value with the obtained position correction value, and drives the servomotor.
    Type: Grant
    Filed: March 3, 1999
    Date of Patent: August 21, 2001
    Assignee: Fanuc Ltd.
    Inventors: Yoshiki Hashimoto, Minoru Enomoto
  • Patent number: 6275946
    Abstract: An uninterrupted power supply (UPS) for a computer having a data storage element and an associated monitor, the computer operating on power supplied by an internal switch mode power supply (SMPS) system receiving line power, characterized in that the UPS comprises an internal device for installation inside the computer and the internal device supplies back up power and protection to the computer and to the monitor from power abnormalities and noises.
    Type: Grant
    Filed: March 12, 1999
    Date of Patent: August 14, 2001
    Assignee: Guardian On Board Ltd.
    Inventor: Ronen Meir
  • Patent number: 6269434
    Abstract: A recording and reproducing apparatus includes a nonvolatile memory which acts as a recording medium; and a control unit for executing recording and reproduction on the nonvolatile memory; wherein the nonvolatile memory includes a first area for recording management information of whole of the nonvolatile memory and a second area for recording data of respective files; wherein the first area has a first file management table produced at the time of start of recording of the files and including at least a first management area for managing information on addresses of start sectors of the files and a second management area for managing information on usable space areas of the files; wherein the second area has a second file management table produced at a leading portion of each of sectors of each of the files on a real-time basis during recording of the files and formed by link information on corresponding ones of the sectors; wherein when the control unit executes recording and reproduction on the nonvolatile
    Type: Grant
    Filed: November 5, 1999
    Date of Patent: July 31, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Kiichi Tanaka
  • Patent number: 6263453
    Abstract: A system and method for preventing damage to media files within a digital camera comprise a power manager for detecting power failures, an interrupt handler for responsively incrementing a counter device and a removable memory driver for performing memory access operations, evaluating the counter device to determine whether a power failure has occurred during the memory access operation and for repeating the memory access operation whenever a power failure has occurred during the memory access operation.
    Type: Grant
    Filed: April 29, 1999
    Date of Patent: July 17, 2001
    Assignee: Apple Computer, Inc.
    Inventor: Eric C. Anderson
  • Patent number: 6253329
    Abstract: A universal serial bus (USB) hub having a plurality of input power sources receives power through an upstream cable or from a local power source unit, and uses it for internal power consumption in the USB hub and for distribution to other USB functions through at least one downstream port. The hub includes a power source interface for inputting both bus power provided through the upstream cable and self-power generated by the local power source unit. Whether or not self-power is to be supplied is determined based on whether or not a user connects an additional power source cable to the USB hub. Thus, it is not necessary for the user to purchase a bus power USB hub or a self-power USB hub separately. The user can easily select a power source supply method which would fit his needs by simply adding a power source cable for self-power.
    Type: Grant
    Filed: January 19, 1999
    Date of Patent: June 26, 2001
    Assignee: SamSung Electronics Co., Ltd.
    Inventor: Hyun-Seek Kang