Reexecuting Single Instruction Or Bus Cycle Patents (Class 714/17)
  • Patent number: 11977745
    Abstract: A data retry-read method, a memory storage device, and a memory control circuit element are provided. The method includes: detecting a notification signal from a volatile memory module; in response to the notification signal, instructing the volatile memory module to execute N command sequences in a buffer; and after the volatile memory module executes the N command sequences, sending at least one read command sequence, according to M physical addresses involved in the N command sequences, to instruct the volatile memory module to read first data from the M physical addresses.
    Type: Grant
    Filed: August 11, 2022
    Date of Patent: May 7, 2024
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Ming-Hui Tseng, Chia-Lung Ma, Zhen-Yu Weng
  • Patent number: 11620183
    Abstract: A method for reducing observed processing latency in networked communication, the method comprising: receiving a first portion of data, the data consisting of the first portion and a second portion; initializing data processing on the data after receiving the first portion of data and before receiving the second portion of the data; receiving the second portion of the data, the second portion of the data including error-detection code; performing error detection on the data based on the error-detection code; in response to the error detection indicating that the data is valid, finalizing data processing on the data and committing a data-processing result; and in response to the error detection indicating that the data is invalid, performing an error-correction process.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: April 4, 2023
    Inventor: Johnny Yau
  • Patent number: 11544175
    Abstract: A SaaS system and methods for capturing dataflow integration and optimizing continuity of operation are presented. Consistent with some embodiments, the method may include receiving a dataflow, and calculating a plurality of attribute scores for the dataflow. The method may further include causing a client device to automatically store a dataflow from the dataflow in response to determining that at least a portion of the plurality of attribute scores are above a predefined threshold. The method may further include receiving a dataflow from a recording application associated with a client device and providing to the user of the client device dataflow-recording directions which are adapted to predetermined criteria that correspond to the purpose of dataflow-recording, the type of activity to be presented in said dataflow.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: January 3, 2023
    Assignee: ZERION SOFTWARE, INC
    Inventor: Warawut Amornkul
  • Patent number: 11449478
    Abstract: Computer-implemented methods, systems and computer program products leveraging blockchain networks to securely store a tamper-proof ledger comprising an audit trail describing the completion or missed data migration tasks, based on a timeline of an end-to-end data migration task schedule. Each of the event logs and alerts from the data migration source, data migration target, and/or migration tools, including network device logs, operating system logs, user-access logs, alerts, migration tool output etc. associated with the end-to-end migration tasks is made a part of the audit trail and stored to the ledger of the blockchain. All event logs, alert or other digital assets recorded to blocks of the blockchain can be timestamped, hashed and distributed across all nodes of the blockchain network and verified as valid by each of the peer nodes. As blocks updating the audit trail are added to the blockchain, the entries cannot be modified or tampered with.
    Type: Grant
    Filed: October 8, 2020
    Date of Patent: September 20, 2022
    Assignee: KYNDRYL, INC.
    Inventors: Kumar Saurabh, Gururajan Sundaramurthy, Susheel Gooly
  • Patent number: 11210161
    Abstract: In some embodiments, a processing system includes at least one hardware block configured to change operation as a function of configuration data, a non-volatile memory including the configuration data for the at least one hardware block, and a configuration module configured to read the configuration data from the non-volatile memory and provide the configuration data read from the non-volatile memory to the at least one hardware block. The configuration module is configured to: receive mode configuration data; read the configuration data from the non-volatile memory; test whether the configuration data contain errors by verifying whether the configuration data are corrupted and/or invalid; and activate a normal operation mode or an error operation mode based on whether the configuration data contain or do not contain errors.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: December 28, 2021
    Assignees: STMicroelectronics Application GMBH, STMicroelectronics S.r.l.
    Inventors: Roberto Colombo, Nicolas Bernard Grossier, Roberta Vittimani
  • Patent number: 11061713
    Abstract: The Prioritization and Source-Nonspecific Based Virtual Machine Recovery Apparatuses, Methods and Systems (“MBR”) transforms backup configuration request, restore request inputs via MBR components into backup configuration response, restore response outputs. A restore request is obtained. A reestablishing virtual machine is booted. A recovery virtual machine configuration identifying source-nonspecific software is determined. A recovery prioritization index for data blocks of the associated backup disk image is determined. Essential data blocks of the backup disk image are prefetched to build a pseudo abridged virtual machine. User access to the reestablishing virtual machine is provided. A latent virtual machine is created inside the reestablishing virtual machine. Command data blocks are fetched for both the reestablishing virtual machine and the latent virtual machine when a user command is received. Remaining data blocks are fetched for the latent virtual machine in priority order.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: July 13, 2021
    Assignee: Datto, Inc.
    Inventors: Campbell Hutcheson, William Robert Speirs, II, Robert J. Gibbons, Jr.
  • Patent number: 11032383
    Abstract: Systems and methods for dispatching targeted event notifications to subscribers are disclosed. In an embodiment, the system includes a receiver to receive events from a publisher. The system further comprises a router in communication with the receiver to route the events. The system further comprises a director to forward the targeted event notifications to the subscribers based on the routing. The director receives a delivery status of the targeted event notification from the subscribers. The delivery status includes one of success in receiving the targeted event notification and failure in receiving the targeted event notification. The director receives an event notification with the delivery status as failure in receiving the targeted event notification. The director places the targeted event notification in a delayed queue indicative of events to be delivered after a predefined time. The director re-transmits the targeted event notification to the subscribers based on the delayed queue.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: June 8, 2021
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Cesar M. Ruiz-Meraz, Clemens F. Vasters, David L. Stucki, Hillary Caituiro Monge, Hitesh Madan, Jayaraman Kalyana Sundaram, PadmaPriya Aradhyula Bhavani, Venkata Raja Gopal Ravipati
  • Patent number: 11012488
    Abstract: A system can include multiple content ingress sites to process content into portions of content. A content ingress site, of the multiple content ingress sites, can include a first set of devices. The first set of devices can be configured to process the content in a synchronized manner. The first set of devices can be configured to have excess processing capacity to facilitate failover of a first segmenter device to a second segmenter device. The first set of devices can be configured to process content from multiple sources. The system can include multiple content distribution sites to encode the portions of content. A content distribution site can include a second set of devices. The system can include multiple content satellite offices to provide the portions of content to one or more destination devices. A content satellite office can include a third set of devices.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: May 18, 2021
    Assignee: Verizon Patent and Licensing Inc.
    Inventors: Kevin Shen, Suri B. Medapati, Caleb Chaney, George So, Yinqing Zhao
  • Patent number: 10979499
    Abstract: A method, system and computer program product for managed object replication and delivery redirects, directly or indirectly, a client's request for an object that is not available at a best or optimal handling edge server of a network to a parent server that has the requested object. So, where the requested object is not available at the handling edge server, the client's request is redirected directly to the parent server that can provide the requested object to the client or indirectly via one or more parent servers to a parent server that can provide the requested object to the client. The method, system and computer program product further intelligently replicates the object to the edge server if the object is popular enough. Likewise, an object is removed from an edge server when it is no longer popular. All redirection and replication operations are preferably transparent to the end-user and do not degrade the quality of service.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: April 13, 2021
    Assignee: Level 3 Communications, LLC
    Inventors: Steven L. Seed, Kevin Hobbs, Shane M. Glynn, Isaac W. Foraker, Peter J. Jones, Homer H. Chen, William P. Greer
  • Patent number: 10963326
    Abstract: Rehabilitating storage devices in a storage array that includes a plurality of storage devices, including: receiving a request to rehabilitate a storage device that is operating outside of a defined range of expected operating parameters; selecting, from a hierarchy of rehabilitative actions that can be performed on the storage device, a rehabilitative action to perform on a storage device in dependence upon information describing a number of times that one or more of the rehabilitative actions have been performed on the storage device; and initiating execution of the selected rehabilitative action.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: March 30, 2021
    Assignee: Pure Storage, Inc.
    Inventors: Andrew Bernat, James Cihla, Jungkeun Kim, Iris McLeary, Damian Yurzola
  • Patent number: 10769627
    Abstract: A mobile device of a consumer can have a mobile-based credential stored in a secure memory thereof and an associated alias. Techniques for conducting a transaction with the mobile device may involve receiving a request for the mobile-based credential from a remotely accessible server in response to a requestor device receiving the alias from the consumer. The mobile-based credential can be accessed from the secure memory and transmitted to the remotely accessible server. The mobile-based credential is then usable at the remotely accessible server in combination with a server-based credential stored thereat for obtaining payment credentials to complete the transaction.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: September 8, 2020
    Assignee: Visa International Service Association
    Inventors: Horatio Nelson Huxham, Alan Joseph O'Regan
  • Patent number: 10684796
    Abstract: There are provided a memory system and an operating method thereof. In a method for operating a memory system, the method includes generating a write request for write data; reading chunk data from a buffer memory in response to the write request; caching the chunk data in a cache memory; generating a read request for read data; and outputting a portion of the cached chunk data as the read data from the cache memory when the read data is included in the cached chunk data.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: June 16, 2020
    Assignee: SK hynix Inc.
    Inventor: Do Hun Kim
  • Patent number: 10656987
    Abstract: A method, computer program product, and computing system for receiving temporal telemetry data portions concerning one or more elements of a storage system. A health score is assigned to the temporal telemetry data portions and a reliability score is assigned to the health score.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: May 19, 2020
    Assignee: EMC IP Holding Company LLC
    Inventors: Sooraj Nair, Charles S. Langley, Michael G. Varteresian, Muzhar Khokhar
  • Patent number: 10585766
    Abstract: A secondary location is configured as a recovery service for a primary location of the service. The secondary location is maintained in a warm state that is configured to replace the primary location in a case of a failover. During normal operation, the secondary location is automatically updated to reflect a current state of the primary location that is actively servicing user load. Content changes to the primary location are automatically reflected to the secondary location. System changes applied to the primary location are automatically applied to the secondary location. For example, removing/adding machines, updating machine/role assignments, removing adding/database are automatically applied to the secondary location such that the secondary location substantially mirrors the primary location. After a failover to the secondary location, the secondary location becomes the primary location and begins to actively service the user load.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: March 10, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Viktoriya Taranov, Daniel Blood, Alexander Hopmann, Siddharth Rajendra Shah, Tarkan Sevilmis, Nikita Voronkov, Ramanathan Somasundaram, Artsiom Kokhan, Bhavesh Doshi
  • Patent number: 10502779
    Abstract: A method, system and product for determining transient error functional masking and propagation probabilities. An Error Infliction Probability of pair of nodes (source and destination) is representative of a Transient Error happening on a source node propagating to the destination node. The probability is computed by simulating a propagation of a transient error for plurality of cycles in a given trace. The simulation utilizes values from the trace for nodes that are not influenced by the error (but may influence its propagation). A plurality of cycle-simulations may be performed and a ratio of a number of times the transient error propagated to the destination node compared to a number of cycles examined may be used to compute the error infliction probability.
    Type: Grant
    Filed: February 17, 2016
    Date of Patent: December 10, 2019
    Assignee: OPTIMA DESIGN AUTOMATION LTD.
    Inventors: Jamil Raja Mazzawi, Ayman Kamil Mouallem
  • Patent number: 10379976
    Abstract: The present disclosure relates to an automatic switching method and an automatic switching system. The automatic switching method includes: an automatic switching device monitoring in real time a service state of an operation server; when the automatic switching device monitors that the operation server has terminated providing service for a client terminal, the automatic switching device sending to the operation server a switching instruction for switching a current configuration of the operation server and sending to a backup server a notification message for switching a current configuration of the backup server; and the backup server switching the current configuration of the backup server to a preset first configuration according to the notification message, and providing service for the client terminal; wherein the first configuration is the configuration of the operation server when the operation server provided service.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: August 13, 2019
    Assignee: NUCTECH COMPANY LIMITED
    Inventors: Long Tian, Tao Wang, Hongzhi Ning
  • Patent number: 10331470
    Abstract: A virtual machine creation method and apparatus are provided to automatically create a virtual machine, and avoid an error that occurs during creation of the virtual machine. The method includes obtaining, by a cloud management platform at a production site, a first redundancy policy, obtaining, by the cloud management platform, storage replication information from M storage devices at the production site, determining, by the cloud management platform based on the storage replication information and from the M storage devices, N storage devices that meet the first redundancy policy, where N is an integer, and N?M, controlling, by the cloud management platform, a virtualization platform to create a virtual machine, and instructing, in a virtual machine creation request, to create a magnetic disk used by the virtual machine on the N storage devices to create the virtual machine.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: June 25, 2019
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Xiangyang Wu, Yajun Zhang, Rong Chen
  • Patent number: 10303551
    Abstract: Various embodiments for troubleshooting a network device in a computing storage environment by a processor. A determination is made if a parity error in a specific port is either an instruction cache parity error or a recoverable data cache type parity error. If the parity error is determined not to be the instruction cache parity error, and determined not to be the recoverable data cache type parity error, a full recovery operation is initiated.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: May 28, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matthew G. Borlick, Steven E. Klein, Ashwani Kumar, Micah Robison
  • Patent number: 10296500
    Abstract: A method performs large-scale data processing in a distributed and parallel processing environment. The method defines application-independent map and reduce operations, each invoking one or more library functions that automatically handle data partitioning, parallelization of computations, and fault tolerance. A user specifies a map operation, which calls one or more of the application-independent map operators to perform data read and write operations. A user also specifies a reduce operation, which calls one or more of the application-independent reduce operators to perform data read and write operations. The method executes application-independent map worker processes. Each map worker process executes the user-specified map operation to read designated portions of input files and store intermediate data values in intermediate data structures. The method also executes application-independent reduce worker processes.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: May 21, 2019
    Assignee: Google LLC
    Inventors: Jeffrey Dean, Sanjay Ghemawat
  • Patent number: 10270878
    Abstract: Systems and methods are described to enable and manage the use of origin-facing points of presence (“POPs”) within a content delivery network (“CDN”). Origin-facing POPs can provide a second-tier caching mechanisms in a CDN, such that cache misses occurring at first-tier POPs may be processed by using information maintained at the origin-facing POPs, rather than requiring interaction with an origin server. Associations between origin-facing POPs and origin servers may be automatically created based on a distance between the respective origin-facing POPs and origin servers, such that an operator of the origin server is not required to specify a location of an origin facing POP. First-tier POPs may selectively retrieve content from origin-facing POPs in instances where the origin-facing POP is expected to provide the content more rapidly than the origin server.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: April 23, 2019
    Assignee: Amazon Technologies, Inc.
    Inventors: Hardeep Singh Uppal, Matthew Graham Baldwin
  • Patent number: 10241875
    Abstract: An approach for at least one service processor to receive a notification of at least one failure during an initial program load of a server and to identify at least one step failing the initial program load. The at least one service processor determines whether a set of conditions are met to switch the initial program load responsibility from a master processor to a service processor. Furthermore, responsive to the at least one service processor determining that the set of one or more conditions are met to switch initial program load responsibility, the at least one service processor assumes the initial program load responsibility.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Manish K. Chowdhary, Raja Das, Nagendra K. Gurram, Deepak Kodihalli
  • Patent number: 10180865
    Abstract: A memory device includes a first interface that is to couple to a bidirectional link and a second interface to couple to a unidirectional link. An encoder generates first error-detection information corresponding to write data received via the bidirectional link for a write operation. An encoder generates second error-detection information corresponding to read data transmitted via the bidirectional link for a read operation. A transmitter coupled to the unidirectional link transmits the both the first and second error-detection information. A controller may receive the first and second error-detection information. Based on at least one of the first and second error-detection information, the controller may command the memory device to retry an operation.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: January 15, 2019
    Assignee: Rambus Inc.
    Inventors: Yuanlong Wang, Frederick A. Ware
  • Patent number: 10176031
    Abstract: An arithmetic processing device includes: a first register configured to hold data to be used to execute an instruction; a second register configured to hold a portion of the data held in the first register; a computing circuit configured to execute computation using the data held in the second register; a first error detector configured to detect whether or not an error is included in the data to be transferred by the first register to the second register; a controller configured to interrupt the execution of the instruction if the first error detector detects the error in the data; and an error corrector configured to correct the error in the data held in the first register if the first error detector detects the error in the data.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: January 8, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Kouji Kimura, Yoshiteru Ohnuki
  • Patent number: 10067695
    Abstract: A management server acquires storage and application information from a first system to store the information. The storage information includes storage area correspondence information indicating a correspondence between a storage area and a processor. The application information includes application correspondence information indicating a correspondence between the processor and an application, and application configuration information indicating a past Input/Output (IO) load on the storage area. The management server estimates an IO load on the storage area by the application based on the storage and application information to obtain an estimated value, and determines whether or not a copy processable period, a period in which a copy process of data can be performed is present, based on the data size and the estimated value. When the copy processable period is present, the management server transmits a copy indication including a start time of the copy processable period to a copy processing server.
    Type: Grant
    Filed: June 26, 2014
    Date of Patent: September 4, 2018
    Assignee: Hitachi, Ltd.
    Inventors: Takayuki Suzuki, Toru Tanaka, Keisuke Hatasaki, Toshio Otani, Atsumi Terayama
  • Patent number: 10061664
    Abstract: Systems, methods, and computer-readable storage media for high availability and failover. A device obtains an external identity designated for a set of devices on a network, the set of devices comprising the device and a second device, and the external identity comprising public address settings which the set of devices can use when in live mode to communicate with devices outside of the network. While the device is in failover mode and the second device is in live mode, the device listens for heartbeat messages transmitted from the second device. Next, the device detects a failover event when a predetermined number of heartbeat messages have not been received by the device. In response to the failover event, the device then changes from failover mode to live mode and assumes the external identity.
    Type: Grant
    Filed: January 15, 2015
    Date of Patent: August 28, 2018
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Patrick Douglas Verkaik, Robert Tristan Shanks
  • Patent number: 10055155
    Abstract: A secure SoC IC is disclosed herein. In embodiments, a SoC IC for computing may comprise a plurality of processor cores, wherein each processor core has at least one level of private cache and its own private memory to securely execute one or more applications. Further, the SoC IC may include a plurality of isochronous memory disposed between selected pairs of the processor cores to provide deterministic data transfers between the processor core pairs. Other embodiments may be disclosed or claimed.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: August 21, 2018
    Assignee: WIND RIVER SYSTEMS, INC.
    Inventor: Mati Sauks
  • Patent number: 10049023
    Abstract: Various systems, methods, and processes to perform recovery operations in a cluster based on exponential backoff models are disclosed. A node failure is detected. The node is one of multiple nodes in a cluster. In response to the node failure, an application executing on the node is failed over to another node in the cluster. In response to the detecting the node failure, recovery operations are automatically performed to determine whether the node is recovered. A subsequent recovery operation is performed after a prior recovery operation. The subsequent recovery operation is performed periodically based on a frequency that decreases exponentially after performing the prior recovery operation.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: August 14, 2018
    Assignee: Veritas Technologies LLC
    Inventor: Anand J. Bhalerao
  • Patent number: 9880898
    Abstract: Transmission control checking circuitry adds control check data to a transaction response which is received at a transaction master and compared with expected data at the transaction master. The expected data having control check data may be a unique transaction identifier. The transaction master generated the unique transaction identifier when it generated the transaction request and will check that the transaction responses include that unique transaction identifier. In this way, errors in the control of transmission of transactions (e.g., misrouting) may be detected.
    Type: Grant
    Filed: July 8, 2015
    Date of Patent: January 30, 2018
    Assignee: ARM Limited
    Inventors: Michael Williams, Simon John Craske, Loïc Pierron
  • Patent number: 9798598
    Abstract: An approach is provided for managing a failure of a critical high availability (HA) component in a HA system. Critical HA components are identified. Categories are assigned to the identified components and weights are assigned to the categories. A current value indicating a performance of a component included in the identified components is obtained by periodically monitoring the components. A reference value for the performance of the component is received. A deviation between the current value and the reference value is determined. Based on the deviation, the component is determined to have failed. Based in part on the failed component, the categories, and the weights, a health index is determined in real-time. The health index indicates in part how much the component having failed affects a measure of health of the HA system.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: October 24, 2017
    Assignee: International Business Machines Corporation
    Inventor: Arunachalam Jayaraman
  • Patent number: 9645949
    Abstract: Embodiments of the invention relate to a data processing apparatus including a processor adapted to operate under control of an executable comprising instructions, and in any of a plurality of operating modes including a non-privileged mode and a privileged mode, the apparatus comprising: means for storing a plurality of stacks; a first stack pointer register for storing a pointer to an address in a first of said stacks; a second stack pointer register for storing a pointer to an address in a second of said stacks, wherein said processing apparatus is adapted to use said second stack pointer when said processor is operating in either the non-privileged mode or the privileged mode; and means for transferring operation of said processor from the non-privileged mode to the privileged mode in response to at least one of said instructions. Embodiments of the invention also relate to a method of operating a data processing apparatus.
    Type: Grant
    Filed: May 27, 2009
    Date of Patent: May 9, 2017
    Assignee: Cambridge Consultants Ltd.
    Inventors: Alistair G. Morfey, Karl Leighton Swepson, Peter Giles Lloyd
  • Patent number: 9501317
    Abstract: Analytical methods and devices for detection of molecular processes, especially in genetics related environments are faced with the challenge of having to operate with the lack of coherent temporal frameworks that incorporate microscopic to macroscopic scale operations. Drawbacks in overcoming these challenges have resulted in substantial underutilization of resources and below optimum outcome as well. The present innovation as its technical solution to the problem outlined above discloses a computing based generic approach that facilitates incorporating operation of such processes as quantifiable entities in terms of a common temporal scale, thus establishing a coherent framework for coordinating operation of different processes that have varied temporal scales, namely, those occurring in temporal extents shorter as well as longer than its variable operational step enabling its adoption in a wide range of practical applications bringing multiple advantages.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: November 22, 2016
    Inventors: Indrajith Kuruppu, Don Damith Nadishan Colambathanthrige
  • Patent number: 9471424
    Abstract: The present technology relates to an information processing device and method, and a recording medium, which make it possible for a data recording system and so forth to be optimized in accordance with use. Provided are: a recording system decision unit that, on the basis of characteristics which are characteristics of data to be recorded in a recording medium, and include a lifespan value representing the retention period of the data and an error rate representing the percentage of errors assumed to be generated when the data is read, generates a plurality of recording regions of a logical device configured from the recording medium, and also decides recording systems to be applied in each of the recording regions; and a logical device initialization unit that initializes each of the recording regions of the logical device on the basis of the decided recording systems.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: October 18, 2016
    Assignee: Sony Corporation
    Inventors: Kazumi Sato, Tomohiro Katori
  • Patent number: 9460183
    Abstract: Method and high availability clusters that support synchronous state replication to provide for failover between nodes, and more precisely, between the master candidate machines at the corresponding nodes. There are at least two master candidates (m=2) in the high availability cluster and the election of the current master is performed by a quorum-based majority vote among quorum machines, whose number n is at least three and odd (n?3 and n is odd). The current master is issued a current time-limited lease to be measured off by the current master's local clock. In setting the duration or period of the lease, a relative clock skew is used to bound the duration to an upper bound, thus ensuring resistance to split brain situations during failover events.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: October 4, 2016
    Assignee: ZETTASET, INC.
    Inventor: Michael W. Dalton
  • Patent number: 9430599
    Abstract: A method, system and product for determining error infliction probability or probability. The method comprises obtaining a representation of a circuit, wherein the circuit comprises nodes, wherein the nodes comprise at least one critical node; obtaining a trace, wherein the trace comprises recorded values of the nodes in a plurality of cycles; determining, by a processor, a Soft Error Infliction Probability (SEIP) of a node, wherein the SEIP is a value representing a probability that a Single Event Upset (SEU) effecting the node in a cycle will inflict a soft error by propagating through the circuit to the at least one critical node, wherein said determining comprises simulating a propagation of the SEU from the cycle to consecutive cycles, wherein said simulating utilizes values from the trace which are associated with the consecutive cycles; and outputting the SEIP of the node.
    Type: Grant
    Filed: January 21, 2015
    Date of Patent: August 30, 2016
    Assignee: OPTIMA DESIGN AUTOMATION LTD
    Inventors: Jamil Raja Mazzawi, Ayman Kamil Mouallem
  • Patent number: 9361199
    Abstract: A system for monitoring a virtual machine executed on a host. The system includes a processor that receives an indication that a failure caused a storage device to be inaccessible to the virtual machine, the inaccessible storage device impacting an ability of the virtual machine to provide service, and applies a remedy to restore access to the storage device based on a type of the failure.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: June 7, 2016
    Assignee: VMware, Inc.
    Inventors: Joanne Ren, Igor Tarashansky, Keith Farkas, Elisha Ziskind, Manoj Krishnan
  • Patent number: 9323593
    Abstract: Embodiments of the present application disclose a method for saving a running log, including: when a running exception occurs in an operating system, configuring that a random access memory adapted to record a running log of the operating system works in a self-refresh mode; performing reset on an application processor of the operating system and keeping a power management unit working normally, where the power management unit is adapted to manage power of the application processor and the random access memory; acquiring the running log of the operating system from the random access memory and saving the running log of the operating system, after reset of the application processor is completed. The embodiments of the present application further disclose a device. By adopting the present application, it can be ensured that a log is saved completely during a preset process of the system.
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: April 26, 2016
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Yu Liu, Zhihui Jia, Cong Yao, Xiang Li
  • Patent number: 9223796
    Abstract: A video file system for an aircraft carrying a person having a personal electronic device (PED) for displaying video files includes a ground-based video server and an aircraft-based video system. The ground-based video server stores video files, with each video file being updatable from an available status to an unavailable status. The aircraft-based video system copies video files from the ground-based video server while the aircraft is on the ground. A determination is made, via communications with the ground-based video server and while the aircraft is on the ground, whether a given video file has been updated from the available status to the unavailable status. The PED is permitted to display the given video file if it has the available status, and is not permitted to display the given video file if it has the unavailable status.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: December 29, 2015
    Assignee: LIVETV, LLC
    Inventors: Michael J. Lynch, Michael G. Moeller
  • Patent number: 9075621
    Abstract: A data processing apparatus executes instructions in a sequence of pipelined execution stages. An error detection unit twice samples a signal associated with execution of an instruction and generates an error signal if the samples differ. An exception storage unit maintains an age-ordered list of entries corresponding to instructions issued to the execution pipeline and can mark an entry to show if the error signal has been generated in association with that instruction. A timer unit is responsive to generation of the error signal to initiate timing of a predetermined time period. An error recovery unit initiates a soft pipeline flush procedure if an oldest pending entry in the list has said error marker stored in association therewith and initiates a hard pipeline flush procedure if said predetermined time period elapses, said hard flush procedure comprising resetting said pipeline to a predetermined state.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: July 7, 2015
    Assignee: ARM Limited
    Inventors: Guillaume Schon, Mélanie Emanuelle Lucie Teyssier, Frederic Claude Marie Piry, Luca Scalabrino, David Michael Bull
  • Publication number: 20150113323
    Abstract: The present invention discloses a method and an apparatus for recovering abnormal data in an internal memory. The method includes: receiving, by a processor, a data abort signal and an address of an abnormal instruction where abnormal data is located; suspending a current instruction being executed, and recording an address pointed to by a computer pointer; obtaining a program unit currently being executed by the processor; if it is determined that the abnormal instruction belongs to the program unit and that instructions between the first instruction and the current instruction in the program unit are all reversible instructions, invoking a destruction program unit corresponding to the program unit, so as to release resources already applied for by the program unit; and causing the computer pointer to point back to an address of the first instruction in the program unit, and re-executing the program unit.
    Type: Application
    Filed: December 22, 2014
    Publication date: April 23, 2015
    Inventors: Weifeng Hui, Xiaogang Zhu
  • Patent number: 9015528
    Abstract: A method for online testing pipeline systems comprising a succession of stages separated by buffers each associated with an idle signal, or idle signal, and/or at least one status bit, comprising: detecting values of the idle signal and/or the corresponding status bits indicating the availability of a cycle or the abrupt interruption of the flow of operations in a pipeline, and indicating that a valid operation, executed by a stage in the pipeline, is followed by an unused cycle; maintaining the state of the buffer in order to allow said valid operation to be re-executed during the unused cycle indicated by said idle signal; re-executing, during the unused cycle, the valid operation, in order to obtain at least a first version and a second version of said valid operation; memorizing, at the output of the pipeline, the results that correspond to the first version of said repeated or re-executed operation, in order to compare with the results of said second version of the same repeated or re-executed operation;
    Type: Grant
    Filed: August 23, 2011
    Date of Patent: April 21, 2015
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Valentin Gherman, Yannick Bonhomme
  • Publication number: 20150095700
    Abstract: Instead of disabling PCI communication between system resources in a host computing device and I/O devices when a PCI Host Bridge (PHB) is unable to function, the host computing device may include a redundant PCI communication path for maintaining communication between the system resources and the I/O devices after a first PHB experiences an unrecoverable error. In one embodiment, the redundant PCI communication path includes a second PHB that is maintained in a standby state so long as the first PHB is functioning normally. However, once the first PHB experiences an unrecoverable error, the second PHB is changed to the master state and assumes the responsibility for maintaining communication between the system resources and the I/O devices.
    Type: Application
    Filed: December 8, 2014
    Publication date: April 2, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jesse P. ARROYO, Srinivas KOTTA, Anjan Kumar GUTTAHALLI KRISHNA
  • Patent number: 8959387
    Abstract: The present disclosure provides techniques for operating a tape drive. A method of operating a tape drive includes monitoring a parameter of the tape drive during a data access operation. The method also includes detecting an access failure. The method further includes selecting a treatment based on the parameter, applying the treatment, and performing a retry.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: February 17, 2015
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Donald J. Fasen, Vernon L. Knowles
  • Patent number: 8924784
    Abstract: An integrated circuit device includes a processor core, and a controller. The processor core issues a command intended for a first thread of a plurality of threads. The controller initiates de-allocates hardware resources of the controller that are allocated to the first thread during a thread reset process for the first thread, returns a specified value to the processor core in response to the first command intended for the first thread during the thread reset process, drops responses intended for the first thread from other devices during the thread reset process, completes the thread reset process in response to a determination that all expected responses intended for the first thread have been either received or dropped, and continues to issue requests to other devices in response to commands from other threads of the plurality of threads and processing corresponding responses during the thread reset process.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: December 30, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Kun Xu, David B. Kramer, Marie J. Sullivan
  • Patent number: 8909988
    Abstract: An error recovery unit that may include error logic to detect an error in a dispatch port and timestamp logic configured to generate a timestamp for the error. The error recovery unit may also include check logic to determine if an instruction associated with the error has been retired based on the timestamp. If the instruction has been retired, a machine check error logic may be initiated. If the instruction has not been retired, an error correction logic may be initiated to recover the error and to re-execute the instruction. Thus, speculative errors may be recovered without the need for calling the machine check error, which is undesirable because of its catastrophic nature. Therefore, machine check errors may be significantly reduced.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: December 9, 2014
    Assignee: Intel Corporation
    Inventors: Zeev Sperber, Ofer Levy, Michael Mishaeli, Ron Gabor
  • Patent number: 8904233
    Abstract: A failure caused by a soft-error including MNU, of an electronic apparatus is prevented, while suppressing increase of a mounting area, power consumption, and processing time. The electronic apparatus stores data indicating the state of a flip-flop included in a sequential logic circuit within an arithmetic unit, each time when execution is performed on a check point provided for every predetermined number of instructions. When a symptom of a soft-error is detected, the apparatus sets the state of the flip-flop included in the sequential logic circuit within the arithmetic unit, based on the data stored after execution of the instruction at the immediately preceding check point, and restarts execution from the next instruction, being subsequent to the instruction associated with the immediately preceding check point.
    Type: Grant
    Filed: February 9, 2011
    Date of Patent: December 2, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Hidefumi Ibe, Tadanobu Toba, Kenichi Shimbo, Hitoshi Taniguchi
  • Patent number: 8898516
    Abstract: A system and method for providing a fault-tolerant basis to execute instructions is disclosed. The system comprises an error detector, a rewriting module, a recovery engine, a fault locator and a fallback programming module. The error detector detects a first error in the execution of an instruction in a faulty stage unit of a first pipeline unit. The rewriting module rewrites the instruction to form a rewritten instruction responsive to detecting the first error. The recovery engine executes the rewritten instruction in the first pipeline unit. The error detector determines if a second error occurs in the execution of the rewritten instruction. Responsive to detecting the second error, the recovery engine selects a substitute stage unit for the faulty stage unit from a second pipeline unit. The fault locator locates a faulty component for the faulty stage unit. The fallback programming module establishes a fallback unit for the faulty component.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: November 25, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Makoto Honda, Kanji Hirano
  • Publication number: 20140223062
    Abstract: A protocol for executing the instructions of a non-authorized transaction on the same processor in a multiprocessor environment is provided. A first instruction of a non-authorized transaction including a sequence of instructions is executed. A determination of whether the unauthorized transaction is aborted after each executed instruction. In response to an abort, the non-authorized transaction is rolled back and restarted at the first instruction of the non-authorized transaction. In response to an absence of an abort, the next instruction is executed until all sequenced instructions of the non-authorized transaction are completed on a same processing device.
    Type: Application
    Filed: February 1, 2013
    Publication date: August 7, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Peter J. Relson
  • Publication number: 20140136895
    Abstract: An aspect includes providing rollback support in an exposed-pipeline processing element. A system includes the exposed-pipeline processing element with rollback support logic. The rollback support logic is configured to detect an error associated with execution of an instruction in the exposed-pipeline processing element. The rollback support logic determines whether the exposed-pipeline processing element supports replay of the instruction for a predetermined number of cycles. Based on determining that the exposed-pipeline processing element supports replay of the instruction, a rollback action is performed in the exposed-pipeline processing element to attempt recovery from the error.
    Type: Application
    Filed: November 15, 2012
    Publication date: May 15, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson, Ravi Nair
  • Publication number: 20140136894
    Abstract: An aspect includes providing rollback support in an exposed-pipeline processing element. A method for providing rollback support in an exposed-pipeline processing element includes detecting, by rollback support logic, an error associated with execution of an instruction in the exposed-pipeline processing element. The rollback support logic determines whether the exposed-pipeline processing element supports replay of the instruction for a predetermined number of cycles. Based on determining that the exposed-pipeline processing element supports replay of the instruction, a rollback action is performed in the exposed-pipeline processing element to attempt recovery from the error.
    Type: Application
    Filed: November 9, 2012
    Publication date: May 15, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce M. Fleischer, Thomas W. Fox, Hans M. Jacobson, Ravi Nair, Daniel A. Prener
  • Patent number: 8726081
    Abstract: A method for event management in asynchronous work processing including timing at least one step in an asynchronous work process, wherein the at least one step is performed by an application and the at least one step has an expected time of completion; determining an error preventing step completion in response to the expected time of completion expiring; correcting the error; and re-performing the at least one step.
    Type: Grant
    Filed: June 14, 2011
    Date of Patent: May 13, 2014
    Assignee: International Business Machines Corporation
    Inventors: Khalid A. Asad, David S. Cruley, John DiClemente, Paul Ilechko, David J. Mulley