Abstract: A method and a device are provided to be run in a network (or in particular on a network component of such network). The network has several network elements that are connected via a ring. One network element is a ring master with a primary port and a secondary port. The novel process includes the steps of (i) a failure along one direction of the ring is detected by the ring master; and (ii) the ring master sends a first message via its port that indicates the direction of the failure.

Abstract: Nano-antennas with a resonant frequency in the optical or near infrared region of the electromagnetic spectrum and methods of making the nano-antennas are described. The nano-antenna includes a porous membrane, a plurality of nanowires disposed in the porous membrane, and a monolayer of nanospheres each having a diameter that is substantially the same as a diameter of the nanowires. The nanospheres are electrically in series with the nanowires.

Abstract: Methods and systems associated with re-transferring data that was unsuccessfully transmitted to a host are described. According to one embodiment method includes receiving a first command to transfer data to a host, wherein the data is arranged in blocks. The data is transferred to the host. When an unsuccessful status is received from the host indicating a transmission error occurred for the first command, a block being transferred when the transmission error occurred is identified. The data in the identified block is re-transferred to the host without re-transferring successfully transferred blocks.

Abstract: An error recovery unit that may include error logic to detect an error in a dispatch port and timestamp logic configured to generate a timestamp for the error. The error recovery unit may also include check logic to determine if an instruction associated with the error has been retired based on the timestamp. If the instruction has been retired, a machine check error logic may be initiated. If the instruction has not been retired, an error correction logic may be initiated to recover the error and to re-execute the instruction. Thus, speculative errors may be recovered without the need for calling the machine check error, which is undesirable because of its catastrophic nature. Therefore, machine check errors may be significantly reduced.

Abstract: A system, method and computer program product, including a primary operating system (OS) having access to at least some hardware resources of the computer system. A Hypervisor controls a plurality of virtualization spaces and at least some of the remaining hardware resources. Each virtualization space maintains data of a corresponding instance of a Virtual Machine with a guest operating system running inside the Virtual Machine. Each Virtual Machine is associated with at least one virtual processor. A hyperswitch controlled by the Hypervisor starts and stops execution of the Virtual Machines. A scheduler dedicates a quantum of running time to each virtual processor. When the quantum is given to the Virtual Machine, the Hypervisor forces the hyperswitch to activate the Virtual Machine on its virtual processor.

Abstract: A processor is provided that is capable of concurrently processing a sequence of instructions for a plurality of threads achieving the retry success rate equivalent to the success rate in processors that process a sequence of instructions for a single thread. An arithmetic device 200 is provided with an instruction execution circuit 201 for executing a plurality of threads, or an execution control circuit 202 for controlling the execution state or rerunning of the threads.

Abstract: The present invention concerns a file repair method for recovering a file, in a system for distributing content to more than one receiver, comprising, at a first receiver, the steps of receiving a set of files in a push multicast from a transmitter, receiving an identifier of a second receiver that owns a missing file that is not comprised in the received set of file; and recovering the missing file from the second receiver in a pull mode using a peer-to-peer mechanism. Another object of the invention is a method for file recovery in a server and in a peer device.

Abstract: Fault tolerant operation is disclosed for a primary instance, such as a process, thread, application, processor, etc., using an active copy-cat instance, a.k.a. backup instance, that mirrors operations in the primary instance, but only after those operations have successfully completed in the primary instance. Fault tolerant logic monitors inputs and outputs of the primary instance and gates those inputs to the backup instance once a given input has been processed. The outputs of the backup instance are then compared with the outputs of the primary instance to ensure correct operation. The disclosed embodiments further relate to fault tolerant failover mechanism allowing the backup instance to take over for the primary instance in a fault situation wherein the primary and backup instances are loosely coupled, i.e. they need not be aware that they are operating in a fault tolerant environment.

Abstract: A system and method for providing a fault-tolerant basis to execute instructions is disclosed. The system comprises an error detector, a rewriting module, a recovery engine, a fault locator and a fallback programming module. The error detector detects a first error in the execution of an instruction in a faulty stage unit of a first pipeline unit. The rewriting module rewrites the instruction to form a rewritten instruction responsive to detecting the first error. The recovery engine executes the rewritten instruction in the first pipeline unit. The error detector determines if a second error occurs in the execution of the rewritten instruction. Responsive to detecting the second error, the recovery engine selects a substitute stage unit for the faulty stage unit from a second pipeline unit. The fault locator locates a faulty component for the faulty stage unit. The fallback programming module establishes a fallback unit for the faulty component.

Abstract: A system for transferring a live application from a source to a target machines includes memory capture component that monitors and captures memory segments associated with one or more memories, one or more sets of these memory segments comprising one or more applications, the memory segments changing while the live application is in execution. A frequency ranking component organizes the memory segments in an order determined by memory segment change frequency. A link identification component identifies one or more connecting links to one or more sets of peer machines, each set of machines connecting said source machine to said target machine, the link identifier further determining the bandwidth associated with each connecting link. A routing component preferentially routes one or more of the memory segments over said connecting links based on said order.

Abstract: After execution by a thread of an instruction for invoking a function containing unreliable code, a pointer is stored to thread local storage for the thread in one or more reserved registers. The thread local storage is a portion of memory of the computing device associated with the thread. In the thread local storage, a stack pointer is stored to a position in a call stack associated with the instruction for invoking the function. The function is called, thereby causing the function to execute. In response to a fault occurring in the function, the pointer to thread local storage is used to retrieve the stack pointer in the thread local storage. The position in the call stack is used in a recovery process for the fault.

Abstract: Methods and systems for performing a restart operation in a storage device include in response to receiving an unsuccessful status from the host indicating a transmission error occurred for the first command, determining in which one of the logical blocks the transmission error occurred and from which data needs to be resent, thereby identifying a restart logical block. The number of blocks in the restart logical block that were sent successfully are calculated, and it is determined that the block immediately following the blocks sent successfully is the block in which the transmission error occurred and from which the data needs to be resent, thereby identifying a restart block. An amount of data successfully sent in the restart block is determined; and an indication is provided to resend at least a portion of the data in the restart block to the host.

Abstract: In one embodiment, the present invention includes a method for determining a vulnerability level for an instruction executed in a processor, and re-executing the instruction if the vulnerability level is above a threshold. The vulnerability level may correspond to a soft error likelihood for the instruction while the instruction is in the processor. Other embodiments are described and claimed.

Abstract: Embodiments include a computer processor-error controller, a computerized device, a device, an apparatus, and a method. A computer processor-error controller includes a monitoring circuit operable to detect a computational error corresponding to an execution of a second instruction by a processor operable to execute a sequence of program instructions that includes a first instruction that is fetched before the second instruction. The computer processor-error controller includes an error recovery circuit operable to restore an execution of the sequence of program instructions to the first instruction in response to the detected computational error.

Abstract: A system and method communicates commands from a command originator to receiving devices, yet the receiving devices do not confirm receipt of the command. The most current command (e.g. the one with the highest sequence number) is rebroadcast by the command originator and the receiving devices, tending to be more frequent upon detection of an event indicating that the most current command was not received by at least one other device, and less frequently upon detection of an event indicating that the most current command was provided with sufficient duplication that if another device could receive it, the device likely did receive it, subject to a maximum and minimum rate.

Abstract: The present disclosure provides memory level error correction methods and apparatus. A memory controller is intermediate the memory devices, such as DRAM chips or memory modules, and a processor, such a graphics processor or a main processor. The memory controller can provide error correction. In an example, the memory controller includes a buffer to store instructions and data for execution by the controller and a replay buffer to store the instructions such that operations can be replayed to prior state before the error. An error detector receives data read from the memory devices and if no error is detected outputs the data. If an error is detected, the error detector signals the memory controller to replay the instructions stored in the replay buffer.

Abstract: A failure caused by a soft-error including MNU, of an electronic apparatus is prevented, while suppressing increase of a mounting area, power consumption, and processing time. The electronic apparatus stores data indicating the state of a flip-flop included in a sequential logic circuit within an arithmetic unit, each time when execution is performed on a check point provided for every predetermined number of instructions. When a symptom of a soft-error is detected, the apparatus sets the state of the flip-flop included in the sequential logic circuit within the arithmetic unit, based on the data stored after execution of the instruction at the immediately preceding check point, and restarts execution from the next instruction, being subsequent to the instruction associated with the immediately preceding check point.

Abstract: Embodiments include a computing system, a device, and a method. A computing system includes a processor subsystem having an adjustable operating parameter. The computing system also includes an information store operable to save a sequence of instructions. The computing system further includes a controller module. The controller module includes a monitor circuit for detecting an incidence of an operating-parameter-caused error corresponding to an execution of an instruction of the sequence of instructions by the processor subsystem. The controller further includes a control circuit for adjusting the adjustable operating parameter based upon an error-tolerant performance criterion.

Abstract: Methods and apparatus to debug a network application are described. A described example network includes a live control network to collect control messages to create a history of network states, the history of network states reflecting an order in which control messages are processed, the live control network to roll back from a current state to a past state upon detection of an improper sequence of messages and to process the messages in a corrected sequence, the corrected sequence to be stored in the history. The described example network further includes a virtualized network corresponding to the live control network, the virtualized network responsive to a command from an operator to step through the history to facilitate debugging.

Abstract: Embodiments of the invention provide an interrupt handler configured to distinguish between critical and non-critical unrecoverable memory errors, yielding different actions for each. Doing so may allow a system to recover from certain memory errors without having to terminate a running process. In addition, when an operating system critical task experiences an unrecoverable error, such a task may be acting on behalf of a non-critical process (e.g., when swapping out a virtual memory page). When this occurs, an interrupt handler may respond to a memory error with the same response that would result had the process itself performed the memory operation. Further, firmware may be configured to perform diagnostics to identify potential memory errors and alert the operating system before a memory region state change occurs, such that the memory error would become critical.

Abstract: A task execution apparatus includes an execution unit configured to execute a task on a plurality of devices, an acquisition unit configured to acquire a cause of failure in execution by the execution unit, a confirmation unit configured to confirm that each device of the plurality of devices on which the execution unit failed to execute the task does not support the task based on the cause, and a re-execution unit configured to re-execute the task on each of the plurality of devices on which the execution unit failed to execute the task, wherein the re-execution unit excludes each of the plurality of devices from a re-execution target of the task, in a case where the confirmation unit confirms that each of the plurality of devices does not support the task.

Abstract: A method including: displaying operation icons representing operations to be performed, a user selecting and arranging the operation icons to define a flow of data between operations and to form a graphical representation of a process, the user specifying an operation icon as a transaction boundary node at the end of a transaction region, and compiling instructions to execute the arranged operations wherein the beginning of a transaction region acts as a roll back point in the event of an error occurring in the transaction region.

Abstract: If an error occurs during workflow processing, the present invention interrupts job processing appropriately while dispersing a load to the devices. When executing a plurality of processing steps with a plurality of devices in accordance with workflow setting information that defines the sequence of processing, a workflow execution method of the present invention includes the steps of: interrupting the processing step being executed when an error occurs in a first device; searching the workflow setting information including the processing step in the first device in which the error has occurred; specifying a second device in which another processing step included in the searched workflow setting information is executed; giving a notification that the error has occurred in the first device to the second device; restarting the interrupted processing step when the first device is recovered; and giving a notification that the first device has recovered to the second device.

Abstract: In one embodiment, the present invention includes a method for determining a vulnerability level for an instruction executed in a processor, and re-executing the instruction if the vulnerability level is above a threshold. The vulnerability level may correspond to a soft error likelihood for the instruction while the instruction is in the processor. Other embodiments are described and claimed.

Abstract: A smart card comprises a storage unit in which various data are stored, a communication unit to perform data communication with an external apparatus, and a processing unit which executes processing corresponding to a command received via the communication unit. The processing unit of the smart card detects data judged to have data abnormality from the data stored in the storage unit in a case where the command received from the external apparatus is an abnormal data confirmation command, and notifies the external apparatus of response data including information indicating the data in which the data abnormality has been detected by the detection.

Abstract: A system and method communicates commands from a command originator to receiving devices, yet the receiving devices do not confirm receipt of the command. The most current command (e.g. the one with the highest sequence number) is rebroadcast by the command originator and the receiving devices, tending to be more frequent upon detection of an event indicating that the most current command was not received by at least one other device, and less frequently upon detection of an event indicating that the most current command was provided with sufficient duplication that if another device could receive it, the device likely did receive it, subject to a maximum and minimum rate.

Abstract: According to one embodiment, a memory control device includes a first controller, a second controller, an access module, and a response sort module. The first controller controls processing of a data access command to a nonvolatile memory from a host. The second controller controls processing assigned to the second controller between the first controller and the second controller. The access module performs data access to the nonvolatile memory in response to a command from the first controller or the second controller. When an error occurs in the data access by the access module, the response sort module returns a response to the second controller instead of the first controller.

Abstract: This method is an error correction method such that, when an error is detected in a CPU with pipeline structure, a content of a register file is restored by a delayed register file which holds an execute completion state of an [Instruction N] correctly executed before this error, and a rollback control that re-executes an instruction from the [Instruction N+1] which is the next instruction of the [Instruction N] is performed. The method collects a parity check result of arbitrary Flip-Flops existing inside the CPU, and detects an error. As a result, the content of the register file is restored into the instruction execute completion state preceding to the instruction range likely to malfunction by the error, and the instruction can be roll backed from the beginning of the instruction range likely having malfunctioned by the error.

Abstract: In one embodiment, the present invention includes a method for determining a vulnerability level for an instruction executed in a processor, and re-executing the instruction if the vulnerability level is above a threshold. The vulnerability level may correspond to a soft error likelihood for the instruction while the instruction is in the processor. Other embodiments are described and claimed.

Abstract: A circuit arrangement and method utilize existing redundant execution pipelines in a processing unit to execute multiple instances of stability critical instructions in parallel so that the results of the multiple instances of the instructions can be compared for the purpose of detecting errors. For other types of instructions for which fault tolerant or stability critical execution is not required or desired, the redundant execution pipelines are utilized in a more conventional manner, enabling multiple non-stability critical instructions to be concurrently issued to and executed by the redundant execution pipelines. As such, for non-stability critical program code, the performance benefits of having multiple redundant execution units are preserved, yet in the instances where fault tolerant or stability critical execution is desired for certain program code, the redundant execution units may be repurposed to provide greater assurances as to the fault-free execution of such instructions.

Abstract: A recording apparatus includes a server, a client, a virtual device, a judgment section, and a regeneration section. The server executes an access to a storage medium as a service. The client includes processes that require the service. The virtual device is used to perform communication between the server and the client using a socket. The judgment section judges, when a process of the client opens the virtual device, whether the virtual device is already opened. The regeneration section regenerates, when the virtual device is already opened, a file descriptor for the process that references the socket based on an existing kernel file table.

Abstract: A master includes a unit configured to register, for each slave, an expected communication time needed to exchange control data; a unit configured to register a slave in which a communication error is detected during exchange of the control data in a communication period; and a unit configured to re-execute exchange of the control data with the registered slave in the same communication period as that in which the communication error is detected. The unit configured to re-execute exchange of control data calculates a remaining resending time that can be used to re-execute exchange of the control data and, when the remaining resending time is longer than the expected communication time of the registered slave, resends the control data.

Abstract: A processor comprises a processor core and a controller. The processor core has an execution unit configured to execute instructions and to attempt to perform at least one operation in executing one of the instructions. The processor core is configured to detect a processor error associated with the at least one operation. The controller is configured to change an operating point of the processor core in response to a detection of the processor error such that the processor core operates at a new operating point, and the processor core is configured to retry the at least one operation while the processor core is operating at the new operating point.

Abstract: A method, system and article of manufacture are disclosed for error recovery in a replicated state machine. A batch of inputs is input to the machine, and the machine uses a multitude of components for processing those inputs. Also, during this processing, one of said components generates an exception. The method comprises the steps of after the exception, rolling the state machine back to a defined point in the operation of the machine; preemptively failing said one of the components; re-executing the input batch in the state machine; and handling any failure, during the re-executing step, of the one of the components using a defined error handling procedure. The rolling, preemptively failing, re-executing and handling steps are repeated until the input batch runs to completion without generating any exception in any of the components that are not preemptively failed.

Abstract: A pipelined execution unit uses the bubbles that occur during execution to selectively repeat operations performed in one or more stages of a multistage execution pipeline to verify the results of such operations during otherwise unused execution cycles for the execution pipeline. Whenever a bubble follows a particular instruction within an execution pipeline, the result of an operation that is performed for that instruction by a particular stage of the execution pipeline may be stored, and the operation may be repeated by the stage in a subsequent execution cycle in which no productive operation would otherwise be performed due to the presence of the bubble. The results of the operations may then be compared and used to either verify the original result or identify a potential error in the execution of the instruction.

Abstract: Fault tolerant operation is disclosed for a primary instance, such as a process, thread, application, processor, etc., using an active copy-cat instance, a.k.a. backup instance, that mirrors operations in the primary instance, but only after those operations have successfully completed in the primary instance. Fault tolerant logic monitors inputs and outputs of the primary instance and gates those inputs to the backup instance once a given input has been processed. The outputs of the backup instance are then compared with the outputs of the primary instance to ensure correct operation. The disclosed embodiments further relate to fault tolerant failover mechanism allowing the backup instance to take over for the primary instance in a fault situation wherein the primary and backup instances are loosely coupled, i.e. they need not be aware that they are operating in a fault tolerant environment.

Abstract: Method and system are disclosed for redelivering failed messages in asynchronous communication systems. The methods and systems automatically delay redelivery of such failed messages in order to allow required system resources to become available. In one implementation, the methods and systems provide two levels of redelivery: a micro level in which redelivery is attempted right away for a certain number of times, and a macro level in which a predefined, user-selectable delay is imposed before any additional micro level redeliveries are attempted. After a certain number of unsuccessful macro level redeliveries, the message is backed out to a backout queue for manual intervention by a system operator. Such an arrangement reduces or eliminates the burden on the system operator to manually resolve failed message deliveries.

Abstract: A thread has a corruption detection mechanism that compares a beginning state of a function with an ending state to determine any inconsistencies. Based on the type of inconsistency, a remedial action may be taken, such as ignoring the inconsistency, cleaning up the inconsistency, and terminating the thread with an exception. The analysis may also include analyzing various states after function execution to find problems such as incomplete transactions. Such a thread may be useful in an operating system as well as a multi-threaded application environment.

Abstract: A microprocessor includes a plurality of execution units configured to receive instructions and operands thereof and to execute the instructions. An instruction scheduler issues the instructions to the execution units and selects sources of the instruction operands. At least one of the execution units detects one of the operands of one of the instructions is a denormal operand, generates an indication that the instruction needs to be replayed in response to detecting the denormal operand, and provides the denormal operand to the instruction scheduler in response to detecting the denormal operand, rather than normalizing the denormal operand. The instruction scheduler normalizes the denormal operand, in response to the indication, and causes the normalized operand, rather than the denormal operand, to be provided to the execution unit when the instruction is replayed.

Abstract: A method for running a computer program on computing hardware, in particular on a microprocessor. The computer program includes multiple program objects designed as tasks, for example. Transient and permanent errors are detected during the running of the computer program on the computing hardware. To be able to handle these transient errors constructively when they occur in a computer system in such a way that the functionality and function reliability of the computer system are restored within the shortest possible error tolerance time, at least one program object that has already been sent for execution is set into a defined state on detection of an error and is restarted from this state. The program object is a runtime object of the computer program, for example, also known as a task. One or more tasks that are still being executed or have already been executed on occurrence of an error are restarted and run again.

Abstract: The present invention provides a computer implemented method and apparatus for unmounting file systems from a plurality of file servers. The method comprises of issuing an unmount command targeting a file system of a first server among the plurality of file servers. The timeout period is then expired without receiving an unmount acknowledgement associated with the unmount command. Thus, the timeout period is associated with an allowable time for the file system to acknowledge unmounting. In response to expiring the timeout period, a ping is transmitted to the first server among the plurality of file servers. The ping timeout then expires based on a failure to receive a ping acknowledgment corresponding to the ping. This action marks the first server for a later retry of unmounting to form a marked set based on the first server.

Abstract: A system is designed for processing instructions in real time during a session. This system comprises: a preloader for obtaining reference data relating to the instructions, the reference data indicating the current values of each specified resource account data file, and the preloader being arranged to read the reference data for a plurality of received instructions in parallel from a master database; an enriched instruction queue for queuing the instructions together with their respective preloaded reference data; an execution engine for determining sequentially whether each received instruction can be executed under the present values of the relevant resource account files and for each executable instruction to generate an updating command; and an updater, responsive to the updating command from the execution engine (for updating the master database with the results of each executable instruction, the operation of the plurality of updaters being decoupled from the operation of the execution engine.

Abstract: Embodiments of the invention relate to methods and systems for error detection and recovery from errors during pipelined execution of data. A cascaded, delayed execution pipeline may be implemented to maintain a precise machine state. In some embodiments, a delay of one or more clock cycles may be inserted prior to a write back stage of each pipeline to facilitate error detection and recovery. Because a precise machine state is maintained error detection and recovery mechanisms may be built directly into register files of the system. If an error is detected execution of the instruction associated with the error and all subsequent instructions may be restarted.

Abstract: A client device includes a command processing device. The command processing device is configured to transmit an error signal while in an abnormal operation mode to prevent an error due to no response to a command received from an external source and process the command while in a normal operation mode. The error signal is indicative of the abnormal operation mode.

Abstract: In one embodiment, a quantum detector is provided to detect a vulnerability measure for a processor based on a processor metrics each associated with operation of a processor structure during a quantum, along with a controller to control an error mitigation unit based on the vulnerability measure. Other embodiments are described and claimed.

Abstract: The present invention provides a data migration management apparatus that can easily create a re-execution task for re-executing an error-terminated data migration task, and also can increase the possibility of the re-execution task being successful. In a case where a data migration from a migration-source volume to a migration-destination volume fails, the management apparatus uses the information of the failed task to create a re-execution task. The management apparatus changes the configuration of a volume pair as necessary. The management apparatus manages the failed task in association with the re-execution task.

Abstract: The invention relates to computer engineering, and its usage ensures the possibility to recognize types of failures occurring during operation of the program computing means, and to respond respectively for a failure of each type. The failures can include errors in storing the core memory content, control transfer to wrong command errors, and errors relating to various time interruptions during a program run.

Abstract: A computer implemented method, apparatus, and computer program product for managing state data in a workload partitioned environment. Process state data for a process in a workload partition is saved. Process state data is used to restore the process to a given state. State data associated with open sockets and open files bound to the first process is saved. In response to a determination that the process is associated with a domain socket that is bound to a socket file, an absolute pathname for the socket file is saved. A domain socket associated with a connecting process in the workload partition uses the socket file to connect to a domain socket associated with a listening process in the same workload partition to enable the two processes to communicate with each other.

Abstract: A method for running a computer program on computing hardware, in particular on a microprocessor, is described, the computer program including multiple program objects and errors being detected in the method while running the computer program on the computing hardware, the program objects being subdivided into at least two classes and program objects of the first class being repeated when an error is detected and, when an error is detected in one program object of the first class, which has already been sent for execution, this program object of the first class being restarted instead of a program object of the second class.

Abstract: A new method for the detection and correction of environmentally induced functional interrupts (or “hangs”) induced in computers or microprocessors caused by external sources of single event upsets (SEU) which propagate into the internal control functions, or circuits, of the microprocessor. This method is named Hardened Core (or H-Core) and is based upon the addition of an environmentally hardened circuit added into the computer system and connected to the microprocessor to provide monitoring and interrupt or reset to the microprocessor when a functional interrupt occurs. The Hardened Core method can be combined with another method for the detection and correction of single bit errors or faults induced in a computer or microprocessor caused by external sources SEUs.