Abstract: A master includes a unit configured to register, for each slave, an expected communication time needed to exchange control data; a unit configured to register a slave in which a communication error is detected during exchange of the control data in a communication period; and a unit configured to re-execute exchange of the control data with the registered slave in the same communication period as that in which the communication error is detected. The unit configured to re-execute exchange of control data calculates a remaining resending time that can be used to re-execute exchange of the control data and, when the remaining resending time is longer than the expected communication time of the registered slave, resends the control data.

Abstract: A data reading method includes the steps of: a reading request issuing step of issuing a reading request for reading predetermined stored data; and a reading request re-issuing step of re-issuing a reading request when read data responsive to the reading request has not arrived within a predetermined time period, wherein: in the reading request re-issuing step, a flag is attached to the re-reading request, and thus, the re-reading request is differed from the first issued reading request.

Abstract: An information processing apparatus that has multiple functional parts and power management domains that serve as control units when supplying power to the functional parts, and that autonomously controls supply of power to the power management domains, the apparatus including a power supply control part that supplies power to only a power management domain that includes the functional part associated with execution of an input instruction, and that stops the power supply to the power management domain in response to termination of execution of an instruction by the functional part; and an execution result storage part that stores a result generated by execution of an instruction by the power management domain to which power is supplied by the power supply control part, independently of the power supply control part supplying power and stopping the supply of power; wherein, after supply of power to a power management domain that terminates execution of an instruction is stopped by the power supply control par

Abstract: A method, apparatus and system for restarting an emulated mainframe IOP, such as a failed or hung emulated mainframe IOP within an emulated mainframe commodity computer. The method includes a rescue process that polls a home location for Restart Request information. In response to receiving Restart Request information, the rescue process is configured to shut down the existing emulated mainframe IOP, start a new emulated mainframe IOP, and reset the home location. The Restart Request information can be provided to the home location by the mainframe computer being emulated. Alternatively, the rescue mechanism can use an interface management card instructed to restart the commodity computer hosting the failed or hung IOP, e.g., from a maintenance service and/or a maintenance program residing in an active commodity computer coupled to the commodity computers hosting one of several emulated mainframe IOPs.

Abstract: A system and method for state-based execution and recovery in a payment system is presented. A payment system uses a state machine to track completed sub-tasks using a state progress identifier and completion state data. When a failure occurs, stored completion state data and the state progress identifier indicate the last successfully completed sub-task. As such, when the payment system resumes payment operation execution after a failure, the state machine retrieves the stored completion state data and state progress identifier, and resumes execution based upon the retrieved information. As a result, the payment system continues payment operation execution at a point as to not duplicate the payment operation's previously completed sub-tasks.

Abstract: A method for executing a computer program on computing hardware, e.g., on a microprocessor, is provided, the computer program including multiple program objects and errors being detected in the method while running the computer program on the computing hardware. The program objects are subdivided into at least two classes, and multiple program objects are executed during one run, program objects of the first class being repeated when an error is detected and, when an error is detected in one program object of the first class, which has already been sent for execution, this program object of the first class is restarted instead of a program object of the second class after the other program objects of the first class of a run.

Abstract: A data transmission system includes a first data transmission device for receiving commands from a host; a second data transmission device for transmitting commands to a memory device; and a crossbar device for receiving commands from the first data transmission device over a first link and transmitting the commands to the second data transmission device over a second link. The crossbar device includes status logic to detect a command transmission error on the first link from the first data transmission device and transmits a retry command to prompt the first data transmission device to retry the transmission of the command over the first link. The second data transmission device reports a transmission error on the second link to the status logic of the crossbar device and the status logic of the crossbar device transmits the retry command to prompt the first data transmission device to retry the transmission of the command over the first link.

Abstract: A method for executing a computer program on computing hardware, e.g., on a microprocessor, is provided, the computer program including multiple program objects and errors being detected in this method while the computer program is running on the computing hardware. When an error is detected, at least one program object, which has already been sent for execution, is transferred into a defined state and is restarted from there, and subsequent additional program objects are shifted.

Abstract: A processor is provided that is capable of concurrently processing a sequence of instructions for a plurality of threads achieving the retry success rate equivalent to the success rate in processors that process a sequence of instructions for a single thread. An arithmetic device 200 is provided with an instruction execution circuit 201 for executing a plurality of threads, or an execution control circuit 202 for controlling the execution state or rerunning of the threads.

Abstract: A system, method and media for performing a composite task, comprising: determining an undo task for each subtask in a plurality of subtask for the composite task; performing each one of the plurality of subtasks; performing the associated undo task for each subtask that was performed if the performing of any subtask in the plurality of subtasks fails. This abstract is not intended to be a complete description of, or limit the scope of, the invention. Other features, aspects and objects of the invention can be obtained from a review of the specification, the figures and the claims.

Abstract: A method maintains a hierarchy of application objects in a computer system. The method includes automatically detecting an exit of a child application object, the exit resulting from a failed process, the child application object launched by a parent application object. A grandchild application object is automatically terminated after the exit of the child application object, the grandchild application object launched by the child application object. Notwithstanding the exit of the child application object, the computer system, which maintains the hierarchy of application objects, the parent application object, and the grandchild application object, remains active.

Abstract: Embodiments include a controller apparatus, a computerized apparatus, a device, an apparatus, and a method. A controller-apparatus includes a monitoring circuit for detecting a computational error corresponding to an execution of an instruction of a sequence of instructions by a processor subsystem having an adjustable operating parameter. The controller apparatus also includes a recovery circuit for rolling back an execution of the sequence of instructions to a checkpoint in response to the detected computational error. The controller apparatus further includes a control circuit for adjusting the adjustable operating parameter in response to a performance criterion.

Abstract: A clock synchronizer, for generating a local clock signal synchronized to a received clock signal, is described and claimed, along with a corresponding clock synchronization method. The clock synchronizer incorporates a reference oscillator providing a reference signal, and a synthesizer circuit arranged to synthesize a local clock signal from the reference signal. The synthesizer circuit comprises a phase-locked-loop circuit, including a phase detector receiving the reference signal, and a controllable divider arranged in a feedback path from a controlled oscillator to the phase detector, the divider being controllable to set a frequency division value N along the path to determine a ratio of the local clock frequency to the reference frequency. The clock synchronizer also incorporates a clock comparison circuit adapted to generate a digital signal indicative of an asynchronism between the local and remote clock signals. A control link is arranged to link the clock comparison circuit to the divider.

Abstract: A method and system for supporting recovery of a computing device includes determining and storing a sub-set of firmware instructions used to establish a pre-boot environment and executing the sub-set of firmware instructions in response to an error.

Abstract: In one embodiment, the present invention includes a method for determining a vulnerability level for an instruction executed in a processor, and re-executing the instruction if the vulnerability level is above a threshold. The vulnerability level may correspond to a soft error likelihood for the instruction while the instruction is in the processor. Other embodiments are described and claimed.

Abstract: A slave device adapted to couple to a master processor and including an error handler and a communication controller. The error handler is configured to detect errors internal to the slave device and, in response to detecting at least one error and independent of the master processor, configured to select an error recovery operation based on the at least one detected error and to initiate and perform the selected error recovery operation. The communication controller is configured to communicate with the master processor according to a master/slave protocol, and configured to maintain the master/slave protocol during performance of the selected error recovery operation by the error handler.

Abstract: The present invention discloses re-configurable data transmission ports with data-integrity transaction controlling unit in a computerized computer and the method for performing the same. The controlling unit further includes a port-configuration detecting mechanism and a buffer-configuration subunit. The port-configuration detecting mechanism can inspect configuration status of all of the first ports on variance of data transmission bandwidths, e.g. “merge” or “spilt” status. The buffer-configuration subunit upon different configuration status of each first port configures each retry buffer. When a specific first port is configured on “merge” status, the buffer-configuration subunit can follows up to configure the retry buffer owned by the specific first port and the retry buffers owned but disused by the other first ports to constitute a buffer group with merging of storing spaces of said configured retry buffers.

Abstract: In one embodiment, a processor comprises a first register file configured to store speculative register state, a second register file configured to store committed register state, a check circuit and a control unit. The first register file is protected by a first error protection scheme and the second register file is protected by a second error protection scheme. A check circuit is coupled to receive a value and corresponding one or more check bits read from the first register file to be committed to the second register file in response to the processor selecting a first instruction to be committed. The check circuit is configured to detect an error in the value responsive to the value and the check bits. Coupled to the check circuit, the control unit is configured to cause reexecution of the first instruction responsive to the error detected by the check circuit.

Abstract: A process group resource manager for managing protected resources during transaction processing is disclosed. The process group resource manager comprises a first process configured to provide access to a protected resource during one or more transactions, the first process being further configured to construct a transaction record for each respective transaction, wherein each transaction record includes each request message received by the first process and each response message sent by the first process during a particular transaction. The process group resource manager further comprises a second process configured to serially replay the transactions in which the first process participates, the second process being configured to cause a particular transaction to rollback if the replay of that transaction does not match the transaction record constructed by the first process for that transaction.

Abstract: A detection and recovery mechanism is herein disclosed for soft errors corrupting TLB data. The mechanism works with a hardware page walker (HPW) and instruction steering control mechanisms in a processor to provide soft error recovery in the TLB arrays and latches. Through use of the disclosed detection and recovery mechanism, efficient and robust protection from silent data corruption is provided without requiring more expensive built-in redundancy.

Abstract: A processor comprises a processor core and a controller. The processor core has an execution unit configured to execute instructions and to attempt to perform at least one operation in executing one of the instructions. The processor core is configured to detect a processor error associated with the at least one operation. The controller is configured to change an operating point of the processor core in response to a detection of the processor error such that the processor core operates at a new operating point, and the processor core is configured to retry the at least one operation while the processor core is operating at the new operating point.

Abstract: A parity generating circuit reverses generated parity data to detect a parity error of a CSE entry during a determination of completion to execute a command retry. A parity check circuit that detects a parity error requests for the execution of the command retry. When a command retry mechanism stops a program and interrupts a verification, the execution of the command retry is suppressed by assuming that no parity error is detected.

Abstract: A command is received, at a network storage driver, from an operating system storage stack, wherein the command is for communication with a target storage device over a connection across a network. The command is selectively executed, a plurality of times over the connection, for communicating with the target storage device, in response to a determination that the command failed to successfully communicate with the target storage device within a threshold period of time.

Abstract: Software techniques are employed to mitigate soft errors. In particular, a compiler (or other executable code generator) may emit otherwise duplicative instructions targeting otherwise duplicative storage locations to facilitate run-time detection and, in some cases, mitigation of soft errors. In general, a compiler emits a program sequence of primary instructions that correspond to source code. However, in addition, for those primary instructions that target storage susceptible to soft errors, the compiler may emit corresponding additional instructions that target additional storage. In some implementations the additional storage is not itself susceptible to soft errors. However, more generally, implementations may tolerate soft errors affecting the additional storage, as long as such soft errors are generally uncorrelated with those affecting the storage targeted by the primary instructions.

Abstract: In some embodiments an apparatus includes a transmission error detector to detect an error of a transmission of an interconnect and a transmitting agent to retry the transmission in response to the detected error. The apparatus also includes a hard failure detector to detect a hard failure of the interconnect if the retry is unsuccessful, and a transmission width reducer to reduce a transmission width of the interconnect in response to the hard failure detector. Other embodiments are described and claimed.

Abstract: A new method for the detection and correction of errors or faults induced in a computer or microprocessor caused by external sources of single event upsets (SEU). This method is named Time-Triple Modular Redundancy (TTMR) and is based upon the idea that very long instruction word (VLIW) style microprocessors provide externally controllable parallel computing elements which can be used to combine time redundant and spatially redundant fault error detection and correction techniques. This method is completed in a single microprocessor, which substitute for the traditional multi-processor redundancy techniques, such as Triple Modular Redundancy (TMR).

Abstract: A system that migrates a process from a source computer system to a target computer system. During operation, the system generates a checkpoint for the process on the source computer system, wherein the checkpoint includes a kernel state for the process. Next, the system swaps out dirty pages of a user context for the process to a storage device which is accessible by both the source computer system and the target computer system and transfers the checkpoint to the target computer system. The system then loads the kernel state contained in the checkpoint into a skeleton process on the target computer system. Next, the system swaps in portions of the user context for the process from the storage device to the target computer system and resumes execution of the process on the target computer system.

Abstract: A memory dump program boot method includes the steps of defining, in non-volatile variables that are managed by a boot firmware of a computer system, boot information of a plurality of stand-alone dump programs that are installed in the computer system, and a table variable indicating a corresponding relationship of the plurality of stand-alone dump programs and a plurality of operating systems, specifying the boot information of a corresponding one of the plurality of stand-alone dump programs from the table variables when the boot firmware boots an arbitrary one of the plurality of operating systems, and writing information indicating the specified boot information in the non-volatile variables that are referred to when executing a stand-alone dump, and booting the corresponding one of the plurality of stand-alone dump programs when a booting of the stand-alone dump is instructed, by checking existence of variables that are referred to when executing the stand-alone dump and referring to information of the

Abstract: The timing of one or more checkpoints that are recorded during execution of a computer process may be controlled based at least in part on the amount of one or more computer resources that are being used by the computer process. Related programs, systems and processes are also set forth.

Abstract: A non-hardened processor is made fault tolerant to SEUs and SEFIs. A processor is provided utilizing time redundancy to detect and respond to SEUs. Comparison circuitry is provided in a radiation hardened module to provide special redundancy with the need to run additional processors. Additionally, a hardened SEFI circuit is provided to periodically send a signal to the process which, in the case of a processor not in the SEFI state, initiates production by the processor of a “correct” response. If the correct response is not received within a particular time window, the SEFI circuit initiates progressively severe actions until a reset is achieved.

Abstract: This method is an error correction method such that, when an error is detected in a CPU with pipeline struct, a content of a register file is restored by a delayed register file which holds an execute completion state of an [Instruction N] correctly executed before this error, and a rollback control that re-executes an instruction from the [Instruction N+1] which is the next instruction of the [Instruction N] is performed. The method collects a parity check result of arbitrary Flip-Flops existing inside the CPU, and detects an error. As a result, the content of the register file is restored into the instruction execute completion state preceding to the instruction range likely to malfunction by the error, and the instruction can be roll backed from the beginning of the instruction range likely having malfunctioned by the error.

Abstract: A new method for the detection and correction of environmentally induced functional interrupts (or “hangs”) induced in computers or microprocessors caused by external sources of single event upsets (SEU) which propagate into the internal control functions, or circuits, of the microprocessor. This method is named Hardened Core (or H-Core) and is based upon the addition of an environmentally hardened circuit added into the computer system and connected to the microprocessor to provide monitoring and interrupt or reset to the microprocessor when a functional interrupt occurs. The Hardened Core method can be combined with another method for the detection and correction of single bit errors or faults induced in a computer or microprocessor caused by external sources SEUs.

Abstract: A method for synchronizing data utilized in a redundant, closed-loop feedback control system is disclosed. In an exemplary embodiment, the method includes configuring a plurality of control nodes within the control system, with each of the plurality of control nodes transmitting and receiving data through a common communication bus. At each of the plurality of control nodes during a given control loop time T=N, the receipt of externally generated data with respect to each control node is verified, the externally generated data having been generated during a preceding control loop time T=N?1. At each of the plurality of control nodes during the given control loop time T=N, output control data is calculated using the externally generated data. During the given control loop time T=N, the calculated output control data from each individual control node is further transmitted over the communication bus to be later utilized by other control nodes during a subsequent control loop time T=N+1.

Abstract: The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among address banks that store memory addresses. Non-trial and error algorithms and techniques determine the number of addresses and the number of identical least significant bit (LSB) values that can share the same physical memory location. By sharing physical locations for identical LSB values, circuit hardware on a memory device (including fusible links and compare circuitry) is reduced. Thus, less die area is needed to provide the same degree of redundancy.

Abstract: The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among address banks that store memory addresses. Non-trial and error algorithms and techniques determine the number of addresses and the number of identical least significant bit (LSB) values that can share the same physical memory location. By sharing physical locations for identical LSB values, circuit hardware on a memory device (including fusible links and compare circuitry) is reduced. Thus, less die area is needed to provide the same degree of redundancy.

Abstract: The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among address banks that store memory addresses. Non-trial and error algorithms and techniques determine the number of addresses and the number of identical least significant bit (LSB) values that can share the same physical memory location. By sharing physical locations for identical LSB values, circuit hardware on a memory device (including fusible links and compare circuitry) is reduced. Thus, less die area is needed to provide the same degree of redundancy.

Abstract: Methods and systems for replaying arbitrary system executions are disclosed. A system includes a storage element, a memory hierarchy and a processor. The memory hierarchy is coupled to the storage element. The processor is coupled to the memory hierarchy. The processor executes instructions from the memory hierarchy. A replay handler is loaded into the memory hierarchy. The replay handler is executed for replaying at least one execution. In another embodiment, a method for replaying executions is disclosed. Normal execution of a processor is interrupted. A replay/restart kernel is loaded. At least one execution is replayed. Normal execution of the processor is resumed.

Abstract: The number of fusible links and other circuit components required to provide memory cell redundancy are reduced by sharing physical memory locations among address banks that store memory addresses. Non-trial and error algorithms and techniques determine the number of addresses and the number of identical least significant bit (LSB) values that can share the same physical memory location. By sharing physical locations for identical LSB values, circuit hardware on a memory device (including fusible links and compare circuitry) is reduced. Thus, less die area is needed to provide the same degree of redundancy.

Abstract: In order to reproduce the past operations of a medical system, a reproduction test service apparatus stores a plurality of past log files directly or indirectly supplied from the medical system in a log file storage unit and reproduces the past operations of the medical system on a pseudo X-ray CT system in accordance with the stored log files.

Abstract: An exception handling system and method for PC-mapped systems. A support library containing language-independent functions is used to raise exceptions. These functions then use language-dependent callback functions to make inquiries about the stack frames built by the language-dependent code, and to further make callbacks to language-dependent functions to clean up those stack frames. The support library works its way up the function call stack from where an exception was issued, searching for function frames that are interested in the exception. An unwind phase is begun when a function frame that is interested in the exception is found. In the unwind phase, the unwinder attempts to unwind the stack up to the interested frame, restoring callee-saved register values, and other pertinent processor-specific information, such as the stack pointer, and frame register. The unwinder then transfers control to the handler code specified by the interested function.

Abstract: A method and apparatus for trace data alignment for trace data generated during differing instruction pipeline stages selectively delays write data, memory access address and memory access control data zero, one or two pipeline stages dependent upon the memory access control data. Program counter data delayed by one clock cycle is delayed one pipeline stage if the next instruction is a new instruction. Program counter control data is also delayed one pipeline stage. The write data, memory access address, memory access control data, program counter data and program counter control data are further delayed a number of pipeline stages to align with read data. The program counter data holds if the pipeline is stalled. The write data, memory access address, memory access control data, program counter data and program counter control data holds in the multistage pipeline delay register if the pipeline is stalled.

Abstract: Retrying processing in access of data having different properties required such as reliability and real time property of the access is optimized. In a magnetic disk apparatus connected to a host computer 10 through a connection interface and including a magnetic disk controller and a magnetic disk, the magnetic disk controller includes a retrying table in which an area address, an area size, a retrying limit value and the like are set for each of a plurality of storage areas A, B and the like of the magnetic disk and the retrying limit value set in the retrying table from the host computer is used to optimize the retrying processing for data having different reliability or real time property of access such as management data and image/audio data stored in each of the storage areas A, B and the like individually.

Abstract: The invention provides a method and system for persistent and reliable delivery of event messages. Those parts of the system responsible for delivering event messages are able to persistently maintain those event messages until the intended recipient of the event message confirms delivery of those event messages. Those parts of the system responsible for recovering from system crashes and other system errors are able to persistently maintain those event messages until delivery, even after recovery from system crashes or other system errors. The system includes a set of event message producers, and maintains an event-indication queue of those event messages provided by the event producers using a set of pre-allocated resources. An event-distribution engine distributes event messages to intended recipients and, after having received confirmation that the event messages were received, removes them from the event-indication queue.

Abstract: Trace data is aligned in a processor having an instruction pipeline by delaying write data and read data a predetermined number of clock cycles, selectively swapping both most significant write data and read data with least significant write data and read dependent upon memory access control data. The write and read data pass normally for even memory bank accesses and are swapped for odd memory bank accesses. Memory access control data, program counter data and program counter control data are similarly delayed. At least the read data and optionally all the data are held upon a pipeline stall.

Abstract: A procedure for temporally isolating an environmentally dependent integrated circuit fault includes the steps of determining a marginally failing and a minimally passing environmental condition corresponding to the fault; identifying a clock cycle Tmax at which the fault was first detected; determining a candidate clock cycle at which the fault may have occurred; and iteratively a) applying test pattern subsets from an initial clock cycle through the candidate clock cycle under the marginally failing environmental condition; b) applying remaining test patterns under the minimally passing environmental condition; and c) adjusting the candidate clock cycle based upon whether the fault occurred during test pattern subset application up through the candidate clock cycle under the marginally failing environmental condition. Candidate clock cycle adjustment in accordance with a binary search technique enables determination of an exact clock cycle at which the fault occurred in a maximum of Log2 (Tmax+1) iterations.

Abstract: A method of maintaining a hierarchy of application objects commences with the automatic detection of the exit of a process of a child application object in an unexpected manner. Responsive to the detected exit, a grandchild application object, launched by the child application object, is automatically terminated. An attempt is then made to restart the child application object. The outcome of the restart of the child application object is reported to a parent application object that launched the child application object.

Abstract: Persistent components are provided across both process and server failures, without the application programmer needing take actions for component recoverability. Application interactions with a stateful component are transparently intercepted and stably logged to persistent storage. A “virtual” component isolates an application from component failures, permitting the mapping of a component to an arbitrary “physical” component. Component failures are detected and masked from the application. A virtual component is re-mapped to a new physical component, and the operations required to recreate a component and reinstall state up to the point of the last logged interaction is replayed from the log automatically.

Abstract: Systems and methods for transient error recovery in pipelined reduced instruction set computer (RISC) processors prevent state changes based on the execution of an instruction until the execution of the instruction is validated. If a transient fault occurs causing an error to appear in an instruction execution, the instruction is retrieved using an instruction fetch address associated with that instruction and is stored in a pipeline history cache. The RISC processor pipeline is then restarted with that instruction. The validation of the execution of an instruction may take place in the execution stage, though processors with high clock frequencies may include a separate validate stage in the pipeline so that there is adequate time to validate the execution of the instruction without having to decrease the clock frequency.

Abstract: A processor is provided that implements a replay mechanism to recover from soft errors. The processor includes a protected execution unit, a check unit to detect errors in results generated by the protected execution unit, and a replay unit to track selected instructions issued to the protected execution unit. When the check unit detects an error, it triggers the replay unit to reissue the selected instructions to the protected execution unit. One embodiment of the replay unit provides an instruction buffer that includes pointers to track issue and retirement status of in-flight instructions. When the check unit indicates an error, the replay unit resets a pointer to reissue the instruction for which the error was detected.

Abstract: The present invention relates to a method and system for efficiently identifying errant processes in a computer system using an operating system (OS) error recovery method that identifies if the error caused by the errant process can be recovered and, if so, can recover from the error. The method and system of the present invention operates after standard Error Correcting Code (ECC) and parity check bit methods and systems are unsuccessful in recovering from the error In accordance with an embodiment of the present invention, the method and system includes detecting an error during instruction execution, storing a physical address of an errant process that caused the error, and storing an execution instruction pointer (IP) in an interruption instruction pointer (IIP).