Abstract: The microcomputer has an instruction memory interface that applies instructions to an instruction execution unit. In a normal state instructions are obtained from instruction memory under control of a normal program counter. In a test state a same source of an instruction is used cyclically to apply a same instruction information from a test instruction memory. Normal addressing is suppressed in the test state, so that the same instruction is executed repeatedly independent of normal program flow.

Abstract: The invention relates to a method, apparatus and computer program for reducing the number of data elements checkpointed in a system having at least one data store where operations on said at least one data store are recorded in a log. A point in the log is recorded. The oldest data element in each of the least one data store is determined and it is then determined for each of the at least one data store whether a logged representation of the data store's oldest data element is more recent than the point recorded. Responsive to determining that a data store's logged representation is more recent than the point recorded, it is realised that it is not necessary to force data elements from that data store to disk if the point recorded is made the point of restart for that data store.

Abstract: A method and system for improving data migration from source data stripes to destination stripes in a Redundant Array of Independent Drives (RAID) logical drive migration (LDM). The invention describes a procedure for checkpointing data migrations, so that if the system should fail in the middle of the LDM, the computer can resume the LDM from the last checkpointed destination stripes, thus ensuring accurate tracking of data location. Further, the invention also provides the capability of properly checkpointing a data write to a stripe according to whether or not the stripe unit has been migrated previously.

Abstract: One embodiment of the present invention provides a system that improves reliability in a compute processor by re-executing instructions. During operation, the system issues an instruction to an execution unit within the computer processor. The execution unit subsequently executes the instruction to produce a first result. If an idle execution slot becomes available, the system reissues the instruction to the execution unit, which causes the instruction to be executed a second time to produce a second result. The system then compares the first result with the second result. If the first result is not identical to the second result, the system flags an error.

Abstract: A system and method for error handling and recovery in a content distribution system is described in which errors corresponding to failed file operations (e.g., file transfer errors, file delete errors) are placed in an error queue. Error analysis logic reads the errors from the error queue and makes a determination as to whether the file operation errors are recoverable errors based on an error recovery policy. If the error analysis logic determines that recovery is possible, then one or more error recovery procedures are invoked. The procedures may be specific to the content delivery system (e.g., “Server X was down on 1/20 between 10:20 and 11:00 AM”), or may be more general (e.g., “attempt file transfers 5 times before quitting”). If it is determined that an error is not automatically recoverable, then the error is included in an error report.

Abstract: Disclosed is a method and system for handling inline recovery from speculatively executed instructions. Each register may be provided with an E-tag, that, when set, indicates an exception occurred in the generation of the value stored in its register, and an R-tag, which is used to manage data flow dependencies in recovery mode. Recovery is performed by re-executing speculatively those set of speculative instructions that are data flow dependent upon a first excepting speculative instruction. The disclosed invention provides an architecture and method for efficient exception handling when combining control speculation, data speculation and predication, thereby resulting in substantially enhanced instruction level parallelism.

Abstract: A processor is provided that implements a replay mechanism to recover from soft errors. The processor includes a protected execution unit, a check unit to detect errors in results generated by the protected execution unit, and a replay unit to track selected instructions issued to the protected execution unit. When the check unit detects an error, it triggers the replay unit to reissue the selected instructions to the protected execution unit. One embodiment of the replay unit provides an instruction buffer that includes pointers to track issue and retirement status of in-flight instructions. When the check unit indicates an error, the replay unit resets a pointer to reissue the instruction for which the error was detected.

Abstract: Retrying processing in access of data having different properties required such as reliability and real time property of the access is optimized. In a magnetic disk apparatus connected to a host computer 10 through a connection interface and including a magnetic disk controller and a magnetic disk, the magnetic disk controller includes a retrying table in which an area address, an area size, a retrying limit value and the like are set for each of a plurality of storage areas A, B and the like of the magnetic disk and the retrying limit value set in the retrying table from the host computer is used to optimize the retrying processing for data having different reliability or real time property of access such as management data and image/audio data stored in each of the storage areas A, B and the like individually.

Abstract: A method and apparatus for handling errors that deadlock a CPU by first attempting to resolve the deadlock without issuing a bus error and without restarting the CPU. If the deadlock cannot be resolved without issuing a bus error, then a bus error is issued and the CPU attempts to restart. The method involves comparing the number of clock cycles taken to execute an instruction to a designated abort value. When an instruction has taken the full abort value of cycles but has not retired, a machine-check abort (MCA) is issued to attempt to resolve the deadlock. The method also involves comparing the number of clock cycles to a larger bus error value. If the MCA does not break the deadlock within a certain period—i.e., before the bus error value is reached—then a bus error is issued and the machine attempts to reset.

Abstract: Apparatus (5) and method for processing data in response to a sequence of program instructions including a primary pipelined processing unit (40) for performing data processing, the primary pipelined processing unit being responsive to a cancellation condition such as an abort to cancel processing of a partially completed program instruction. The apparatus and method comprising a pseudo instruction generator (30) to generate a pseudo instruction to a fix-up pipelined processing unit (50) in response to a program instruction (LDM, STM) that can be subject to cancellation, the pseudo instruction controlling the fix-up pipelined processing unit to produce a state in which the partially completed program instruction may be re-executed at a later time.

Abstract: Audit Trail recovery is enhanced by including addresses of immediately prior periodic saves of all active or open Steps or transactions in each new period save area. Reduced cost in main memory usage and on-the-fly processing to accomplish audit trail format that enhances recovery time results from ability to immediately address next prior period save data once a last periodic save is found in reading back the audit trail. Reading back the audit trail to find the last periodic save can be avoided too by directly addressing the last periodic save in preferred embodiments since the computer system will in all events temporarily maintain a record of the address of the last periodic save to record the next time a periodic save is to be made, so this temporarily maintained record can be accessed and used to jump directly to the last periodic save address on the audit trail.

Abstract: Method and apparatus for copying, transferring, backing up and restoring data are disclosed. The data can be copied, backed up or restored in segments sizes larger than the data blocks which comprise a logical object. In some embodiments, the segment can correspond to a track of a primary storage device and the data blocks to a fixed size block. In some instances, copying, storage and transfer of the segments which include multiple data blocks can result in transfer of a data block not in a logical object.

Abstract: An error recovery mechanism for an interconnect is disclosed. A data processing system includes a bus connected between a bus master and a bus slave. In response to a parity error occurring on the bus, the bus slave issues a bus parity error response to the bus master via the bus. After waiting for a predetermined number of bus cycles to allow the bus to idle, the bus master then issues a RESTART bus command packet to the bus slave via the bus to clear the parity error. If the RESTART bus command packet is received correctly, the slave bus will remove the parity error response such that normal bus communication may resume.

Abstract: A method for supporting recovery processing from a failed storage device in a computer system which also includes a processing unit. The processing unit executes a batch job including plural jobs. Transition history information which includes information of executed jobs and an operated on data-set is obtained during execution of the batch job. When performing recovery processing upon detection of a failed storage device, the transition history information is inspected. Jobs that have performed an output operation to the failed storage device are extracted as direct re-execution jobs. Further, jobs on which a data-set operation is effected by the direct re-execution jobs are extracted as indirect re-execution jobs. Still further, a data-set and generation of a data-set to be restored, deletion of a data-set, and a method and timing thereof are determined. Then, information used for supporting the recovery operation is edited and the edited information is output.

Abstract: A process which stores an indication of a next instruction in a sequence of instructions which is to be executed whenever during execution of instructions of the sequence it is apparent that state of the process is consistent, and refers to the stored indication to determine an instruction at which to begin re-execution of the sequence after executing a fault handler initiated by an interrupt to the sequence.

Abstract: Method and system for reporting events stored in an event log of an electronic device to requesting remote computers. An event reporting mechanism within the electronic device inserts special watermark events into the event log in order to keep track of particular reporting threads. The reporting thread may be associated with a particular type of logged event and a particular requesting remote computer. Watermark events allow logged events to be reported without duplication and with minimal chance of omission. Implementation of the watermark-based event reporting technique does not require extensive changes to, or reformatting of, non-volatile memory-based events logs, and only minimal changes to the hardware circuitry or firmware that implements the event reporting mechanism within an electronic device.

Abstract: Disclosed is a device adapter for controlling devices in a network comprising computer processor nodes and one or more devices, the device adapter having means for determining whether or not a device state has changed after a failure. Responsive to a determination that the device state has not changed, the adapter communicates with other device adapters in the network to reestablish permissions before resubmitting I/O requests. Responsive to a determination that the device state has changed after a failure, the adapter reintegrates itself with the other device adapters in the network before reprocessing work as necessary.

Abstract: Repositioning within an input/output device is accomplished without any knowledge of where the input/output device is currently positioned. The input/output device is repositioned to a predetermined position, in order for a program to be retried. The predetermined position is determined from a previously executed program. The previously executed program is scanned looking for commands. For each command found, a position identifier is adjusted based upon the type of command. When the scan and adjustments are complete, the position identifier represents the predetermined position used for repositioning the input/output device.

Abstract: Customer-service tasks are performed in a noninvasive manner by relying on automatic methods for (a) capturing the state of the operating domain and (b) automatically communicating this state as well as a description of the circumstances that lead to activation of the process to a remote service machine via an electronic network. Network-based customer-service for software support includes an automatic mechanism which initiates the product support process. This automatic mechanism may optionally be augmented by a manual mechanism for initiating the support process. The process captures the operating environment in sufficient detail so as to enable its re-creation in part or in whole on a separate machine. Archived data is transmitted to an off-site storage device, and when this data is received, notification is transmitted to customer-support personnel.

Abstract: Systems and methods for transient error recovery in pipelined reduced instruction set computer (RISC) processors prevent state changes based on the execution of an instruction until the execution of the instruction is validated. If a transient fault occurs causing an error to appear in an instruction execution, the instruction is retrieved using an instruction fetch address associated with that instruction and is stored in a pipeline history cache. The RISC processor pipeline is then restarted with that instruction. The validation of the execution of an instruction may take place in the execution stage, though processors with high clock frequencies may include a separate validate stage in the pipeline so that there is adequate time to validate the execution of the instruction without having to decrease the clock frequency.

Abstract: Systems and methods for transient error recovery in pipelined reduced instruction set computer (RISC) processors prevent state changes based on the execution of an instruction until the execution of the instruction is validated. If a transient fault occurs causing an error to appear in an instruction execution, the instruction is retrieved using an instruction fetch address associated with that instruction and is stored in a pipeline history cache. The RISC processor pipeline is then restarted with that instruction. The validation of the execution of an instruction may take place in the execution stage, though processors with high clock frequencies may include a separate validate stage in the pipeline so that there is adequate time to validate the execution of the instruction without having to decrease the clock frequency.

Abstract: A mechanism for handling processing errors in a computer system. The mechanism includes a first means for processing a stream of instructions, second means for detecting an error caused by a timing dependant defect and occurring during processing of the instruction by the first means and third means for varying the instruction processing cycle time of the first means in response to the detection of the error by the second means, and for causing the second means to retry at least a portion of the instruction subsequent to the varying. In a preferred embodiment, the mechanism uses the variable frequency oscillator, controlled by recovery code, to increase the system clock cycle time by a specified time (Textend) following what has been determined to be a critical fail and after normal retry has been unsuccessful. The increased cycle time extends the net slack and, thereby, provides tolerance to certain AC (path delay) defects which have developed in any cycle time dependant latch to latch segment.

Abstract: A mechanism for handling processing errors in a computer system. The mechanism includes a first means for processing a stream of instructions, second means for detecting an error caused by a timing dependant defect and occurring during processing of the instruction by the first means and third means for varying the instruction processing cycle time of the first means in response to the detection of the error by the second means, and for causing the second means to retry at least a portion of the instruction subsequent to the varying. In a preferred embodiment, the mechanism uses the variable frequency oscillator, controlled by recovery code, to increase the system clock cycle time by a specified time (Textend) following what has been determined to be a critical fail and after normal retry has been unsuccessful. The increased cycle time extends the net slack and, thereby, provides tolerance to certain AC (path delay) defects which have developed in any cycle time dependant latch to latch segment.

Abstract: A method and apparatus for processing call data. A first server in active mode replicates call data to a second server in standby mode. The first server is monitored for a fault condition by the second server, as well as other network devices. If a fault condition is detected, the first server is switched to standby mode and the second server to active mode.

Abstract: A computer system and a parallel execution control method thereof. A job execution managing module includes a job control statement interpreting module for deciding by interpretation of job control statements whether jobs registered by a job registration processing module are capable of undergoing parallel execution. For the jobs susceptible to the parallel execution, the job execution managing module commands reregistration of such job to the job registration processing module. The job control statement interpreting module further decides by interpreting the control statement whether execution of individual job steps of registered jobs are to be skipped or not. The job step decided to be skipped is inhibited from execution by a step execution control module. Time taken for execution of jobs and job steps can be shortened.