Built-in Hardware For Diagnosing Or Testing Within-system Component (e.g., Microprocessor Test Mode Circuit, Scan Path) Patents (Class 714/30)
  • Patent number: 10971243
    Abstract: A BIST engine configured to store a per pattern based fail status during memory BIST run and related processes thereof are provided. The method includes testing a plurality of patterns in at least one memory device and determining which of the plurality of patterns has detected a fail during execution of each pattern. The method further includes storing a per pattern based fail status of each of the detected failed patterns.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: April 6, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Aravindan J. Busi, John R. Goss, Paul J. Grzymkowski, Krishnendu Mondal, Kiran K. Narayan, Michael R. Ouellette, Michael A. Ziegerhofer
  • Patent number: 10942213
    Abstract: The device for testing a motherboard includes a power adapter, a first DC-DC converter, and a microcontroller. The power adapter converts an AC input voltage to a DC supply voltage. The DC-DC converter converts the DC supply voltage to a DC voltage at a channel coupled to the motherboard, and adjusts a voltage level of the DC voltage in response to a control signal. The DC-DC converter is enabled according to an enable signal. The microcontroller is configured to provide the control signal and the enable signal, and to determine whether a power on/off operation of the motherboard is normal. The microcontroller is configured to perform a test procedure on the motherboard to obtain a workable voltage range of the motherboard. The voltage level of the DC voltage in the test procedure is dynamically adjusted within a predetermined range around a nominal voltage value of the DC voltage.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: March 9, 2021
    Assignee: DFI Inc.
    Inventors: Chia-yi Chang, Chien-Ming Yu, Jheng-Rong Cai
  • Patent number: 10935601
    Abstract: A falling edge controller includes a controller having an inverted TCK (Test Clock) input, a TMS (Test Mode Select) input, a shift register control output, an update register control output, and a shift output; a shift register having a TDI (Test Data In) input, a shift register control input coupled to the shift register control output, address inputs, a select input, address and select outputs, and a TDO (Test Data Out) output; an update register having address and select inputs coupled to the address and select outputs, an update register control input coupled to the update register control output, address outputs coupled to the address inputs, and a select output coupled to the select input; and address circuitry having address inputs coupled to the address outputs, and having an enable output.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: March 2, 2021
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10902933
    Abstract: In various examples, a test system is provided for executing built-in-self-test (BIST) according to JTAG and IEEE 1500 on chips deployed in-field. Hardware and software selectively connect onto the IEEE 1500 serial interface for running BIST while the chip is being used in deployment—such as in an autonomous vehicle. In addition to providing a mechanism to connect onto the serial interface, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making BIST possible in deployment. Furthermore, some embodiments include components configured to store functional states of clocks, power, and input/output prior to running BIST, which permits restoration of the functional states after the BIST.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: January 26, 2021
    Assignee: NVIDIA Corporation
    Inventors: Anitha Kalva, Jue Wu
  • Patent number: 10896139
    Abstract: The present disclosure describes technologies and techniques for use by a data storage controller (such as a non-volatile memory (NVM) controller) to emulate hardware registers in software and/or firmware. In illustrative examples, an arbiter of the NVM controller arbitrates inbound register accesses from a host. Regular register accesses from the host are directed by the arbiter along a regular hardware read path within the NVM controller to physical memory registers. Other transactions (e.g. writes to, or reads from, an undefined or reserved address space) are instead directed by the arbiter to the processor of the NVM controller for handling by software running on the processor (and/or by firmware). In this manner, new hardware registers added to an NVM standard may be implemented by software and/or firmware rather than hardware. Hence, the NVM controller may comply with new standard requirements without changing the hardware. NVMe examples are provided.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: January 19, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Shay Benisty, Elkana Richter, Alexey Martynenko
  • Patent number: 10891410
    Abstract: In an example embodiment, a computer-implemented method is provided for receiving an integrated circuit design, wherein the integrated circuit design comprises at least one position in violation of one or more design rules associated with the integrated design, identifying one or more design patterns at the at least one violating position, generating one or more pattern graphs for the one or more design patterns, extracting a system on chip design for transformation into a block graph, and. comparing the block graph with each of the one or more pattern graphs to determine whether the at least one violating position is cleared. In circumstances where a match is found between the block graph and the each of the one or more pattern graphs, the computer-implemented method further comprises changing the one or more design patterns and repeating the step of comparing until there is no further match found.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: January 12, 2021
    Assignee: Synopsys, Inc.
    Inventors: Chin-Hsiung Hsu, Philip Hui-Yuh Tai, Sheng-Wei Yang, Guo-Ting Wang
  • Patent number: 10885068
    Abstract: The present invention extends to methods, systems, and computer program products for consolidating information from different signals into an event. Aspects of the invention used a multiphase approach to consolidating information from different signals into (e.g., deduplicating) an event. Detected events are held in the event holding cache for some amount of time after detection in accordance event holding criteria. As events are detected, an information consolidator compares currently detected events to previously cached events. Events determined to be the same event are grouped into an event group. When holding criteria expire for an event in the event group, the event group is published to one or more entities. As such, each new detection of the event does not trigger a corresponding new notification. Different portions of content from the same signal can also be monitored to reduce duplicate detections based on different content types in the same signal.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: January 5, 2021
    Assignee: safeXai, Inc.
    Inventors: Christian Gratton, Damien Patton, Rish Mehta, K W Justin Leung
  • Patent number: 10877833
    Abstract: Processing circuitry (85) supports a vector atomic memory update instruction identifying an address vector, for triggering at least one atomic memory update operation for performing an atomic memory update to a memory location having an address determined based on a corresponding active data element of the address vector. When a fault condition is determined for the address determined using a given faulting active data element of the address vector, atomic memory update operations for that element and any subsequent element in a predetermined sequence are suppressed. If the faulting element is the first active data element in the sequence, a fault handling response is triggered, while otherwise the fault handling response is suppressed and status information is stored indicating which element is the faulting element.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: December 29, 2020
    Assignee: ARM Limited
    Inventor: Nigel John Stephens
  • Patent number: 10824493
    Abstract: A mechanism for disambiguation of error logging during a warm reset is disclosed. A system agent detects an error occurring during bootstrapping of a processor package. The error occurs prior to initiation of a machine check system. A wide pulse event is initiated to signal a wide pulse register to store a wide pulse time stamp counter value. The wide pulse event also signals a lap register to store a lap time stamp counter value. The wide pulse register maintains the wide pulse time stamp counter value during a warm reset, and the lap register clears the lap time stamp counter value during the warm reset. The system agent obtains the wide pulse time stamp counter value and the lap time stamp counter value after bootstrapping is complete to determine an order of occurrence of the error relative to the warm reset.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: November 3, 2020
    Assignee: Intel Corporation
    Inventors: Subhankar Panda, Gaurav Porwal
  • Patent number: 10783299
    Abstract: An exemplary system, method, and computer-accessible medium may be provided, which may include, for example, receiving a design a memory including a plurality MBIST logic paths and a plurality of non-MBIST logic paths, determining particular non-MBIST logic path(s) of the non-MBIST logic paths to deactivate, and deactivating only the particular non-MBIST logic path(s). The particular non-MBIST logic path(s) may be deactivated using a clock signal. A simulation on the memory may be performed while the particular non-MBIST logic path(s) may be deactivated. The particular non-MBIST logic path(s) may be reactivated after the simulation has been performed. The deactivating the particular non-MBIST logic path(s) may include forcing all flip flops in the particular non-MBIST logic path(s) to a known state.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: September 22, 2020
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Steven Lee Gregor, Puneet Arora, Norman Robert Card
  • Patent number: 10773454
    Abstract: A 3D printer is provided that includes a print head having an extruder (stepper) motor positioned to feed a filament into a heater, a X and Y print head positioning system configured to move the print head relative to a print surface, and a stepper driver operable to control the operation of the extruder motor. In one aspect, the 3D printer further includes a sensor module having a feed rate sensor positioned to detect a feed rate of the filament, and a control system programmed to: receive signals from the sensor module that are indicative of the feed rate of the filament, and control the operation of the stepper driver based on the signals from the sensor module. In a further aspect, the X and Y positioning system includes X and Y positioning motors and X and Y encoders positioned to sense the rotation of said positioning motors.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: September 15, 2020
    Inventor: Robert Ladanyi
  • Patent number: 10761139
    Abstract: A semiconductor apparatus includes a storage circuit, a processing circuit that performs processing using data stored in the storage circuit and writes data into the storage circuit as the processing is performed, a scan test circuit that executes a scan test on the processing circuit when the processing circuit does not perform processing, and an inhibit circuit that inhibits writing of data from the processing circuit to the storage circuit when the scan test on the processing circuit is executed.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: September 1, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Shinichi Shibahara, Daisuke Kawakami, Yutaka Igaku
  • Patent number: 10754723
    Abstract: In some embodiments, a processing system includes at least one hardware block configured to change operation as a function of configuration data, a non-volatile memory including the configuration data for the at least one hardware block, and a configuration module configured to read the configuration data from the non-volatile memory and provide the configuration data read from the non-volatile memory to the at least one hardware block. The configuration module is configured to: receive mode configuration data; read the configuration data from the non-volatile memory; test whether the configuration data contain errors by verifying whether the configuration data are corrupted and/or invalid; and activate a normal operation mode or an error operation mode based on whether the configuration data contain or do not contain errors.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: August 25, 2020
    Assignees: STMICROELECTRONICS APPLICATION GMBH, STMICROELECTRONICS S.R.L.
    Inventors: Roberto Colombo, Nicolas Bernard Grossier, Roberta Vittimani
  • Patent number: 10746790
    Abstract: Embodiments of the invention are directed to a built-in self-test system for an electronic circuit. The system includes a memory having two or more base seeds stored thereon. The system further includes seed generation logic configured to generate, based at least in part on the two or more base seeds, a plurality of generated seeds. The generated seeds can be constructed from the base seeds such that each of the generated seeds encodes a test pattern that satisfies a functional constraint. A finite state machine is configured to generate, based on the plurality of generated seeds, a sequence of constrained pseudorandom test patterns. A test controller is operable to place the electronic circuit into a test mode based on the constrained pseudorandom test pattern.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: August 18, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Alejandro Alberto Cook Lobo, Thomas Gentner, Daniel Kiss, Jens Kuenzer
  • Patent number: 10742198
    Abstract: A semiconductor apparatus including a pipe latch is provided. The pipe latch includes a first latch unit, a second latch unit and an output unit. The first latch unit configured to store an input signal into a first latch node based on a first input control signal. The second latch unit configured to store the signal stored in the first latch node into a second latch node based on a second input control signal. The output unit configured to output the signal stored in the second latch node as output signal based on an output control signal.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: August 11, 2020
    Assignee: SK hynix Inc.
    Inventor: Hyun Seung Kim
  • Patent number: 10732847
    Abstract: A non-volatile memory system may include a non-volatile memory die storing a requested data set that a host requests to be read. In response to the host request, a copy of a data set may be retrieved from the non-volatile memory die without performing error correction on an entry identifying a physical address where the data set is stored. If the data set copy matches the requested data set, the data set copy may be sent to the host. If the data set copy does not match the requested data set, then error correction may be performed on a copy of the entry to identify the correct physical address where the requested data set is stored. A copy of the requested data set may then be retrieved and sent to the host.
    Type: Grant
    Filed: January 30, 2019
    Date of Patent: August 4, 2020
    Assignee: SanDisk Technologies LLC
    Inventors: Alexander Bazarsky, Grishma Shah, Idan Alrod, Eran Sharon
  • Patent number: 10732869
    Abstract: Non-limiting examples of the present disclosure relate to execution of in-situ manufacturing for a data storage device. In-situ manufacturing is on-location configuration of a data storage device within an operational environment in which a data storage device is being deployed. In-situ manufacturing occurs at any point after a data storage device is shipped from a manufacturing plant or factory. When an operational environment of the data storage device is known, parameters of the data storage device can be configured (or re-configured) on-location within an operational environment to optimize capacity management as well as performance of the data storage device.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: August 4, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Austin Striegel, Timothy Lieber
  • Patent number: 10726177
    Abstract: A system on a chip (SoC) includes a plurality of processing cores and a stream switch coupled to two or more of the plurality of processing cores. The stream switch includes a plurality of N multibit input ports, wherein N is a first integer. a plurality of M multibit output ports, wherein M is a second integer, and a plurality of M multibit stream links dedicated to respective output ports of the plurality of M multibit output ports. The M multibit stream links are reconfigurably coupleable at run time to a selectable number of the N multibit input ports, wherein the selectable number is an integer between zero and N.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: July 28, 2020
    Assignees: STMICROELECTRONICS S.R.L., STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Thomas Boesch, Giuseppe Desoli
  • Patent number: 10706949
    Abstract: A storage device includes: a first disabling unit configured to output write enable signals without change when at least two write addresses of a plurality of write addresses for which write enable signals are enabled and held by a first holding unit do not match; a second holding unit configured to hold sets of the plurality of write addresses held by the first holding unit and the plurality of write enable signals output by the first disabling unit; a second disabling unit configured to output one write enable signal of the plurality of write enable signals held by the second holding unit without change in a test mode; and a third holding unit configured to write data in accordance with sets of the plurality of write addresses held by the second holding unit and the plurality of write addresses output by the second disabling unit.
    Type: Grant
    Filed: September 4, 2018
    Date of Patent: July 7, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Soichiro Nakamura, Tomohiro Tanaka
  • Patent number: 10690720
    Abstract: An IC includes an IEEE 1149.1 standard test access port (TAP) interface and an additional Off-Chip TAP interface. The Off-Chip TAP interface connects to the TAP of another IC. The Off Chip TAP interface can be selected by a TAP Linking Module on the IC.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: June 23, 2020
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10691569
    Abstract: A system for testing a data storage device includes the data storage device, an electronic device and a computer device. The electronic device includes a host device coupled to the data storage device and communicating with the data storage device via an interface logic. The computer device is coupled to the electronic device and is configured to issue a plurality of commands to test the data storage device in a test procedure. When the electronic device has been successfully started up, the computer device issues a first command to the electronic device to trigger the electronic device to enter a hibernate mode. After waiting for a first predetermined period of time, the computer device issues a second command to the electronic device, so as to wake up the electronic device.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: June 23, 2020
    Assignee: Silicon Motion, Inc.
    Inventor: Po-Yi Shih
  • Patent number: 10692584
    Abstract: A BIST engine configured to store a per pattern based fail status during memory BIST run and related processes thereof are provided. The method includes testing a plurality of patterns in at least one memory device and determining which of the plurality of patterns has detected a fail during execution of each pattern. The method further includes storing a per pattern based fail status of each of the detected failed patterns.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: June 23, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Aravindan J. Busi, John R. Goss, Paul J. Grzymkowski, Krishnendu Mondal, Kiran K. Narayan, Michael R. Ouellette, Michael A. Ziegerhofer
  • Patent number: 10678680
    Abstract: Provided is a method for automatically generating a search heuristic that is optimal for a test subject program and a method of concolic testing that uses a parameterized search heuristic to yield a consistent test performance for any program.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: June 9, 2020
    Assignee: Korea University Research and Business Foundation
    Inventors: Sooyoung Cha, Seongjoon Hong, Junhee Lee, Hakjoo Oh
  • Patent number: 10678691
    Abstract: Systems, apparatuses, and methods for implementing coherence flows for dual-processing coherence and memory cache pipelines are disclosed. A dual-processing pipeline includes a coherence processing pipeline and a memory cache processing pipeline. When a transaction is issued to the dual-processing pipeline, the coherence processing pipeline performs a duplicate tag lookup in parallel with the memory cache processing pipeline performing a memory cache tag lookup for the transaction. If the duplicate tag lookup is a hit, then the coherence processing pipeline locks the matching entry, the memory cache processing pipeline discards the original transaction, and a copyback request is sent to a coherent agent identified by the matching entry. When the copyback response is received by a communication fabric, the copyback response is issued to the memory cache processing pipeline. When the copyback response passes the global ordering point, the coherence processing pipeline clears the lock on the matching entry.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: June 9, 2020
    Assignee: Apple Inc.
    Inventors: Harshavardhan Kaushikkar, Srinivasa Rangan Sridharan, Xiaoming Wang
  • Patent number: 10671466
    Abstract: Systems, apparatuses and methods may provide for receiving one or more debug communications and programming, via a bus, a set of debug registers with debug information corresponding to the one or more debug communications. Additionally, tunnel logic hardware may be instructed to transfer the debug information from the set of debug registers to one or more test access ports of an intelligent device such as a non-volatile memory storage unit having a microcontroller. In one example, if it is detected that debug permission has been granted during a boot process, a control status register may be unlocked. If, on the other hand, the debug permission is not detected during the boot process, the control status register may be locked. Accordingly, an enable bit of the control status register may be used to activate the tunnel logic hardware only if the control status register is unlocked.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: June 2, 2020
    Assignee: Intel Corporation
    Inventors: Shamanna M. Datta, Murugasamy K. Nachimuthu, Mahesh S. Natu
  • Patent number: 10664390
    Abstract: Systems, methods, and computer-readable media for optimizing the execution order of a set of test programs that includes at least one system interval dependent test program are disclosed. The optimized execution order may be determined by identifying each non-system interval dependent test program that can be executed during each instance of a system interval without impacting execution of system interval dependent test programs. The optimized execution order minimizes a total execution time of the set of test programs.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: May 26, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joseph W. Gentile, Brian D. Keuling, Anthony T. Sofia
  • Patent number: 10649029
    Abstract: Control events may be signaled to a target system having a plurality of components coupled to a scan path by using the clock and data signals of the scan path. While the clock signal is held a high logic level, two or more edge transitions are detected on the data signal. The number of edge transitions on the data signal is counted while the clock signal is held at the high logic state. A control event is determined based on the counted number of edge transitions on the data signal after the clock signal transitions to the low logic state.
    Type: Grant
    Filed: July 18, 2018
    Date of Patent: May 12, 2020
    Assignee: Texas Instruments Incorporated
    Inventor: Gary L. Swoboda
  • Patent number: 10642688
    Abstract: In geographically-distributed object storage systems that utilize erasure coding, non-intersecting sub matrices of a great encoding matrix can be utilized to erasure code data fragments of a chunk at the zone level and generate coding fragments. Accordingly, the data fragments that are stored within different zones are identical, while the coding fragments stored within the different zones are disparate. Subsequent to a multi-zone data failure, wherein it is determined that a decoding operation cannot be performed at the zone level, available fragments associated with the chunk can be collected from the zones and collectively decoded to recover the chunk. In one aspect, the fragments can be decoded by utilizing a great decoding matrix that corresponds to the great encoding matrix.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: May 5, 2020
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Mikhail Danilov, Konstantin Buinov
  • Patent number: 10639849
    Abstract: In an aspect, a 3D printer is provided and includes a print head having an extruder motor (that is a stepper motor) positioned to feed a filament into a heater, a print head positioning system configured to move the print head relative to a print surface, a stepper driver that is connected to the extruder motor and is operable to control the operation of the extruder motor, a sensor module that includes a feed rate sensor positioned to detect a rate of feed of the filament, and a control system that is programmed to: receive signals from the sensor module that are indicative of the feed rate of the filament, and control the operation of the stepper driver based on the signals from the sensor module.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: May 5, 2020
    Inventor: Robert Ladanyi
  • Patent number: 10637475
    Abstract: An extended General Purpose Input/Output (eGPIO) scheme is disclosed. In some implementations, an input/output (I/O) boundary scan cell comprises an output path to route output signals from a first voltage domain and signals from a second voltage domain to an I/O pad operating in a pad voltage domain, the output path having a first level shifter to up shift the output signals from the first voltage domain or the second voltage domain to the pad voltage domain; an input path to receive input signals from the I/O pad, the input path having a second level shifter to down shift the input signals from the pad voltage domain to the second voltage domain; and test logic to test signals in the first voltage domain and the second voltage domain.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: April 28, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Varun Jain, Brent Duckering
  • Patent number: 10628275
    Abstract: A method, apparatus, article of manufacture, and system are provided for detecting hardware faults on a multi-core integrated circuit device by executing runtime software-based self-test code concurrently on multiple processor cores to generate a first set of self-test results from a first processor core and a second set of self-test results from a second processor core; performing mutual inter-core checking of the self-test results by using the first processor core to check the second set of self-test results from the second processor core while simultaneously using the second processor core to check the first set of self-test results from the first processor core; and then using the second processor core to immediately execute a recovery mechanism for the first processor core if comparison of the first set of self-test results against reference test results indicates there is a hardware failure at the first processor core.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: April 21, 2020
    Assignee: NXP B.V.
    Inventors: Andrei S. Terechko, Gerardo H. O. Daalderop, Johannes van Doorn, Han Raaijmakers
  • Patent number: 10620260
    Abstract: An integrated circuit (IC) chip for providing a safety-critical value includes first and second processing paths. The first processing path includes a first processing element and is coupled to receive a first input signal on a first input pin and to provide a first output signal that provides the safety-critical value on an output pin. The second processing path includes a second processing element and is coupled to receive a second input signal and to provide a second output signal. The first processing path and the second processing path are independent of each other. A smart comparator on the IC chip receives the first output signal and the second output signal and initiates a remedial action responsive to a difference between the first output signal and the second output signal reaching a configurable threshold.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: April 14, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jeffrey Earl Stafford, Prasanth Viswanathan Pillai, Ashish Arvind Vanjari
  • Patent number: 10621070
    Abstract: An information processing system includes a first memory that stores information on a request for performing data processing associated with a type of the data processing, a second memory that stores information on a request for performing data processing for testing, and a plurality of circuitry that performs data processing according to the type of the data processing. The plurality of circuitry includes a first circuitry that operates in a normal mode and a second circuitry that operates in a test mode. The second circuitry starts up in the test mode to operate in the test mode if the first circuitry operates in the normal mode and transitions from the test mode to the normal mode according to a user request. In the normal mode, the circuitry acquires the information on the request for performing the data processing from the first memory and performs the data processing.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: April 14, 2020
    Assignee: Ricoh Company, Ltd.
    Inventors: Masateru Kumagai, Tadashi Honda, Kohichiroh Nishikawa, Tomoya Amikura
  • Patent number: 10614885
    Abstract: There are provided a microcontroller, a memory system having the same, and a method for operating the same. A memory system includes: a semiconductor memory performing a scanning operation on ROM data stored in a microcontroller in a test operation and outputting a result of the scanning operation as a status output signal; and a controller for determining whether an error exists in the ROM data, using the status output signal.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: April 7, 2020
    Assignee: SK hynix Inc.
    Inventors: Byoung Sung You, Seung Hyun Chung, Jae Young Lee
  • Patent number: 10606714
    Abstract: A plurality of tasks are executed on a plurality of central processing units (CPUs) of a computational device. In response to an occurrence of an event in the computational device, one or more CPUs that are executing tasks associated with an event category to which the event belongs are stopped within a first predetermined amount of time. In response to stopping the one or more CPUs, a data set indicative of a state of the computational device is collected, for at most a second predetermined amount of time.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: March 31, 2020
    Assignee: International Business Machines Corporation
    Inventors: Matthew D. Carson, Trung N. Nguyen, Louis A. Rasor, Todd C. Sorenson
  • Patent number: 10580512
    Abstract: An example of a system includes a host interface, a set of non-volatile memory cells assigned a first logical address range, and one or more control circuits coupled to the host interface and coupled to the set of non-volatile memory cells. The one or more control circuits are configured to generate debug data and send the debug data through the host interface in response to a command received through the host interface. The command is directed to a second logical address range, the second logical address range assigned exclusively for debug data.
    Type: Grant
    Filed: February 21, 2018
    Date of Patent: March 3, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Karthik Subramanian, Vinay Vijendra Kumar Lakshmi
  • Patent number: 10572299
    Abstract: An apparatus (2) has processing circuitry (6) having access to a first processing resource (20-0) and a second processing resource (20-3). A first thread can be processed using the first processing resource. In a thread mode the second processing resource (20-3) can be used to process a second thread while in a transaction mode the second processing resource (20-3) can be used to process a transaction of the first thread comprising a number of speculatively performed operations for which results are committed at the end of the transaction. By sharing resources for supporting additional threads and supporting transactions, circuit area and power consumption can be reduced.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: February 25, 2020
    Assignee: ARM Limited
    Inventors: Stephan Diestelhorst, Matthew James Horsnell, Guy Larri
  • Patent number: 10571518
    Abstract: Certain aspects of the disclosure are directed toward test control and test access configuration via two pins on an integrated circuit (IC). According to a specific example, an IC chip-based apparatus is used in connection with a controller for testing a target IC. The IC chip-based apparatus includes an event (capture) circuit configured and arranged to control logic states through which a static test configuration is selected for a given event detected in response to a clock signal and to a data signal respectively derived from the controller. A test-operation control circuit may be configured and arranged to test the target IC by selectively configuring each of the clock pin and the I/O pin of the controller for use as an analog test bus, data input to the controller or data output from the controller, and carrying out dynamic operations by communicating test signals via pins of the target IC.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: February 25, 2020
    Assignee: NXP B.V.
    Inventors: Tom Waayers, Mahmoud Abdalwahab, Willem Franciscus Slendebroek
  • Patent number: 10552289
    Abstract: The present subject matter relates to a method and system for correlation analysis of performance metrics. In one embodiment, a computing system for correlation analysis of performance metrics is described. The computing system includes a processor, and a memory which is coupled to the processor. Further, the memory comprises a profiler agent, a correlation engine, and a graphics controller. The profiler agent collects the performance metrics based on execution of a target application. The correlation engine establishes correlation between the performance metrics based on a predefined parameter. The graphics controller generates a consolidated interface of the performance metrics depicting the established correlation between the performance metrics.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: February 4, 2020
    Assignee: Tata Consultancy Services Limited
    Inventors: Ramkumar Ilangovan, Swarup Chatterjee
  • Patent number: 10553302
    Abstract: A BIST engine configured to store a per pattern based fail status during memory BIST run and related processes thereof are provided. The method includes testing a plurality of patterns in at least one memory device and determining which of the plurality of patterns has detected a fail during execution of each pattern. The method further includes storing a per pattern based fail status of each of the detected failed patterns.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: February 4, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Aravindan J. Busi, John R. Goss, Paul J. Grzymkowski, Krishnendu Mondal, Kiran K. Narayan, Michael R. Ouellette, Michael A. Ziegerhofer
  • Patent number: 10540299
    Abstract: An apparatus has processing circuitry to perform data processing in one of two or more operating states associated with different levels of privilege. At least one operating state holding element holds a state indication indicating a current operating state of the processing circuitry. In response to a transition of a reset signal from a first value to a second value for triggering a reset of the processing circuitry, the at least one operating state holding element resets the state indication to indicate a default operating state other than a most privileged operating state of the two or more operating states.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: January 21, 2020
    Assignee: ARM Limited
    Inventors: Carlo Dario Fanara, Frederic Jean Denis Arsanto, Guillaume Schon, Jocelyn Francois Orion Jaubert
  • Patent number: 10539606
    Abstract: A test control port (TCP) includes a state machine SM, an instruction register IR, data registers DRs, a gating circuit and a TDO MX. The SM inputs TCI signals and outputs control signals to the IR and to the DR. During instruction or data scans, the IR or DRs are enabled to input data from TDI and output data to the TDO MX and the top surface TDO signal. The bottom surface TCI inputs may be coupled to the top surface TCO signals via the gating circuit. The top surface TDI signal may be coupled to the bottom surface TDO signal via TDO MX. This allows concatenating or daisy-chaining the IR and DR of a TCP of a lower die with an IR and DR of a TCP of a die stacked on top of the lower die.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: January 21, 2020
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10540310
    Abstract: A programmable apparatus for executing a function is disclosed. The programmable apparatus includes a physical interface configured to be connected with an external apparatus. The programmable apparatus also includes a function logic circuit configured to execute the function on the programmable apparatus. The programmable apparatus further includes a plurality of peripheral logic circuits, each of which is configured to connect the function logic circuit with the physical interface using a respective protocol. The programmable apparatus also includes a selector circuit configured to select one from among the plurality of the peripheral logic circuits to activate.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: January 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: Yutaka Kawai, Yohichi Miwa
  • Patent number: 10539616
    Abstract: A scan data control apparatus includes a trigger circuit, a scan sequencer, a shift register, and a transmitter. The trigger circuit is configured to receive a trigger signal, detect a malfunction of a system and output a scan mode start signal and a scan mode end signal. The scan sequencer is configured to output scan enable signals corresponding to a CPU and a master to the CPU and the master. The shift register is configured to receive scan data of the CPU and the master from the CPU and the master. The transmitter is configured to receive the scan data of the CPU and the master and output the scan data to a memory.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: January 21, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung-Heon Jeong, Ho-Sung Kim, Sung-Jae Lee
  • Patent number: 10521292
    Abstract: A self-test method of a flash memory device includes: generating input data; encoding the input data to generate an error correction code; utilizing the input data and the error correction code to simulate to read a page of a flash memory of the flash memory device to generate soft information; and decoding the soft information to generate a decoding result.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: December 31, 2019
    Assignee: Silicon Motion, Inc.
    Inventor: Chen-Yu Weng
  • Patent number: 10495690
    Abstract: A circuit is for coupling test access port (TAP) signals to a Joint Test Action Group (JTAG) interface in an integrated circuit package. An nTRST pin receives a test reset signal, a TMS pin receives a test mode select signal, a testing test access port (TAP) has a test reset signal input and a test mode select signal input, and a debugging test access port (TAP) has a test reset signal input coupled to the nTRST pin and a test mode select signal input coupled to the TMS pin. An inverter has an input coupled to the nTRST pin and an output coupled to the test reset signal input of the testing TAP, and an AND gate has a first input coupled to the output of the inverter, a second input coupled to the TMS pin, and an output coupled to the test mode select input of the testing TAP.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: December 3, 2019
    Assignee: STMicroelectronics International N.V.
    Inventors: Venkata Narayanan Srinivasan, Manish Sharma
  • Patent number: 10489271
    Abstract: The size of a multi-processor is prevented from increasing even when the number of processor cores is increased. The multi-processor includes a plurality of cores and a debugging control unit. At least one of the plurality of cores is a debugging core, the debugging core being connected to the debugging control unit so that the debugging control unit can refer to and update register information in the debugging core. The debugging control unit transfers register information in a first core to the debugging core, the first core being one of the plurality of cores and being a core to be debugged. The debugging core debugs a program by using the transferred register information, the program being executed in the first core.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: November 26, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Motoyasu Takabatake, Hisashi Shiota, Atsushi Nakamura, Yuji Chiba
  • Patent number: 10474737
    Abstract: The present disclosure relates to dynamically adjusting a title in a donut chart based on an adjustment to the donut chart. The donut chart may include an outer ring portion, an inner hole region, and the title. In particular, the title may be set based on the inner hole region to prevent the title from overlapping the outer ring portion which may prevent the title from obscuring labels located in the outer ring portion. As a property of the donut chart is adjusted, the title may be automatically adjusted for better visual effect. For example, the title may be dynamically resized and/or dynamically rewrapped. In this manner, the title may be dynamically adjusted based on an adjustment to the donut chart, avoiding the tedious process of manually adjusting the title for better visual effect.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: November 12, 2019
    Assignee: Apple, Inc.
    Inventors: Elizaveta Girsova, Chao-Kuo Lin, Andrew L. Harding, Ryan M. Olshavsky, Carlyle C. Hoch, Kevin D. Broom
  • Patent number: 10452506
    Abstract: A drawing processing device includes a GPU, a diagnosis circuit which executes divisions of a diagnostic test of the GPU and a control unit which controls execution of the divided diagnostic tests by the diagnosis circuit. The control unit schedules so as to complete execution of drawing processes for one frame in a first time which is a one-frame display time which is defined in accordance with a frame rate and schedules so as to execute the divided diagnostic tests in a third time which is a remaining time obtained by subtracting a second time which is a processing time requested for execution of the drawing processes for one frame from the first time.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: October 22, 2019
    Assignee: Renesas Electronics Corporation
    Inventor: Yoshihiko Mori
  • Patent number: 10437700
    Abstract: A method of tracing transactions on an integrated circuit chip. The method comprises, for each transaction: extracting the transaction from interconnect circuitry of the integrated circuit chip, the transaction comprising an address signal and a data signal; applying a filtering condition to the address signal; only if the address signal does not fail the filtering condition, storing the address signal in an address trace buffer; storing the data signal in a data trace buffer; applying a triggering condition to the stored transaction; and outputting the stored transaction if the stored transaction matches the triggering condition.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: October 8, 2019
    Assignee: UltraSoC Technologies Limited
    Inventors: Iain Craig Robertson, Andrew Brian Thomas Hopkins, Michael Jonathan Thyer