Built-in Hardware For Diagnosing Or Testing Within-system Component (e.g., Microprocessor Test Mode Circuit, Scan Path) Patents (Class 714/30)
  • Patent number: 10419216
    Abstract: A keying infrastructure may generate and/or manage cryptographic keys. The cryptographic keys may include identity keys, encryption keys, and a variety of other types of keys. The cryptographic keys may be derived or created with a key derivation function (KDF) or other one-way function. The cryptographic keys may include keys that are accessible to a boot loader, keys that are accessible to particular components of a Trusted Execution Environment (TrEE), and so on. In some examples, a key may be derived from a preceding key in a sequence of keys. The preceding key may be deleted when the key is derived.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: September 17, 2019
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Niels T. Ferguson, Magnus Bo Gustaf Nystrom, Dave M. McPherson, Paul England, Mark Fishel Novak
  • Patent number: 10401428
    Abstract: The disclosure describes a novel method and apparatus for making device TAPs addressable to allow device TAPs to be accessed in a parallel arrangement without the need for having a unique TMS signal for each device TAP in the arrangement. According to the disclosure, device TAPs are addressed by inputting an address on the TDI input of devices on the falling edge of TCK. An address circuit within the device is associated with the device's TAP and responds to the address input to either enable or disable access of the device's TAP.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: September 3, 2019
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10379159
    Abstract: A method and circuit are provided for implementing enhanced scan data testing with minimization of over masking in an on product multiple input signature register (OPMISR) test due to Channel Mask Enable (CME) sharing, and a design structure on which the subject circuit resides. A common Channel Mask Scan Registers (CMSR) logic is used with a multiple input signature register (MISR). Individual local addressing is used for implementing enhanced scan data testing. An architecture and algorithm efficiently expand and target the use of the CME pins to minimize over-masking, to increase test pattern effectiveness with the use of individual local addressing.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: August 13, 2019
    Assignee: International Business Machines Corporation
    Inventors: Steven M. Douskey, Michael J. Hamilton, Amanda R. Kaufer, Matthew B. Schallhorn, Mary P. Kusko
  • Patent number: 10371749
    Abstract: A method and test circuit are provided for implementing enhanced scan data testing with removal of over masking in an on product multiple input signature register (OPMISR) test, and a design structure on which the subject circuit resides. Common Channel Mask Scan Registers (CMSR) data is used with a multiple input signature register (MISR) in each satellite. A test algorithm control is used for implementing enhanced scan data testing to allow sharing the CMSR data and common Channel Mask Enable (CME) pins with removal of over masking. Selectively pausing scan unload is provided for each respective satellite when wrong CME data for the respective satellite is at the CME pins. Each satellite includes a select signal which controls advancing the scan into the MISR. The select signal is used to selectively pause the scan unload for the respective satellite.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: August 6, 2019
    Assignee: International Business Machines Corporation
    Inventors: Steven M. Douskey, Mary P. Kusko, Amanda R. Kaufer, Michael J. Hamilton, Matthew B. Schallhorn
  • Patent number: 10355693
    Abstract: An extended General Purpose Input/Output (eGPIO) scheme is disclosed. In some implementations, an input/output (I/O) boundary scan cell comprises an output path to route output signals from a first voltage domain and signals from a second voltage domain to an I/O pad operating in a pad voltage domain, the output path having a first level shifter to up shift the output signals from the first voltage domain or the second voltage domain to the pad voltage domain; an input path to receive input signals from the I/O pad, the input path having a second level shifter to down shift the input signals from the pad voltage domain to the second voltage domain; and test logic to test signals in the first voltage domain and the second voltage domain.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: July 16, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Varun Jain, Brent Duckering
  • Patent number: 10345379
    Abstract: An integrated circuit includes clock suppression circuitry that can suppress the launch pulse of an at-speed test to prevent scan test data from propagating from an output of a scan latch through a multi-clock cycle combinational logic path to a downstream scan latch during the at-speed test. The integrated circuit can also suppress the capture pulse of an at-speed test to prevents scan test data that is propagated from an upstream scan latch through a multi-cycle combinational logic path from being latched at the downstream latch during the at-speed test.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: July 9, 2019
    Assignee: NXP USA, Inc.
    Inventors: Alexandre Sansigolo Lujan, Milton Hissasi Kataoka, Rubens Takiguti
  • Patent number: 10311963
    Abstract: A data processing apparatus comprises at least one memory configured to store data; processing circuitry to access data in the at least one memory. Memory built-in self-test (MBIST) circuitry has an interface to access the at least one memory and is configured to perform a test procedure for testing at least one target memory location of the at least one memory. The test procedure involves at least writing test data to the target memory location. Diagnostic circuitry executes a diagnostic procedure to generate diagnostic data in response to processing operations carried out by the processing circuitry. The MBIST circuitry is configured to control writing of the diagnostic data generated by the diagnostic circuitry to memory locations in a temporarily reserved memory region comprising at least a portion of the at least one memory.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: June 4, 2019
    Assignee: ARM Limited
    Inventors: Mark Gerald LaVine, Alan Jeremy Becker
  • Patent number: 10310830
    Abstract: Systems, methods, and computer readable media to improve the development of image processing intensive programs are described. In general, techniques are disclosed to non-intrusively monitor the run-time performance of shader programs on a graphics processing unit (GPU)—that is, to profile shader program execution. More particularly, the shader profiling comprises of sampling data during the execution of a compiled code on GPU. The execution duration of the sequences of instructions within the code is determined. Subsequently, based relative latency of the instructions within the sequence, the duration time for each binary instruction is determined. The binary instructions are then mapped to source code in order to obtain the amount of time each source code instruction in a shader take to execute per draw call.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: June 4, 2019
    Assignee: Apple Inc.
    Inventors: Syed Irfan Zaidi, Sun Tjen Fam, Puyan Lotfi, Venkat R. Indukuru, Jun Pan, Andrew M. Sowerby, Jean-Luc Duprat
  • Patent number: 10311002
    Abstract: A programmable apparatus for executing a function is disclosed. The programmable apparatus includes a physical interface configured to be connected with an external apparatus. The programmable apparatus also includes a function logic circuit configured to execute the function on the programmable apparatus. The programmable apparatus further includes a plurality of peripheral logic circuits, each of which is configured to connect the function logic circuit with the physical interface using a respective protocol. The programmable apparatus also includes a selector circuit configured to select one from among the plurality of the peripheral logic circuits to activate.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: June 4, 2019
    Assignee: International Business Machines Corporation
    Inventors: Yutaka Kawai, Yohichi Miwa
  • Patent number: 10302700
    Abstract: Disclosed herein is a test circuit for a device under test. The test circuit includes a test data source and a test data target. A debug chain is coupled between the test data source and test data target, and operates in either a clock debug mode or a test mode. The debug chain, when in the test mode, is deactivated. The debug chain, when in the clock debug mode, receives the test pattern data from the test data source and stores the test pattern data, generates a clock debug signature from the stored test pattern data while clocked by a test clock, and outputs the clock debug signature to the test data target, the clock debug signature indicative of whether the test clock is operating properly.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: May 28, 2019
    Assignee: STMicroelectronics, Inc.
    Inventors: Vinay Kumar, Pramod Kumar
  • Patent number: 10304559
    Abstract: A device is disclosed that includes a data write engine configured to store data into a block of a memory. The device also includes a post-write read engine configured to adjust a read voltage responsive to an output of the temperature sensor and to read stored data from the block based on the adjusted read voltage to verify integrity of the data. The device also includes a block manager configured to initiate a corrective operation responsive to an error characteristic of the data read from the block.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: May 28, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Himanshu Hemant Naik, Biswajit Ray, Mohan Vamsi Dunga, Changyuan Chen
  • Patent number: 10295594
    Abstract: A method for debugging and a method for testing a circuit design on a programmable logic device is disclosed, making use of a parameterized configuration. A corresponding system also is disclosed.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: May 21, 2019
    Assignee: UNIVERSITEIT GENT
    Inventors: Alexandra Kourfali, Dirk Stroobandt
  • Patent number: 10281526
    Abstract: A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. The test architecture includes a selector circuit for selecting a core for testing. Additional features and embodiments of the device test architectures are also disclosed.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: May 7, 2019
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10247776
    Abstract: Structurally assisted functional test and diagnostics include executing one or more functional test exercisers in a functional execution sequence for a device under test up to one or more checkpoints. One or more built-in structural test support circuits of the device under test is applied to identify one or more likely causes of a failure identified at the one or more checkpoints. A portion of the functional execution sequence between a plurality of the checkpoints is iteratively invoked to progressively isolate the one or more likely causes of the failure as a most likely failure source in combination with one or more results from the one or more built-in structural test support circuits.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: April 2, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mary P. Kusko, Franco Motika, Gerard M. Salem
  • Patent number: 10235300
    Abstract: A memory system includes first and second memory devices having at least one different characteristic from each other and a controller suitable for configuring an address map of data stored in the first and the second memory devices, checking access frequency of the stored data, and updating the address map based on a result of the checking.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: March 19, 2019
    Assignee: SK hynix Inc.
    Inventor: Young-Jae Jin
  • Patent number: 10229040
    Abstract: Systems, methods, and computer-readable media for optimizing the execution order of a set of test programs that includes at least one system interval dependent test program are disclosed. The optimized execution order may be determined by identifying each non-system interval dependent test program that can be executed during each instance of a system interval without impacting execution of system interval dependent test programs. The optimized execution order minimizes a total execution time of the set of test programs.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: March 12, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joseph W. Gentile, Brian D. Keuling, Anthony T. Sofia
  • Patent number: 10229123
    Abstract: A method for archiving files includes determining when a change in an operating file is imminent, capturing the operating file immediately before the change in the operating file occurs, if the operating file has not already been captured; and capturing the operating file immediately after the change in the operating file has occurred.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: March 12, 2019
    Inventors: Warren Roach, Steven R Williams, Troy Reiber, Steven C Burdine
  • Patent number: 10215803
    Abstract: Compressed electronic test response using multiple compressed samples of inner scan chains spanning a plurality of concatenated test patterns responses into a single entity in a manner that each scan cell of those scan chains is observed in at least two different compressed inner scan chain samples. At least two compressed scan chain samples that contain at least one sampled scan cell value in common are used to remove undefined values (Xs) from the compressed inner scan chain samples and to identify a scan cell sample containing an error (D or Dbar). Concatenating test pattern responses into a single entity increases test time and test data compression by allowing further reduction of scan chain length.
    Type: Grant
    Filed: October 15, 2014
    Date of Patent: February 26, 2019
    Inventor: Santiago Remersaro
  • Patent number: 10192633
    Abstract: A method and system for high speed on chip testing for quality assurance. A multi-core system on a chip has a plurality of processing cores. The cores act as transaction agents with an auto-response unit fabricated on the chip at a chip boundary, the auto-response unit to provide a deterministic return value based on a logical address of a received read request.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: January 29, 2019
    Assignee: Intel Corporation
    Inventors: Lakshminarayana Pappu, Timothy J. Callahan, Tomer Levy
  • Patent number: 10169131
    Abstract: An approach for determining a trace of a system dump. The approach receives a system dump request, wherein the system dump request includes performing, by one or more computer processors, a system dump utilizing a dumping tool, wherein the system dump includes a trace wherein the trace comprises one or more trace entries collected in a trace table. The approach determines an initial trace of the system dump. The approach determines a time period to collect trace entries following the system dump. The approach determines an updated trace table. The approach determines an extra trace utilizing an exit program.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Darren R. Beard, Jenny J. He
  • Patent number: 10162004
    Abstract: This disclosure describes a reduced pin bus that can be used on integrated circuits or embedded cores within integrated circuits. The bus may be used for serial access to circuits where the availability of pins on ICs or terminals on cores is limited. The bus may be used for a variety of serial communication operations such as, but not limited to, serial communication related test, emulation, debug, and/or trace operations of an IC or core design. Other aspects of the disclosure include the use of reduced pin buses for emulation, debug, and trace operations and for functional operations. In a fifth aspect of the present disclosure, an interface select circuit, FIGS. 41-49, provides for selectively using either the 5 signal interface of FIG. 41 or the 3 signal interface of FIG. 8.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: December 25, 2018
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10127066
    Abstract: Methods and apparatus for updating virtual machines (VMs) on a provider network according to modifications made to a server in a client network. A version of the server may be currently instantiated and executing as one or more VM instances on the provider network. Agent(s) installed on the server in the client network intercept write requests to volume(s) attached to the server, and send blocks that include updates to the server volume(s) to a service on the provider network. The service stores the blocks to incremental snapshots, and generates timestamped machine images (MIs) of the server from the snapshots. A VM service updates the VM instances on the provider network according to the MIs. Thus, the VM instances can be kept up to date with changes to the server without having to upload the entire volume(s) to the provider network to perform each update.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: November 13, 2018
    Assignee: Amazon Technologies, Inc.
    Inventors: Ekanth Sethuramalingam, Suk Won Kim, John Merrill Phillips, David Samuel Zipkin
  • Patent number: 10114687
    Abstract: A method of verifying integrity of communications between a master circuit and a slave circuit includes updating a first cyclic multibit signature based on each transaction sent by the master circuit to the slave circuit. A second cyclic multibit signature is updated based on each transaction received by the slave circuit. One or more bits based on the second cyclic multibit signature are compared with corresponding bits based on the first cyclic multibit signature, with a number of the one or more bits being less than a total number of bits of the second cyclic signature. Error conditions are detected and responded based on the comparing.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: October 30, 2018
    Assignee: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Gilles Ries, Abdelaziz Goulahsen
  • Patent number: 10114658
    Abstract: A method for testing peripheral component interconnect express (PCIe) devices is provided. The method implemented at a PCIe testing system detects that one or more PCIe devices have been inserted into one or more PCIe buses of a data processing system. In response to the detection, the PCIe testing system scans all PCIe buses of the data processing system to discover the one or more PCIe devices. For each of the PCIe devices discovered, the PCIe testing system repairs and retrains a PCIe link associated with the PCIe device, without rebooting the data processing system. The PCIe testing system loads a device driver instance for the PCIe device to be hosted by an operating system. The PCIe testing system then executes a test routine to concurrently test the one or more PCIe devices via the respective device driver instances.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: October 30, 2018
    Assignee: Baida USA LLC
    Inventors: Davy Huang, Krishna Elango, Xu Zhou
  • Patent number: 10110232
    Abstract: A memory includes a clock generator and a multiplexing latch circuit. The clock generator is configured to generate a first latching clock signal and a second latching clock signal based on a multiplexing select signal and a clock signal, and to transmit the first latching clock signal and the second latching clock signal. The multiplexing latch circuit is configured to select the first data or the second data based on the first latching clock signal and the second latching clock signal, and to store and output the selected data.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: October 23, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Hyunsung Hong
  • Patent number: 10101388
    Abstract: Disclosed herein is a method for failure signature detection in a semiconductor comprising generating defect signatures for failing latches from a plurality of integrated circuit chips; generating a latch to mask relationship for the failing latches; generating maximally descriptive masks into identities; generating a list of identities for comparison; determining commonalities between the lists of identities; and generating details about differences and commonalities within the defect signatures.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: October 16, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert C. Redburn, Andrew A. Turner, Jeffrey S. Zimmerman
  • Patent number: 10095702
    Abstract: Systems and methods generate custom device description files using a device description file generator. The systems and methods include a processor and a memory medium. The custom device description file is communicated to one or more devices to configure the respective devices to be able to accept and communicate data defined by the custom device description file.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 9, 2018
    Assignee: COGNEX CORPORATION
    Inventor: Dale Peterson
  • Patent number: 10070176
    Abstract: Systems and methods for implementing a Transport I/O system are described. Network encrypted content may be received by a device. The device may provide the network encrypted content to a secure processor, such as, for example, a smart card. The secure processor obtains a network control word that may be used to decrypt the network encrypted content. The secure processor may decrypt the network encrypted content to produce clear content. In embodiments, the secure processor may then use a local control word to generate locally encrypted content specific to the device. The device may then receive the locally encrypted content from the secure processor and proceed to decrypt the locally encrypted content using a shared local encryption key. The Transport I/O system ensures the protection of the network control word by maintaining the network control word on the secure processor.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: September 4, 2018
    Assignee: NAGRASTAR, LLC
    Inventors: William Michael Beals, Nicolas Fischer, Benjamin Brian Ellis, Gregory Duval
  • Patent number: 10061731
    Abstract: A programmable apparatus for executing a function is disclosed. The programmable apparatus includes a physical interface configured to be connected with an external apparatus. The programmable apparatus also includes a function logic circuit configured to execute the function on the programmable apparatus. The programmable apparatus further includes a plurality of peripheral logic circuits, each of which is configured to connect the function logic circuit with the physical interface using a respective protocol. The programmable apparatus also includes a selector circuit configured to select one from among the plurality of the peripheral logic circuits to activate.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: August 28, 2018
    Assignee: International Business Machines Corporation
    Inventors: Yutaka Kawai, Yohichi Miwa
  • Patent number: 10055587
    Abstract: Disclosed are devices, systems, apparatus, methods, products, media and other implementations, including a method that includes triggering a beacon circuit combined with a hardware-based protection module, included within a hardware device, the hardware-based protection module configured to provide protection against malicious implementations within the hardware device, with the beacon circuit being configured to provide a beacon output when triggered. The method further includes determining based on the beacon output provided by the triggered beacon circuit whether the hardware device includes at least one malicious implementation.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: August 21, 2018
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: Lakshminarasimhan Sethumadhavan, Adam Waksman
  • Patent number: 10031683
    Abstract: A method and technique are provided for providing a service address space. The method includes providing a service co-processor with a service address space attached to a main processor. The main processor is provided with a main address space. Instructions that modify the main address space are intercepted, storage delta packets are generated based on intercepted instructions, and the storage delta packets are sent to a service co-processor maintaining a service address space.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: July 24, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David J. Harman, Neil W. Leedham, Kim P. Walsh, Andrew Wright
  • Patent number: 10025363
    Abstract: The present disclosure is directed to device-agnostic power monitoring and profiling. A target device may be supplied with power through a power monitor that may generate power data based on the power provided to the target device and also transmit the power data. A diagnostic module in the target device may receive the power data and operational data regarding the target device. The diagnostic module may transmit at least one of the power data or the operational data to another device for processing, or may undertake processing the power and operational data. Processing the power and operational data may include generating relevant data by parsing the power and operational data and may then correlate the relevant power data with the relevant operational data. At least the correlated data may then be presented by the target device, may be made available via the Internet and/or may be transmitted to another device.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: July 17, 2018
    Assignee: Intel Corporation
    Inventors: Abhishek Agrawal, Thyagarajan Srinivasan
  • Patent number: 10025515
    Abstract: A system and technique are provided for providing a service address space. The system includes a service co-processor provided with a service address space. The service co-processor is attached to a main processor where the main processor is provided with a main address space. The service co-processor creates and maintains an independent copy of the main address space in the form of the service address space. The service co-processor updates the service address space with storage delta packets received from the main processor, and the service co-processor performs diagnostic services based on command packets received from the main processor.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: July 17, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David J. Harman, Neil W. Leedham, Kim P. Walsh, Andrew Wright
  • Patent number: 10024918
    Abstract: A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. The test architecture includes a selector circuit for selecting a core for testing. Additional features and embodiments of the device test architectures are also disclosed.
    Type: Grant
    Filed: May 2, 2017
    Date of Patent: July 17, 2018
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10008289
    Abstract: A semiconductor memory device and a method of operating the same are provided. The method of operating the semiconductor memory device includes detecting a first group of changed bits between first and second page data, by comparing the first and second page data, which are read out using first and second test voltages from the memory cells, respectively, detecting a second group of changed bits between the second page data and a third page data, by comparing the second page data with the third page data read out from the memory cells using a third test voltage, comparing the numbers of the first and second groups of changed bits, and determining one of the first to third test voltages as a read voltage according to the comparing of the numbers of the first and second groups of changed bits.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: June 26, 2018
    Assignee: SK Hynix Inc.
    Inventor: Tae Hoon Kim
  • Patent number: 9963036
    Abstract: This vehicle ground fault detection apparatus maintains a high level of insulation in an aluminum electrolytic capacitor to improve long-term reliability. This vehicle ground fault detection apparatus (10) detects a ground fault of a DC power supply by connecting the positive terminal or the negative terminal of a high-voltage power supply to one terminal of a coupling capacitor (15) provided with aluminum electrolytic capacitors (C1, C2, C3), applying a square-wave pulse signal to a measurement point at the other terminal of the coupling capacitor, and detecting a voltage signal generated at the measurement point. The vehicle ground fault detection apparatus (10) includes a charger and discharger (CPU 13) that charges and discharges the coupling capacitor when a ground fault of the DC power supply is not being detected.
    Type: Grant
    Filed: April 3, 2015
    Date of Patent: May 8, 2018
    Assignee: CALSONIC KANSEI CORPORATION
    Inventor: Yasuhiro Kobayashi
  • Patent number: 9952282
    Abstract: A programmable device comprises a plurality of programmable blocks, a debug interface coupled with the plurality of programmable blocks, and a power manager coupled with the plurality of programmable blocks. The power manager is configured to supply power to a subset of the plurality of programmable blocks during debugging of the subset while maintaining a different subset of the plurality of programmable blocks in a lower power mode.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: April 24, 2018
    Assignee: Cypress Semiconductor Corporation
    Inventors: Harold M. Kutz, Timothy John Williams, Bert S. Sullam, Warren S. Snyder, James H. Shutt, Bruce E. Byrkett, Monte Mar, Eashwar Thiagarajan, Nathan Wayne Kohagen, David G. Wright, Mark E Hastings, Dennis R. Seguine
  • Patent number: 9927309
    Abstract: According to one embodiment, there is provided a semiconductor device including a temperature detection circuit and a test circuit. The temperature detection circuit is configured to detect a temperature by comparing potential of a reference block and reference potential. The test circuit is configured to test, in a test mode, an operation of the temperature detection circuit by serially switching a value of the reference potential to a value selected from a plurality of values, which is different from each other, while a temperature of the semiconductor device is kept at a first temperature.
    Type: Grant
    Filed: September 8, 2014
    Date of Patent: March 27, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Makoto Hara, Shuuji Matsumoto, Hirosi Ootuka
  • Patent number: 9903914
    Abstract: A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device waits for a synchronization point sequence. Upon detecting the synchronization point sequence, the second remote device implements a predetermined feature set and synchronizes itself to the state diagram at a common point as the host device and first remote device.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: February 27, 2018
    Assignee: Texas Instruments Incorporated
    Inventor: Gary L. Swoboda
  • Patent number: 9903915
    Abstract: The disclosure describes a novel method and apparatus for allowing response data output from the scan outputs of a circuit under test to be formatted and applied as stimulus data input to the scan inputs of the circuit under test. Also the disclosure described a novel method and apparatus for allowing the response data output from the scan outputs of a circuit under test to be formatted and used as expected data to compare against the response data output from the circuit under test. Additional embodiments are also provided and described in the disclosure.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: February 27, 2018
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 9900840
    Abstract: A communication device includes a reception unit configured to receive information from an external device; a control unit configured to implement control for storing, in a storage unit, state information relevant to a state of the communication device itself; a first processor configured to perform a process on the information received from the external device; and a second processor configured to perform a process of executing output. When the information received from the external device is a browse request to browse the state information, the first processor acquires requested information from the state information stored in the storage unit, and executes control to send the acquired information to the external device.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: February 20, 2018
    Assignee: RICOH COMPANY, LTD.
    Inventor: Hidekuni Annaka
  • Patent number: 9880903
    Abstract: A method for intelligently rebuilding a RAID includes subjecting a storage drive in an existing RAID to a stress workload test by placing the storage drive in a RAID 1 configuration with a spare storage drive. In the event the storage drive fails the stress workload test but can still be read, the method uses the RAID 1 configuration to copy recoverable data from the failing storage drive to the spare storage drive. The method uses other storage drives in the existing RAID to reconstruct, on the spare storage drive, data that is not recoverable from the failing storage drive. Either before or after all non-recoverable data has been reconstructed on the spare storage drive, the method logically replaces, in the existing RAID, the failing storage drive with the spare storage drive. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: November 22, 2015
    Date of Patent: January 30, 2018
    Assignee: International Business Machines Corporation
    Inventors: Matthew G. Borlick, John C. Elliott, Lokesh M. Gupta, Clint A. Hardy, Karl A. Nielsen
  • Patent number: 9881693
    Abstract: Apparatuses including an interface chip that interfaces with dice through memory channels are described. An example apparatus includes: an interface chip that interfaces with a plurality of dice through a plurality of memory channels, each of the dice comprising a plurality of memory cells, and the interface chip comprising a test circuit. The test circuit includes: first and second terminals corresponding to the first and second memory channels respectively; a test terminal and a built in self test (BIST) circuit common to the first and second memory channels; and a selector coupled to the first and second terminals, the test terminal and the BIST circuit, and couples a first selected one of the first terminal, the test terminal and the BIST circuit to the first channel and a second selected one of the second terminal, the test terminal and the BIST circuit to the second channel.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: January 30, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Chikara Kondo, Tomoyuki Shibata, Ryota Suzuki
  • Patent number: 9870488
    Abstract: Circuitry and methods prevent unauthorized programming, or reprogramming, of a programmable device, by requiring a signature in the configuration data to match a signature previously stored in the programmable device. A programmable integrated circuit device includes an input for configuration data, and programming control circuitry operable to derive a current signature from the configuration data, examine a first bit stored in the programmable integrated circuit device, and when the first bit is in a first state, compare the current signature to a first predetermined signature stored in the programmable integrated circuit device and configure the programmable integrated circuit device according to the configuration data only when the current signature matches the first predetermined signature, and when the first bit is in a second state, configure the programmable integrated circuit device according to the configuration data without comparing the current signature to the first predetermined signature.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: January 16, 2018
    Assignee: Altera Corporation
    Inventor: Bruce B. Pedersen
  • Patent number: 9857425
    Abstract: A test circuit board adapted to be used on memory slot is provided. Each memory slot of a board to be tested is connected to one test circuit board. A plurality of the test circuit boards form an in-series connection therebetween. A test access port (TAP) controller is connected electrically to the board to be tested and one of the test circuit boards so that the memory slots, which are connected to the test circuit boards, may be tested at the same time.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: January 2, 2018
    Assignees: INVENTEC (PUDONG) TECHNOLOGY CORPORATION, INVENTEC CORPORATION
    Inventors: Ping Song, Chang Qing Mu, Xiao Qian Li
  • Patent number: 9858167
    Abstract: Embodiments of an invention for monitoring the operation of a processor are disclosed. In one embodiment, a system includes a processor and a hardware agent external to the processor. The processor includes virtualization logic to provide for the processor to operate in a root mode and in a non-root mode. The hardware agent is to verify operation of the processor in the non-root mode based on tracing information to be collected by a software agent to be executed by the processor in the root mode.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: January 2, 2018
    Assignee: Intel Corporation
    Inventors: Gilbert Neiger, Andrew V. Anderson, Richard A. Uhlig, David M. Durham, Ronak Singhal, Xiangbin Wu, Sailesh Kottapalli
  • Patent number: 9858148
    Abstract: A method for preventing data loss in a RAID includes monitoring the age of storage drives making up a RAID. When a storage drive in the RAID reaches a specified age, the method individually tests the storage drive by subjecting the storage drive to a stress workload test. This stress workload test may be designed to place additional stress on the storage drive while refraining from adding stress to other storage drives in the RAID. In the event the storage drive fails the stress workload test (e.g., the storage drive cannot adequately handle the additional workload or generates errors in response to the additional workload), the method replaces the storage drive with a spare storage drive and rebuilds the RAID. In certain embodiments, the method tests the storage drive with greater frequency as the age of the storage drive increases. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: November 22, 2015
    Date of Patent: January 2, 2018
    Assignee: International Business Machines Corporation
    Inventors: Matthew G. Borlick, Lokesh M. Gupta, Clint A. Hardy, Karl A. Nielsen, Brian A. Rinaldi
  • Patent number: 9849373
    Abstract: A data communication restricted content providing device executes a program of game content, accepts operation input for the game content, controls the game content in accordance with operation input, generates, based on information of a changed progress condition of the game content, audio data indicating the progress condition, and plays back the audio data. An information processing device acquires an audio signal played back by the content providing device, extracts information of the progress condition from the audio signal, and outputs, to an external device, information of the progress condition.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: December 26, 2017
    Assignee: SQUARE ENIX CO., LTD.
    Inventor: Hiroki Morimoto
  • Patent number: 9817789
    Abstract: The SNMP cache of the present solution supports multi-core/multi-node environment by recalculating the SNMP ordering of the entities in the response from multiple cores/nodes at insertion time. The most significant gain is achieved by prefetching or augmenting the cache, wherein while requesting an entity and its stat information, next few entities in SNMP order are requested from the owner processes. SNMP Management systems extensively utilize repeated GETNEXT (such as via a SNMP WALK) and few next responses may be served from the cache directly. Further performance improvements are obtained by introducing another level of cache on top of the existing cache. This auxiliary cache ensures a high hit ratio for repeated SNMP GETNEXT request (SNMP WALK operation) by caching last accessed entity within the main cache. This auxiliary cache also aids in insertion in the larger main cache by maintaining pointers to last accessed entity before the main cache miss.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: November 14, 2017
    Assignee: Citrix & Systems, Inc.
    Inventor: Nishant Kumar Jain
  • Patent number: 9812223
    Abstract: A semiconductor memory device includes memory cells coupled to a word line; and a peripheral circuit configured to read first to kth page data from the memory cells by sequentially applying first to kth test voltages to the word line, where k is a natural number greater than 3, wherein the peripheral circuit is configured to gradually reduce times during which the first to kth test voltages are applied to the word line.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: November 7, 2017
    Assignee: SK Hynix Inc.
    Inventor: Tae Hoon Kim