Built-in Hardware For Diagnosing Or Testing Within-system Component (e.g., Microprocessor Test Mode Circuit, Scan Path) Patents (Class 714/30)
  • Patent number: 11907100
    Abstract: A method of tracing instruction execution on a processor of an integrated circuit chip in real time whilst the processor continues to execute instructions during clock cycles of the processor. The instruction execution of the processor is monitored by counting the number of successive instructions which are retired contiguously in time to form an instruction count, and counting the number of subsequent contiguous clock cycles of the processor during which no instruction is retired to form a stall count. A trace message is generated which includes the instruction count and the stall count, and the trace message is outputted.
    Type: Grant
    Filed: April 16, 2020
    Date of Patent: February 20, 2024
    Assignee: Siemens Industry Software Inc.
    Inventor: Iain Robertson
  • Patent number: 11886291
    Abstract: An information handling system utilizes data with a cache line size. A memory module is coupled to a memory controller by a memory bus, and stores and retrieves data with a memory line size. The cache line size is an integer multiple of the memory line size. The memory controller calculates error correction code data for each memory line of user data, and generates metadata related to the user data for chunks of data that are equal to an integer number (N) of cache lines, where N is greater than one.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: January 30, 2024
    Assignee: Dell Products L.P.
    Inventor: Stuart Allen Berke
  • Patent number: 11775415
    Abstract: A processor comprising at least one processing module, each processing module comprising: an execution pipeline; memory; an instruction fetch unit comprising operable to switch between an operational mode and a debugging mode, the instruction fetch unit being configured so as, when in the operational mode, to fetch machine code instructions from the memory into the execution pipeline to be executed; and a debug interface for connecting to a debug adapter. The debug interface comprises a debug instruction register enabling the debug adapter to write a machine code instruction to the debug instruction register, and wherein the instruction fetch unit is configured so as, when in the debug mode, to fetch instructions from the debug instruction register into the pipeline instead of from the memory.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: October 3, 2023
    Assignee: GRAPHCORE LIMITED
    Inventors: Alan Graham Alexander, Graham Bernard Cunningham
  • Patent number: 11714736
    Abstract: Methods, apparatuses, and non-transitory machine-readable media associated with relative humidity (RH) sensors are described. Examples can include receiving from an RH sensor RH information of an environment of a processing resource or a memory resource coupled to the processing resource, or both, determining that the RH information indicates an RH level above a particular threshold for the processing resource or the memory resource, or both, and disabling one or more aspects of the processing resource or the memory resource, or both, to mitigate damage to the processing resource or the memory resource, or both, responsive to determining that the RH is above the particular threshold.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: August 1, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Brooke Spencer, Jennifer F. Huckaby, Yi Hu, Deepti Verma
  • Patent number: 11709202
    Abstract: Existing multi-wire debugging protocols, such as 4-wire JTAG, 2-wire cJTAG, or ARM SWD, are run through a serial wireless link by providing the debugger and the target device with hardware interfaces that include UARTs and conversion bridges. The debugger interface serializes outgoing control signals and de-serializes returning data. The target interface de-serializes incoming control signals and serializes outgoing data. The actions of the interfaces are transparent to the inner workings of the devices, allowing re-use of existing debugging software. Compression, signal combining, and other optional enhancements increase debugging speed and flexibility while wirelessly accessing target devices that may be too small, too difficult to reach, or too seal-dependent for a wired connection.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: July 25, 2023
    Assignee: Intel Corporation
    Inventors: Sankaran M. Menon, Bradley H. Smith, Jinshi Huang, Rolf H. Kuehnis
  • Patent number: 11675005
    Abstract: The semiconductor device includes a transmitting-side hierarchical block, a receiving-side hierarchical block and an inter-block circuit. The transmitting-side hierarchical block includes a first logic circuit and an output control circuit connected to the first logic circuit and controlling an output signal of the transmitting-side hierarchical block. The receiving-side hierarchical block includes a second logic circuit being scan test target and operating by receiving the output signal of the transmitting-side hierarchical block, and a test control circuit controlling the scan test of the second logic circuit. The inter-block circuit transmits the output signal of the transmitting-side hierarchical block to the receiving-side hierarchical block.
    Type: Grant
    Filed: November 24, 2020
    Date of Patent: June 13, 2023
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Masayuki Tsukuda, Tomoji Nakamura
  • Patent number: 11669490
    Abstract: An apparatus to facilitate computing efficient cross channel operations in parallel computing machines using systolic arrays is disclosed. The apparatus includes a plurality of registers and one or more processing elements communicably coupled to the plurality of registers. The one or more processing elements include a systolic array circuit to perform cross-channel operations on source data received from a single source register of the plurality of registers, wherein the systolic array circuit is modified to: receive inputs from the single source register at different stages of the systolic array circuit; perform cross-channel operations at channels of the systolic array circuit; bypass disabled channels of the systolic array circuit, the disabled channels not used to compute the cross-channel operations; and broadcast a final result of a final stage of the systolic array circuit to all channels of a destination register.
    Type: Grant
    Filed: November 3, 2021
    Date of Patent: June 6, 2023
    Assignee: INTEL CORPORATION
    Inventors: Subramaniam Maiyuran, Jorge Parra, Supratim Pal, Chandra Gurram
  • Patent number: 11631474
    Abstract: A redundancy analysis method of replacing a faulty part of a memory with at least one spare according to the present embodiment includes: acquiring fault information of the memory; and redundancy-allocating the fault with combinations of the spares to correspond to combination codes corresponding to the combinations of the spares, in which, the redundancy-allocating with the combination of the spare areas includes performing parallel processing on each combination of the spares.
    Type: Grant
    Filed: October 22, 2021
    Date of Patent: April 18, 2023
    Assignee: UIF (UNIVERSITY INDUSTRY FOUNDATION), YONSEI UNIVERSITY
    Inventors: Sung Ho Kang, Tae Hyun Kim
  • Patent number: 11598804
    Abstract: Embodiments described herein may be directed to receiving a plurality of data captured, respectively, by a plurality of test instruments coupled to a device under test, wherein a plurality of data elements within, respectively, the plurality of captured data are associated with a timestamp based upon a time a data element was captured. Embodiments may also analyze the received plurality of data captured, respectively, by the one or more test instruments, and graphically display at least a portion of the analyzed plurality of captured data to a user. Other embodiments may be identified herein.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: March 7, 2023
    Assignee: Intel Corporation
    Inventors: Jesse Armagost, Nathan Blackwell, Matthew Boelter, Geoffrey Kelly, James Neeb, Sundar Pathy, Yu Zhang, Shelby Rollins
  • Patent number: 11586534
    Abstract: The present disclosure provides method and apparatus for identifying flaky tests. Historical running data of a test case may be obtained. Statistical analysis may be performed based on the historical running data. It may be determined whether the test case is a flaky test based on the statistical analysis.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: February 21, 2023
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Bin Qin, Mengdie Xia, Yiliang Xiong, Fangpeng Guo
  • Patent number: 11531773
    Abstract: An apparatus, method, and system assess the trustworthiness of a design representation while maintaining its confidentiality and thwarting attempts at unauthorized access, misappropriation, and reverse engineering of confidential proprietary aspects of the design representation and/or its bit stream. A utility/tool is provided for trust assessment and verification of designs and/or bit streams. The utility/tool may be instantiated on a semiconductor device or implemented as a utility executable on a mobile computing device or other information processing system, apparatus, or network.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: December 20, 2022
    Assignee: GRAF RESEARCH CORPORATION
    Inventors: Jonathan Peter Graf, Ali Asgar Ali Akbar Sohanghpurwala, Scott Jeffery Harper
  • Patent number: 11519963
    Abstract: A semiconductor integrated circuit includes scan chains, each of which includes a serial connection of sequential circuits and performs a shift register operation in a scan test; and an integrated clock gating (ICG) chain composed by coupling, to one another, ICG circuits, each of which individually supplies a corresponding one of the scan chains with a circuit clock signal to operate the sequential circuits. In the ICG chain, an ICG enable propagation signal for controlling timing when the ICG circuits output the circuit clock signals propagates through a signal line and is input sequentially to the ICG circuits. The ICG circuits output the circuit clock signals at respective timings that are different among the scan chains.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: December 6, 2022
    Assignee: Kioxia Corporation
    Inventor: Masaki Ooiso
  • Patent number: 11442805
    Abstract: The present disclosure relates to a system for real-time debugging of microcontroller, the system includes a microcontroller configured in an embedded device to execute a set of instructions, the microcontroller includes a counter unit that generates a set of values for the executed set of instructions. An on-chip debugger (OCD) fetches a selective set of data packets of the set of instructions from the microcontroller. An encoder encodes the selective set of data packets to store the encoded set of data packets in a storage unit, wherein encoding of the set of data packets is performed to compress the data for minimal information size such that the external debugger unit (EDU) receives the encoded set of data packets with minimal information size through the external interface.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: September 13, 2022
    Assignee: SILICONCH SYSTEMS PVT LTD
    Inventors: Rakesh Kumar Polasa, Shrikantha Venkatesh, Harshith Subramanya
  • Patent number: 11416612
    Abstract: Disclosed are systems and methods for detecting malicious applications. The described techniques detect a first process has been launched on a computing device, and monitor at least one thread associated with the first process using one or more control points of the first process. An execution stack associated with the one or more control points of the first process is received from the first process. In response to detecting activity on the one or more control points of the first process, an indication that the execution of the first process is malicious is generated by applying a machine learning classifier to the received execution stack associated with the one or more control points of the first process.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: August 16, 2022
    Assignee: Acronis International GmbH
    Inventors: Vladimir Strogov, Serguei Beloussov, Alexey Dod, Valery Chernyakovsky, Anatoly Stupak, Sergey Ulasen, Nikolay Grebennikov, Vyacheslav Levchenko, Stanislav Protasov
  • Patent number: 11403206
    Abstract: Provided are a method and an apparatus for debugging, and a system on chip. The method for debugging includes: a component to be debugged receives a debugging instruction from a controller, and the component to be debugged performs debugging operation according to the debugging instruction and configuration of a state machine inside the component to be debugged. Then an SW level debugging operation of component on system on chip can be achieved, which improves the debugging efficiency of these components with large amounts of data flow on system on chip.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: August 2, 2022
    Assignee: HANGZHOU FABU TECHNOLOGY CO., LTD.
    Inventors: Xiaofei He, Siddartha Kavilipati, Bahaa Osman
  • Patent number: 11397702
    Abstract: Disclosed embodiments relate, generally, to interfacing serial communication interfaces of a first device with a parallel communication interface of a second device. A first group of two or more serial communication interfaces and an interfacing logic may be provided. The interfacing logic may form second encoded data blocks by arranging the data elements of the first encoded data blocks such that data elements within a same data element position of respective second encoded data blocks represent a given one of the symbols, and provide the second encoded data blocks to a number of serial communication interfaces coupled to a parallel communication interface of another device. An interfacing logic may additionally or alternatively be configured to receive, from a second group of two or more serial communication interfaces, received encoded data blocks representing received symbols.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: July 26, 2022
    Assignee: Microchip Technology Incorporated
    Inventor: Johan Vaarlid
  • Patent number: 11387154
    Abstract: A memory device includes a first wafer including a first bonding pad disposed on a first surface; a second wafer, including a second bonding pad disposed on a second surface of the second wafer, the second surface of the second wafer bonded on the first surface of the first wafer; and a first test pattern. The first test pattern includes a pair of first test pads disposed on the first surface and electrically coupled to each other; a pair of second test pads disposed on the second surface of the second wafer and respectively coupled to the pair of first test pads, when no misalignment failure between the first bonding pad and the second bonding pad occurs; and a pair of third test pads disposed on a third surface of the second wafer, which is opposite to the second surface, and respectively coupled to the pair of second test pads.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: July 12, 2022
    Assignee: SK hynix Inc.
    Inventor: Sung Lae Oh
  • Patent number: 11379297
    Abstract: An automotive control system includes a safety processor and a system-on-a-chip. The SoC includes a primary processor, a safety monitor, first and second GPIO banks, and a debug interface. The safety monitor is configured to detect a fault condition of the primary processor and to provide an indication of the fault condition to the safety processor. The first GPIO bank is coupled to the primary processor to provide input/output operations to a non-critical function of an automobile, while the second GPIO bank is coupled for a critical function of the automobile. The debug interface is coupled to the second GPIO bank to form a scan chain with input and output registers of the second GPIO bank, and is coupled to the safety processor to receive control information for the scan chain to provide input/output operations to the critical function of the automobile when the safety monitor provides the indication.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: July 5, 2022
    Assignee: NXP USA, Inc.
    Inventors: Jeffrey Thomas Loeliger, Derek Beattie, Gordon Campbell
  • Patent number: 11372042
    Abstract: A semiconductor device includes a temperature sensor, a scan control circuit which generates scan chain selection information in accordance with a measurement result of the temperature sensor, a clock control circuit which generates one or more scan chain clock signals based on an external clock signal and the scan chain selection information, a pattern generation circuit which generates a test pattern, and a logic circuit which includes a plurality of scan chains and which receives the scan chain clock signals and the test pattern. The clock control circuit generates the scan chain clock signal in association with each scan chain. During a burn-in test, the logic circuit captures the test pattern into the scan chain associated with the scan chain clock signal.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: June 28, 2022
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Koji Suzuki, Masaaki Tanimura
  • Patent number: 11307793
    Abstract: A memory controller according to an aspect of the present invention includes a buffer configured to store an operation command table including operation commands entered by a user, a BIST (built-in self-tester) controller configured to generate a pointer pointing to an operation command, a command and address generator configured to decode the operation command corresponding to the pointer among the operation commands to generate first memory commands, a command and address queue comprising queues for storing the first memory commands, and a command requester configured to output a test command including first operation command information for the generation of a memory command output from a first queue included in the queues among the memory command, location information of the first queue, and the operation commands.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: April 19, 2022
    Assignee: SILICON WORKS CO., LTD.
    Inventor: Jang Won Seo
  • Patent number: 11301312
    Abstract: Systems and methods are described for improved error logging during system boot and shutdown. A hardware initialization firmware on a computing device can include a logging module. When errors occur during early system booting or late system shutdown, the firmware can create error logs. The logging module can receive the error logs and prioritize them according to a set of rules. The logging module can select error logs of the highest priority up to a predetermined maximum amount. The logging module can modify the error logs using a shorthand form and write them to nonvolatile random-access memory. The firmware can initialize runtime services and launch an operating system. A system logger on the operating system can retrieve the error logs, save them to a file, and erase them from the memory.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: April 12, 2022
    Assignee: VMware, Inc.
    Inventors: Ashish Kaila, Tobias Stumpf, Mukund Gunti
  • Patent number: 11263220
    Abstract: Systems and methods are described for modifying input and output (I/O) to an object storage service by implementing one or more owner-specified functions to I/O requests. A function can implement a data manipulation, such as filtering out sensitive data before reading or writing the data. The functions can be applied prior to implementing a request method (e.g., GET or PUT) specified within the I/O request, such that the data to which the method is applied my not match the object specified within the request. For example, a user may request to obtain (e.g., GET) a data set. The data set may be passed to a function that filters sensitive data to the data set, and the GET request method may then be applied to the output of the function. In this manner, owners of objects on an object storage service are provided with greater control of objects stored or retrieved from the service.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: March 1, 2022
    Assignee: Amazon Technologies, Inc.
    Inventors: Timothy Lawrence Harris, Kevin C. Miller, Ramyanshu Datta
  • Patent number: 11257562
    Abstract: An integrated circuit includes a built-in-self-test circuit that generates output test signals and a circuit tested by the built-in-self-test circuit. The circuit tested by the built-in-self-test circuit generates test results in response to the output test signals during a test. Pipeline register circuits are coupled together to form a signal path for transmitting the output test signals from the built-in-self-test circuit to the circuit tested by the built-in-self-test circuit. A functional circuit block is located in a reserved die area of the integrated circuit. The signal path is routed around the reserved die area to the circuit tested by the built-in-self-test circuit. At least a subset of the pipeline register circuits are located adjacent to at least two sides of the reserved die area.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: February 22, 2022
    Assignee: Intel Corporation
    Inventor: Tze Sin Tan
  • Patent number: 11249115
    Abstract: An electrical test and measurement device is described that has at least one analog channel comprising an analog input, an attenuator circuit, an amplifier unit, and a digitizer. The electrical test and measurement device comprises another digitizer allocated to a digitizer input of the electrical test and measurement device. The digitizer input is configured to be connected to a measurement extension device. Further, a measurement extension device and a test and measurement system are described.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: February 15, 2022
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventor: Philip Diegmann
  • Patent number: 11221901
    Abstract: An integrated circuit (IC) chip includes system circuitry having system memory, and a master processor and a checker processor configured to operate in lockstep; and monitoring circuitry comprising an internal lockstep monitor, a master tracer and a checker tracer. The internal lockstep monitor is configured to: observe states of internal signals of the master processor and the checker processor, compare corresponding observed states of the master processor and the checker processor, and if the corresponding observed states differ: trigger the master tracer to output stored master trace data recorded from the output of the master processor, and trigger the checker tracer to output stored checker trace data recorded from the output of the checker processor.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: January 11, 2022
    Assignee: SIEMENS INDUSTRY SOFTWARE INC.
    Inventors: Gajinder Panesar, Iain Robertson, Hanan Moller, Callum Stewart, Melvin Cheah
  • Patent number: 11210096
    Abstract: A vector friendly instruction format and execution thereof. According to one embodiment of the invention, a processor is configured to execute an instruction set. The instruction set includes a vector friendly instruction format. The vector friendly instruction format has a plurality of fields including a base operation field, a modifier field, an augmentation operation field, and a data element width field, wherein the first instruction format supports different versions of base operations and different augmentation operations through placement of different values in the base operation field, the modifier field, the alpha field, the beta field, and the data element width field, and wherein only one of the different values may be placed in each of the base operation field, the modifier field, the alpha field, the beta field, and the data element width field on each occurrence of an instruction in the first instruction format in instruction streams.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: December 28, 2021
    Assignee: INTEL CORPORATION
    Inventors: Robert C. Valentine, Jesus Corbal San Adrian, Roger Espasa Sans, Robert D. Cavin, Bret L. Toll, Santiago Galan Duran, Jeffrey G. Wiedemeier, Sridhar Samudrala, Milind Baburao Girkar, Edward Thomas Grochowski, Jonathan Cannon Hall, Dennis R. Bradford, Elmoustapha Ould-Ahmed-Vall, James C Abel, Mark Charney, Seth Abraham, Suleyman Sair, Andrew Thomas Forsyth, Lisa Wu, Charles Yount
  • Patent number: 11199586
    Abstract: A Joint Test Access Group (JTAG) device can include a Joint Test Access Group (JTAG) port, transport layer circuitry to provide a communication to and from a debug device, and packet interpreter circuitry communicatively coupled between the JTAG port and the transport layer circuitry, the packet interpreter circuitry to translate data in a packet from the debug device into a sequence of bits to be provided to the JTAG port.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: December 14, 2021
    Assignee: Intel Corporation
    Inventors: Enrico D. Carrieri, John W. Kitterman, Keith A. Jones
  • Patent number: 11200125
    Abstract: Embodiments of the invention are directed to a computer-implemented method of unit environment verification. The method includes monitoring, by a processor, a data stream between a first driver and a device under test (DUT) in a unit verification environment. The processor retrieves a transaction value from a database, wherein the transaction value was generated in a higher-level verification environment than the unit verification environment. The processor transmits the retrieved transaction value to the DUT. The processor compares a response from the DUT to the transmitted transaction value to an expected value. In response to the comparison indicating an error, the processor initiates a repair of the error at the unit verification environment.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: December 14, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Narasimha Adiga, Madhusudan Kadiyala
  • Patent number: 11195839
    Abstract: A memory device comprises a first selector and a storage capacitor in series with the first selector. A second selector is in parallel with the storage capacitor coupled between the first selector and zero volts. A plurality of memory devices form a 2S-1C cross-point DRAM array with 4F2 or less density.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: December 7, 2021
    Assignee: Intel Corporation
    Inventors: Ravi Pillarisetty, Abhishek A. Sharma, Prashant Majhi, Elijah V. Karpov, Brian S. Doyle
  • Patent number: 11175978
    Abstract: An error in content generated by a first electronic device can be detected by a second electronic device. The second electronic device receives, in one or more messages, first message content and second message content generated by integrated circuit logic within the first electronic device. The second electronic device compares the first message content with predetermined message content. Based on detecting a mismatch between the first message content and the predetermined message content, the second electronic device initiates error recovery for the one or more messages. Initiating error recovery can include, for example, logging an error in the integrated circuit logic, requesting for the first electronic device to regenerate the first message content and second message content, or initiating execution of a program that detects and corrects programming errors in the integrated circuit logic.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: November 16, 2021
    Assignee: International Business Machines Corporation
    Inventor: Michael Shapiro
  • Patent number: 11137823
    Abstract: The present disclosure describes methods and systems for data storage or other devices that are L1 sub-state capable, to be able to enter these sub-states while on the same network or bus as a device not enabled for transition to an L1 sub-state. In some embodiments, when an LTSSM circuit in a MAC of a PCIe device indicates an L1 idle state, an L1 sub-state (L1SS) timer is initiated in a CLKREQ on the device. Upon expiration of the timer, a CLKREQ_in emulator de-asserts its signal on the MAC, causing the MAC to enter an L1SS.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: October 5, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Elkana Richter, Shay Benisty, Nissim Elmaleh
  • Patent number: 11119149
    Abstract: Techniques are disclosed relating to using non-debug path circuitry to perform debug commands. In some embodiments, an apparatus includes a processor core that includes path circuitry configured to access data for instructions executed by the processor core and storage elements which the path circuitry is configured to access via one or more ports. In some embodiments, the apparatus includes debug circuitry configured to receive external debug inputs and send abstract commands to the processor core based on the external debug inputs. In some embodiments, the apparatus includes control circuitry in the processor core configured to, in response to an abstract command to access one or more of the storage elements: generate signaling to access the one or more storage elements using the path circuitry, access read data from the one or more storage elements based on the signaling, and transmit the accessed read data to the debug circuitry.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: September 14, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Deepak Panwar, Muhammad Tauseef Rab, Robert T. Golla, Matthew B. Smittle
  • Patent number: 11114138
    Abstract: A memory structure having 2m read ports allowing for concurrent access to n data entries can be constructed using three memory structures each having 2m?1 read ports. The three memory structures include two structures providing access to half of the n data entries, and a difference structure providing access to difference data between the halves of the n data entries. Each pair of the 2m ports is connected to a respective port of each of the 2m?1-port data structures, such that each port of the part can access data entries of a first half of the n data entries either by accessing the structure storing that half directly, or by accessing both the difference structure and the structure containing the second half to reconstruct the data entries of the first half, thus allowing for a pair of ports to concurrently access any of the stored data entries in parallel.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: September 7, 2021
    Assignee: Groq, Inc.
    Inventors: Jonathan Alexander Ross, Gregory M. Thorson
  • Patent number: 11113233
    Abstract: Systems and methods are provided to enable parallelized multiply-accumulate operations in a systolic array. Each row of the systolic array can include multiple busses enabling independent transmission of inputs along the respective bus. Each processing element of a given row-oriented bus can receive an input from a prior element of the given row-oriented bus, and perform arithmetic operations on the input. The systolic array can be divided into a plurality of sub-arrays corresponding to a row-oriented bus where each sub-array is separated by a shifter. Each shifter can shift a row-oriented bus into the active bus position for a given sub-array. Use of row-oriented busses can enable parallelization to increase speed or enable increased latency at individual processing elements.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: September 7, 2021
    Assignee: Amazon Technologies, Inc.
    Inventor: Thomas A Volpe
  • Patent number: 11112854
    Abstract: Operating pulsed latches on a variable power supply including turning on a first power rail powering a first latch of an integrated circuit, wherein the first latch is a pulsed latch; turning on a second power rail powering a second latch of the integrated circuit, wherein the second latch is operatively coupled to the first latch; performing a scan operation using the first latch and the second latch; turning off the first power rail powering the first latch; and performing a functional operation using the second latch, wherein the first power rail powering the first latch is off during the functional operation.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: September 7, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steven M. Douskey, Raghu G. Gopalakrishnasetty, Mary P. Kusko, Hari Krishnan Rajeev, James D. Warnock
  • Patent number: 11094394
    Abstract: Methods, systems, and devices for imprint recovery management for memory systems are described. In some cases, memory cells may become imprinted, which may refer to conditions where a cell becomes predisposed toward storing one logic state over another, resistant to being written to a different logic state, or both. Imprinted memory cells may be recovered using a recovery or repair process that may be initiated according to various conditions, detections, or inferences. In some examples, a system may be configured to perform imprint recovery operations that are scaled or selected according to a characterized severity of imprint, an operational mode, environmental conditions, and other factors. Imprint management techniques may increase the robustness, accuracy, or efficiency with which a memory system, or components thereof, can operate in the presence of conditions associated with memory cell imprinting.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: August 17, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Shashank Bangalore Lakshman, Jonathan D. Harms, Jonathan J. Strand, Sukneet Singh Basuta
  • Patent number: 11074988
    Abstract: Apparatus and methods for debugging on a host and memory device include an example apparatus comprising a memory device having an array of memory cells. Sensing circuitry is coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to perform logical operations on the memory device. A controller is coupled to the array and sensing circuitry, the controller is configured to control performance of the logical operations. An interface is configured to receive a debugging indication and to cause the controller to halt a logical operation on the memory device.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: July 27, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Shawn Rosti
  • Patent number: 11062077
    Abstract: Bit-reduction in a verification processes for memory arrays is disclosed. Properties are determined for verification of a circuit that includes a memory array. Circuit data for the circuit is received in a verification environment. When it is determined that the circuit includes a memory array, an address for the memory array is sampled as part of a read operation during verification for the circuit. A determination may be made that the circuit is in compliance with a property of the properties based at least in part on compliance of the read operation with a predetermined model. The sampling of the address replicates a delay expected in physical read operation of the memory array, but with reduced bits communicated or generated per cycle in the verification process because output data is not sampled contrasting the physical read operation.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: July 13, 2021
    Assignee: Amazon Technologies, Inc.
    Inventor: Max Chvalevsky
  • Patent number: 11062068
    Abstract: An electronic computer-aided design tool includes a design module and a printed electronics printer coupled to the design module. The design module determines one or more design specifications for an electronic device. The printed electronics printer produces one or more printed electronics prototypes of the electronic device based at least in part on at least on at least one of the design specifications. In some embodiments, the electronic computer-aided design tool includes a prototype testing unit that tests prototypes made by the printed electronics printer.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: July 13, 2021
    Inventor: Hanan Potash
  • Patent number: 11062776
    Abstract: A nonvolatile memory device includes a memory cell array including a plurality of memory cells that are programmed based on a high voltage, a high voltage generator to generate the high voltage by boosting an input voltage based on a pumping clock, a pumping clock generator to generate the pumping clock, a high voltage detector to generate a detection signal by comparing an adjustment voltage with a reference voltage, a programming current controller to adjust a programming current flowing through each of selected memory cells of the plurality of memory cells; and a control logic to adjust a frequency of the pumping clock and a current driving capability of the programming current based on the detection signal during a programming period with respect to the selected memory cells. The detection signal includes information indicating whether the high voltage reaches to a target voltage.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: July 13, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Jin Shin, Ji-Sung Kim, Ho Young Shin, Myeong Hee Oh
  • Patent number: 11055309
    Abstract: A method comprising receiving, from a first enterprise system, a series of first language commands written in a first language to control a first data flow of first data, the first data being from a first and a second data source, the first series of first language commands indicating first functions to be performed including collection of first data, storage of the first data into a first data warehouse, and application of one or more first applications on the stored first data, the first and second data sources being unrelated to each other and being remote from the first enterprise system and the data warehouse, translating the series of first language commands into first translated commands that may be provided to the first and second data sources as well as the first data warehouse to control the first data flow.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: July 6, 2021
    Assignee: Datacoral, Inc.
    Inventor: Raghotham Murthy
  • Patent number: 11048597
    Abstract: Exemplary methods, apparatuses, and systems include a controller detecting a trigger to configure a memory. The memory includes a plurality of dice, including two or more spare dice. The controller accesses each die via one of a plurality of channels. The controller accesses a first spare die via a first channel and the second spare die via a second channel. In response to detecting the trigger, the controller maps a plurality of logical units to the plurality of dice, excluding the two spare dice. The mapping includes mapping each logical unit of the plurality of logical units across multiple dice of the plurality of dice, such that a first half of the plurality of logical units reside on dice accessible via channels other than the first channel and a second half of the plurality of logical units reside on dice accessible via channels other than the second channel.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: June 29, 2021
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Justin Eno, Samuel E. Bradshaw
  • Patent number: 11037623
    Abstract: A semiconductor memory device includes a memory cell array, a storage circuit suitable for storing pattern data, a data input circuit suitable for receiving normal write data from an external device, a comparison circuit suitable for comparing the pattern data with the normal write data based on a pre-read control signal, and generating a comparison signal corresponding to the comparison result, and a write circuit suitable for writing the pattern data to the memory cell array based on a pre-write control signal, and writing some of the normal write data to the memory cell array based on a normal write control signal and the comparison signal.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: June 15, 2021
    Assignee: SK hynix Inc.
    Inventors: Chang-Yong Ahn, Han-Suk Ko
  • Patent number: 11022647
    Abstract: A method of reconfiguring a current debug configuration of a debug unit connected to a peripheral circuit on an integrated circuit chip. The method comprises the debug unit collecting debug data of the peripheral circuit and outputting the debug data in a message stream. The debug unit receives a debug reconfiguration command. The debug unit transmits an indication of the current debug configuration, then reconfigures the current debug configuration to a new debug configuration in accordance with the debug reconfiguration command, then transmits an indication of the new debug configuration. The indication of the current debug configuration and the indication of the new debug configuration are transmitted adjacent to the debug data in the message stream.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: June 1, 2021
    Assignee: MENTOR GRAPHICS CORPORATION
    Inventors: Andrew Brian Thomas Hopkins, Andrew James Bower, Michael Jonathan Thyer
  • Patent number: 10971243
    Abstract: A BIST engine configured to store a per pattern based fail status during memory BIST run and related processes thereof are provided. The method includes testing a plurality of patterns in at least one memory device and determining which of the plurality of patterns has detected a fail during execution of each pattern. The method further includes storing a per pattern based fail status of each of the detected failed patterns.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: April 6, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Aravindan J. Busi, John R. Goss, Paul J. Grzymkowski, Krishnendu Mondal, Kiran K. Narayan, Michael R. Ouellette, Michael A. Ziegerhofer
  • Patent number: 10942213
    Abstract: The device for testing a motherboard includes a power adapter, a first DC-DC converter, and a microcontroller. The power adapter converts an AC input voltage to a DC supply voltage. The DC-DC converter converts the DC supply voltage to a DC voltage at a channel coupled to the motherboard, and adjusts a voltage level of the DC voltage in response to a control signal. The DC-DC converter is enabled according to an enable signal. The microcontroller is configured to provide the control signal and the enable signal, and to determine whether a power on/off operation of the motherboard is normal. The microcontroller is configured to perform a test procedure on the motherboard to obtain a workable voltage range of the motherboard. The voltage level of the DC voltage in the test procedure is dynamically adjusted within a predetermined range around a nominal voltage value of the DC voltage.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: March 9, 2021
    Assignee: DFI Inc.
    Inventors: Chia-yi Chang, Chien-Ming Yu, Jheng-Rong Cai
  • Patent number: 10935601
    Abstract: A falling edge controller includes a controller having an inverted TCK (Test Clock) input, a TMS (Test Mode Select) input, a shift register control output, an update register control output, and a shift output; a shift register having a TDI (Test Data In) input, a shift register control input coupled to the shift register control output, address inputs, a select input, address and select outputs, and a TDO (Test Data Out) output; an update register having address and select inputs coupled to the address and select outputs, an update register control input coupled to the update register control output, address outputs coupled to the address inputs, and a select output coupled to the select input; and address circuitry having address inputs coupled to the address outputs, and having an enable output.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: March 2, 2021
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 10902933
    Abstract: In various examples, a test system is provided for executing built-in-self-test (BIST) according to JTAG and IEEE 1500 on chips deployed in-field. Hardware and software selectively connect onto the IEEE 1500 serial interface for running BIST while the chip is being used in deployment—such as in an autonomous vehicle. In addition to providing a mechanism to connect onto the serial interface, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making BIST possible in deployment. Furthermore, some embodiments include components configured to store functional states of clocks, power, and input/output prior to running BIST, which permits restoration of the functional states after the BIST.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: January 26, 2021
    Assignee: NVIDIA Corporation
    Inventors: Anitha Kalva, Jue Wu
  • Patent number: 10896139
    Abstract: The present disclosure describes technologies and techniques for use by a data storage controller (such as a non-volatile memory (NVM) controller) to emulate hardware registers in software and/or firmware. In illustrative examples, an arbiter of the NVM controller arbitrates inbound register accesses from a host. Regular register accesses from the host are directed by the arbiter along a regular hardware read path within the NVM controller to physical memory registers. Other transactions (e.g. writes to, or reads from, an undefined or reserved address space) are instead directed by the arbiter to the processor of the NVM controller for handling by software running on the processor (and/or by firmware). In this manner, new hardware registers added to an NVM standard may be implemented by software and/or firmware rather than hardware. Hence, the NVM controller may comply with new standard requirements without changing the hardware. NVMe examples are provided.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: January 19, 2021
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Shay Benisty, Elkana Richter, Alexey Martynenko
  • Patent number: 10891410
    Abstract: In an example embodiment, a computer-implemented method is provided for receiving an integrated circuit design, wherein the integrated circuit design comprises at least one position in violation of one or more design rules associated with the integrated design, identifying one or more design patterns at the at least one violating position, generating one or more pattern graphs for the one or more design patterns, extracting a system on chip design for transformation into a block graph, and. comparing the block graph with each of the one or more pattern graphs to determine whether the at least one violating position is cleared. In circumstances where a match is found between the block graph and the each of the one or more pattern graphs, the computer-implemented method further comprises changing the one or more design patterns and repeating the step of comparing until there is no further match found.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: January 12, 2021
    Assignee: Synopsys, Inc.
    Inventors: Chin-Hsiung Hsu, Philip Hui-Yuh Tai, Sheng-Wei Yang, Guo-Ting Wang