Abstract: A service oriented architecture (SOA) provides on-demand service call debugging and call stack tracing. The service call (e.g., an API) includes a new field and optional signature value. The field is a ‘debug-requested’ field, and the optional field is a unique call-id signature. The service provider can enable debugging in accordance with the debug-requested field for this service call, and tag all debugged data with the unique call-id. If it is necessary to call other services to fulfill the request, then the service can pass the ‘debug-requested’ field and the ‘unique id’ in the call to that service. Using this mechanism, detailed debugging can be supported across an entire stack for only those requests that need it and the performance/latency impact of having debugging enabled only applies to the subset of calls which need debugging.

Abstract: Methods, devices, and systems for detecting return-oriented programming (ROP) exploits are disclosed. A system includes a processor, a main memory, and a cache memory. A cache monitor develops an instruction loading profile by monitoring accesses to cached instructions found in the cache memory and misses to instructions not currently in the cache memory. A remedial action unit terminates execution of one or more of the valid code sequences if the instruction loading profile is indicative of execution of an ROP exploit involving one or more valid code sequences. The instruction loading profile may be a hit/miss ratio derived from monitoring cache hits relative to cache misses. The ROP exploits may include code snippets that each include an executable instruction and a return instruction from valid code sequences.

Abstract: Some embodiments include apparatuses and methods having a component to change a value of a bit among a number of M bits of information when the M bits have the same value and when M exceeds a selected value. At least one of such embodiments can include a transmitting component to provide the information to a connection. At least one of such embodiments can include a receiving component to receive the information from the connection. In at least one of such embodiments, the selected value can include a maximum number of consecutive bits having the same value that such a receiving component can be configured to receive. Other embodiments including additional apparatuses and methods are described.

Abstract: There is provided a low-cost electronic control unit that is capable of performing its hardware check every start and stop of the electronic control unit. A monitoring and control circuit section that is an integrated circuit element built in the electronic control unit includes a self-test circuit configured with a built-in self-test control block, scan chain circuits and mask circuitry, and performs a self-test using the built-in self-test control block and a partial combination of the scan chain circuits at start of the operation. In the shipment inspection of the integrated circuit element alone, an external test is performed by a checker microprocessor using an entire combination of the scan chain circuits. Thus, the electronic control unit of low-cost configuration is capable of performing a scan test by making use of part of the scan chain circuits designed for the component inspection.

Abstract: Testing of die on wafer is achieved by; (1) providing a tester with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, (2) providing die on wafer with the capability of externally communicating JTAG test signals using simultaneously bidirectional transceiver circuitry, and (3) providing a connectivity mechanism between the bidirectional transceiver circuitry's of the tester and a selected group or all of the die on wafer for communication of the JTAG signals.

Abstract: A control test point (CTP) of an integrated circuit scan chain includes a scan latch and an integrated clock gate (ICG). The ICG includes clock, functional enable (FE) and scan enable (SE) inputs, and a gated clock output. The ICG can respond to an SE input active state, in a serial scan mode allowing the gated clock output to change. The ICG can also be operated in a scan capture mode, responding to an SE input inactive state, in which the gated clock output is inhibited from changing in response to a low FE input level. The ICG's gated clock output is coupled to the scan latch clock input, which holds its data output at a fixed level in response to ICG's gated clock output being inhibited from changing during the scan capture operation.

Abstract: Systems and methods are provided for a data storage cell. A pass gate, controlled by one or more clock signals, is configured to selectively pass data to a keeper circuit. A multiplexer device is disposed in the keeper circuit and is configured to select one of the data that is passed to the keeper or a scan input.

Abstract: A driving method for liquid crystal display (LCD) panel includes the following steps: A. sending feedback signals to a monitoring module before timing control modules (T-CONs) sends driving signals to drive display of the LCD panel; B. generating control signals when the monitoring module receives the feedback signal of each of the T-CONs, and then simultaneously sending the control signals to each of the T-CONs; C. sending a driving signal to drive display of the LCD panel when each of the T-CONs receives the control signal.

Abstract: The disclosure provides a voltage testing device and a method. A voltage testing device includes a PCB, a computer, and a detecting chip. The PCB includes a CPU socket, a signal producing chip, and a voltage regulator. The computer sets predetermined data. The detecting chip is inserted in the CPU socket. The detecting chip includes a reading module, a converting module, a sending module, and a control module. The signal producing chip sends a start-up signal to the control module. The converting module converts the predetermined data to SVID data. The sending module sends the SVID data to the voltage regulator. The voltage regulator sends a CPU voltage to the CPU socket. The voltage value testing device calculates a value of the CPU voltage to determine if the value of the CPU voltage associates with a voltage corresponding to the predetermined data.

Abstract: A system and method for dynamically modifying scheduling of scan operations for a system under test includes a processing module configured to apply input test data to the system under test based on the scan operations via a test access port and a scheduler adapted to provide the processing module with scheduling for the plurality of scan operations. The scheduler includes a circuit model of the system under test. The circuit model includes at least one attribute providing enhancing information for at least a portion of the system under test. The scheduler is adapted to schedule the scan operations based on the circuit model and to modify the schedule based on the at least one attribute. The processing module is configured to receive the modified scheduled scan operations and to apply the input test data to the system under test based on the modified scheduled scan operations.

Abstract: A method of monitoring operations of a set of ICs. The method loads a first set of configuration data into a first IC for configuring a group of configurable circuits of the first IC to perform operations of a user design. The method receives a definition of an event based on values of a set of signals in the user design and a set of corresponding actions to take when the event occurs. The set of signals includes at least one signal received from a second IC. The method generates an incremental second set of configuration data based on the definition of the event and the set of corresponding actions. While the first IC is performing the operations of the user design, the method loads the incremental second set of configuration data into the first IC and monitors the signals received from the second IC at the first IC.

Abstract: First and second scan channels each comprise a plurality of scannable latches that apply input to and receive output from logic circuits on a chip under test. First input is scanned into the first scan channel and second input is scanned into the second scan channel. Output from the first scan channel is hashed using a first XOR on the first scan channel and output from the second scan channel is hashed using a first XOR on the second scan channel. Output from the first XOR on the first scan channel is hashed using a second XOR on the first scan channel. A rotator creates adjustment data from the output from the second XOR on the first scan channel. The adjustment data and output from the first XOR on the second scan channel are hashed using a second XOR on the second scan channel.

Abstract: The present disclosure describes novel methods and apparatuses for directly accessing JTAG Tap domains that exist in a scan path of many serially connected JTAG Tap domains. Direct scan access to a selected Tap domain by a JTAG controller is achieved using auxiliary digital or analog terminals associated with the Tap domain and connected to the JTAG controller. During direct scan access, the auxiliary digital or analog terminals serve as serial data input and serial data output paths between the selected Tap domain and the JTAG controller.

Abstract: A method of testing a plurality of DUTs includes providing a plurality of shift registers to test a plurality of cores in each DUT, supplying test input data, a test mode input signal, a test clock signal, and a test reset signal to the shift registers and cores, receiving a master bit, a first control value, and a second control value, based on the test input data and the test mode input signal, according to the test clock signal and the test reset signal, selecting at least one core and a test method, according to the first control value, selecting a target DUT according to the master bit or the second control value, simultaneously testing and debugging the selected core according to the test method, and outputting the test data output of the target DUT to check a result of the testing when an output enable signal is received.

Abstract: A storage medium including a processing module and a cell array. The processing module receives test data according to a write command. The cell array stores the test data. The processing module receives verify data according to a comparison command, reads the test data stored in the cell array to generate access data, and compares the access data with the verify data to generate a compared report.

Abstract: First and second scan channels each comprise a plurality of scannable latches that apply input to and receive output from logic circuits on a chip under test. First input is scanned into the first scan channel and second input is scanned into the second scan channel. Output from the first scan channel is hashed using a first XOR on the first scan channel and output from the second scan channel is hashed using a first XOR on the second scan channel. Output from the first XOR on the first scan channel is hashed using a second XOR on the first scan channel. A rotator creates adjustment data from the output from the second XOR on the first scan channel. The adjustment data and output from the first XOR on the second scan channel are hashed using a second XOR on the second scan channel.

Abstract: A method includes: decoding an instruction a first time to obtain a first decoded instruction; decoding the instruction a second time to obtain a second decoded instruction; comparing at least a portion of the first decoded instruction to at least a portion of the second decoded instruction; and when the at least a portion of the first decoded instruction matches the at least a portion of the second decoded instruction, executing the instruction.

Abstract: The present disclosure relates to a method for verifying a digital design using a computing device. The method may include determining one or more tests associated with verifying the digital design and generating, using the computing device, a verification result by performing one or more verification runs on the digital design. The method may further include merging coverage data generated by the one or more verification runs and ranking the one or more tests based upon, at least in part, a first verification run having a first configuration and a second verification run having a second configuration, wherein the first and second configurations differ.

Abstract: A method for performing trace based measurement for a plurality of CPUs in parallel includes receiving a signal to perform a CPU parallel trace mode and enabling a parallel trace mode multiplexer to output all trace data, representing all data writes to the local memory, to a single observation unit. In one embodiment, the single observation unit is a processor observation block (POB), and in another embodiment, a bus observation block (BOB). If the single observation unit is a BOB, then the parallel trace mode multiplexer first routes the local memory data trace through a BOB adaptation layer to convert the CPU trace output data to data which is understood by the BOB.

Abstract: A power-on self-test circuit and a pattern generation circuit are provided. The power-on self-test circuit includes a selection circuit and a comparator circuit. The selection circuit selects, instead of an external pin group corresponding to a test access port, an output of the pattern generation circuit when a self-diagnosis execution signal is asserted and supplies a test pattern generated by the pattern generation circuit to a built-in self-test circuit. The comparator circuit compares a test result of a circuit-under-test with an expected value. By asserting the self-diagnosis execution signal in this manner, the semiconductor integrated circuit mounted on a user system executes BIST.

Abstract: A test method which tests a processing device includes: obtaining a maximum number of processing units with which the processing device as a test target can simultaneously parallel process a plurality of threads; specifying a number of threads, causing the processing device as the test target to parallel process the threads, and obtaining a processing time corresponding to the number of threads; and outputting information indicating that the processing device as the test target is normal when the number of threads for which the processing time is more than or equal to a threshold matches the maximum number of processing units which can simultaneously parallel process, or outputting information indicating that the processing device as the test target is abnormal when the number of threads does not match.

Abstract: Subject matter disclosed herein relates to a system of one or more processors that includes persistent memory.

Abstract: Methods and apparatus for output of high-bandwidth debug data/traces in electronic devices using embedded high-speed debug port(s). Debug data is received from multiple blocks and buffered in a buffer. The buffer's output is operatively coupled to one or more high-speed serial I/O interfaces via muxing logic during debug test operations. The buffered data is encoded as serialized data and sent over the one or more high-speed serial I/O interfaces to a logic device that receives serialized data and de-serializes it to generate parallel debug data that is provided to a debugger. The buffer may be configured as a bandwidth-adapting buffer that facilitates transfer of debug data that is received at a variable combined data rate outbound via the one or more high-speed serial I/O interfaces at a data rate corresponding to the bandwidth of the serial I/O interfaces.

Abstract: A test apparatus for a server includes a first connection unit coupled to a mother board of the server, a second connection unit coupled to a device under test, a data transmission unit, a processing unit, and a network unit. According to a selection signal, the data transmission unit switches one of data transmission modes to perform data transmission between the first connection unit and the second connection unit. The processing unit controls the data transmission unit to perform a first test program for the mother board through the first connection unit, or perform a second test program for the device under test through the first connection unit and the second connection unit. The network unit receives a control signal generated by an external apparatus, so that the external apparatus controls the processing unit to perform the first test program and the second test program through the network unit.

Abstract: The subject matter described herein includes methods, systems, and computer readable media for efficiently scrambling data in high speed communications networks. One exemplary method includes, in a network equipment test device, providing a scrambler for scrambling data to be transmitted to a device under test. Scrambling the data includes separating a scrambling algorithm into a scramble key portion and a data portion. Scrambling the data further includes pre computing and storing the scramble key portion. Scrambling the data further includes precomputing and storing the data portion. Scrambling the data further includes logically combining the precomputed scramble key portion with the precomputed data portion to produce a data bus width scrambled output data. The method further includes transmitting the scrambled output data over a network to the device under test.

Abstract: Roughly described, an integrated circuit chip comprises a plurality of peripheral circuits, each peripheral circuit connected to a respective debug unit; a shared hub; and between each respective debug unit and the shared hub, a single physical interface configured to transport both configuration data and event data, wherein the interface is configured such that if an event occurs while the interface is transporting configuration data, the interface interrupts the transport of the configuration data in order to transport the event data.

Abstract: A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select register that stores a value that selects a protocol from among the plurality of protocols to become an active protocol; and a state machine accessible to the communications interface, the state machine used to control the exchange of information through the communications interface according to the active protocol. The active protocol is used by the communications interface to exchange information while the remaining protocols of the plurality of protocols remain inactive. The state machine sequences through a series of states that cause the communications interface to operate according to the active protocol, and that are designated as inert sequences under the remaining protocols.

Abstract: An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and de-bug of a part/platform under test.

Abstract: Roughly described, a method of controlling transportation of debug data on an integrated circuit chip. The chip has a shared hub and a number of peripheral circuits. Each peripheral circuit is connected to a respective debug unit, and between each debug unit and the shared hub there is an interface configured to transport data messages over each of a number of prioritized flows. In the method, still roughly described, control data for controlling the state of a debug unit is transported on a priority flow having a first priority, and debug data output by a debug unit as a result of debugging the peripheral circuit connected to that debug unit is transported on a flow having a second priority, the first priority being higher than the second priority.

Abstract: A method is provided for performing a self-test on a memory device in a test mode, where the memory device includes a universal flash storage (UFS) link layer and a UFS physical layer having a transmitting unit and a receiving unit. The method includes generating a first signal; sending the first signal from a test unit through the UFS link layer to the transmitting unit in the UFS physical layer to be transmitted to the receiving unit; receiving a second signal at the test unit from the receiving unit in the UFS physical layer through the UFS link layer, the second signal being the first signal received by the receiving unit; and testing an operation performed by at least one of the UFS physical layer and the UFS link layer based on the first signal and the second signal.

Abstract: A coherence system includes a storage array that may store duplicate tag information associated with a cache memory of a processor. The system may also include a pipeline unit that includes a number of stages to control accesses to the storage array. The pipeline unit may pass through the pipeline stages, without generating an access to the storage array, an input/output (I/O) request that is received on a fabric. The system may also include a debug engine that may reformat the I/O request from the pipeline unit into a debug request. The debug engine may send the debug request to the pipeline unit via a debug bus. In response to receiving the debug request, the pipeline unit may access the storage array. The debug engine may return to the source of the I/O request via the fabric bus, a result of the access to the storage array.

Abstract: Apparatus and techniques for performing JTAG testing on production devices and systems through industry standard interfaces. The devices employ processors configured to receive packetized test input data from a tester over a standard communication interface such as a USB or Ethernet port and perform associated testing operations defined by the test input data, such as JTAG-compliant testing. This is facilitated, in part, via use of a bridge and one or more DFx handlers, with the bridge operating as an interface between the DFx handlers and a bus and/or interconnect over which test input and result data is transferred via the standard communication interface. The techniques enable testing such as JTAG testing to be performed on fully-assembled devices and systems without requiring the use of dedicated test or debug ports.

Abstract: A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device waits for a synchronization point sequence. Upon detecting the synchronization point sequence, the second remote device implements a predetermined feature set and synchronizes itself to the state diagram at a common point as the host device and first remote device.

Abstract: Embodiments of the present invention provide a test and measurement instrument that displays acquired data on a logarithmic scale without intensity banding. The test and measurement instrument processes the acquired data before it is displayed by appending pseudo-random sub-LSB (least significant bit) values to it. When the processed acquired data is displayed on a logarithmic scale, the pseudo-random sub-LSB values fill in the gaps between discrete power levels, thereby eliminating intensity banding and providing a smooth, visually pleasing display.

Abstract: A memory subsystem includes a test engine coupled to a memory controller that can provide memory access transactions to the memory controller, bypassing a memory address decoder. The test engine hardware is configurable for different tests. The test engine identifies a range of addresses through which to iterate a test sequence in response to receiving a software instruction indicating a test to perform. For each iteration of the test, the test engine, via the selected hardware, generates a memory access transaction, selects an address from the range, and sends the transaction to the memory controller. The memory controller schedules memory device commands in response to the transaction, which causes the memory device to execute operations to carry out the transaction.

Abstract: A memory subsystem includes a test engine coupled to a memory controller that can provide memory access transactions to the memory controller, bypassing a memory address decoder. The test engine receives a command to cause it to generate transactions to implement a memory test. The command identifies the test to implement, and the test engine generates one or more memory access transactions to implement the test on the memory device. The test engine passes the transactions to the memory controller, which can schedule the commands with its scheduler. Thus, the transactions cause deterministic behavior in the memory device because the transactions are executed as provided, while at the same time testing the actual operation of the device.

Abstract: An information processing apparatus includes an external tool unit configured to provide a man-machine interface to a debugging user; and a microcontroller. The microcontroller includes: a CPU section configured to execute a program as a debugging target in a response to a first clock signal, wherein a clock rate of the first clock signal is changed in response to an instruction from the CPU section; a first transmitting section configured to transmit debugging data to the external tool unit in response to the first clock signal; a second transmitting section configured to transmit the debugging data to the external tool unit in response to a second clock signal which is different from the first clock signal; and a receiving section configured to receive data transmitted from the external tool unit.

Abstract: A programmable interface-based validation and debug system includes, for example, a test connector that is arranged to communicatively couple a design under test to the test fixture. A programmable logic interface is communicatively coupled to the test connector and is arranged to receive a downloadable test bench, where the downloadable test bench is arranged to apply test vectors from a first set of test vectors to a first test control bus. A multiplexer is arranged to selectively couple one of the first test control bus and a second test control bus to a shared test bus that is coupled to the test connector, where the second test control bus is arranged to apply test vectors from a second set of test vectors provided by, for example, a debugger that is operated by a human.

Abstract: A debug controller monitors a tip-ring-ring-shield (TRRS) socket, within a form factor device, to detect whether a debug unit is transmitting a request for a TRRS socket debug connection. The form factor device also includes a system on chip (SoC), a switch, and an audio codec. The SoC includes the debug controller and a software debug interface. The switch couples a right audio lead and left audio lead of the TRRS socket to the audio codec. If the debug controller detects the request from the debug unit, then the debug controller instructs the switch to establish a TRRS socket debug connection. The switch establishes the TRRS socket debug connection by coupling right audio lead and left audio lead to the software debug interface instead of the audio codec. This establishment of the TRRS socket debug connection eliminates the need for manual configuration of the TRRS socket debug connection.

Abstract: Methods, systems, and apparatuses are presented that remove BIST intrusion logic from critical timing paths of a microcircuit design without significant impact on testing. In one embodiment, BIST data is multiplexed with scan test data and serially clocked in through scan test cells for BIST testing. In another embodiment, BIST data is injected into the feedback path of one or more data latches. In a third embodiment, BIST data is injected into the result data path of a multi-cycle ALU within an execution unit. In each embodiment, BIST circuitry is eliminated from critical timing paths.

Abstract: Techniques for processing signal information from a high speed communication bus. The techniques includes determining spatial regions on an eye characterized by a start point, an end point, a middle point, a left point, and a right point. The start point is a beginning of an eye opening at a reference voltage. The end point is at an ending of eye opening at the reference voltage. The middle point is at a center point of eye opening at the reference voltage. The left point is a left sampling location characterized by a minimum setup time requirement, and the right point is a right sampling location characterized by a minimum hold time requirement. Determining the points is based on shifting a DQS position and a DQ position and running a plurality of memory built-in self test (BIST) engines and a plurality of results of BIST tests.

Abstract: Methods and apparatus are provided that facilitate debugging operations for components in dynamic power domains. In an embodiment, an integrated circuit includes hardware sectors associated with observability circuits served by a debug data bus of a debug circuit. A controlled sector residing in a dynamically-controlled power domain may be turned off while the power domain of another sector remains on. To continue to have debug observability all the way through and after these power events, a debug data register is configured to provide data, such as configuration and/or programming data, to the observability circuit of the controlled sector via the debug data bus. A shadow register is configured to capture the data provided to the controlled sector's observability circuit. The shadow register data is used upon restoring power to the controlled sector to restore the controlled sector's observability circuit to a state when the controlled sector was previously powered on.

Abstract: Methods and apparatus are provided that facilitate debugging operations for components that may include different power domains. In an embodiment, an integrated circuit (IC) includes a plurality of hardware sectors, each hardware sector associated with a debug observability circuit that is served by a debug data bus of a debug circuit. The plurality of hardware sectors includes a controlled sector residing in a dynamically-controlled power domain that may be turned off while the power domain of another sector remains on. A selectively switchable data bus component is configured to couple the debug observability circuit associated with the controlled sector to the debug data bus when the power to the controlled sector is on and to switch to bypass the debug observability circuit associated with the controlled sector when the power to the controlled sector is not on.

Abstract: A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device determines whether to initialize to a standard protocol or to an advanced protocol. Upon determining to initialize to the advanced protocol, the second remote device then waits for a synchronization point sequence.

Abstract: The present invention relates to a home appliance diagnosis system and to a method for operating same, wherein product information is output in a predetermined signal sound by a home appliance product, and the signal sound is transmitted via a communication network connected to a remote service center to enable the service center to easily check the state of the home appliance product. In addition, the product information is encoded into a predetermined format and modulated to enable sound to be outputted by the home appliance product, thereby preventing noise or signal errors. The present invention enables stable signal modulation and accurate sound output, and enables the easy recovery of the sound transmitted to the service center via the communication network.

Abstract: A system on chip is provided which performs a built-in self-test operation using an error access pattern. The system on chip includes a master device and a slave device. A bus is configured to transfer an instruction from the master device to the slave device. A built-in instruction capture circuit is configured to receive and store the instruction. The built-in instruction capture circuit stores the instruction as the error access pattern when an error occurs in the slave device due to the instruction.

Abstract: A system for providing a test result from an integrated circuit to a status analyzer. A deserializer is configured to deserialize, into data frames, messages received from the integrated circuit. The messages include the test result and are received from the integrated circuit in a serial data format. A frame sync module is configured to synchronize the data frames, output the synchronized data frames, and generate a clock signal. A gateway module is configured to receive the synchronized data frames from the frame sync module in accordance with the clock signal, convert signal levels and signal timings associated with the synchronized data frames from a first format used by the frame sync module to a second format used by the status analyzer, and provide the synchronized data frames to the status analyzer in accordance with the signal levels and the signal timings in the second format used by the status analyzer.

Abstract: An apparatus and method for error management in an integrated circuit system are presented. An error management unit (EMU) apparatus manages critical and non-critical errors that may be masked or non-masked. An EMU includes an EMU state machine, having a BOOT state, a CONFIG state, a FUNCT state, a WARNING state and an ERROR state. The method discloses transitions in the EMU state machine. While in the ERROR state an error reaction may be applied. The objective of the error reaction is to recover errors by software and hardware means. The EMU may further appropriately alert the system while in ERROR state and therefore be used as a safety mechanism permitting to collect error signals issued by fault detector units and can further cause action on faulty units for recovery purposes.

Abstract: The present invention describes a method and system for optimizing a test flow within each ATE (Automated Test Equipment) station. The test flow includes a plurality of test blocks. A test block includes a plurality of individual tests. A computing system schedule the test flow based one or more of: a test failure model, test block duration and a yield model. The failure model determines an order or sequence of the test blocks. There are at least two failure models: independent failure model and dependant failure model. The yield model describes whether a semiconductor chip is defective or not. Upon completing the scheduling, the ATE station conducts tests according to the scheduled test flow. The present invention can also be applied to software testing.

Abstract: A method and apparatus for authenticating a bitstream used to configure programmable devices are described. In an example, the bitstream is received via a configuration port of the programmable device, the bitstream including instructions for programming configuration registers of the programmable device and at least one embedded message authentication code (MAC). At least a portion of the instructions is initially stored in a memory of the programmable device without programming the configuration registers. At least one actual MAC is computed based on the bitstream using a hash algorithm. The at least one actual MAC is compared with the at least one embedded MAC, respectively. Each instruction stored in the memory is executed to program the configuration registers until any one of the at least one actual MAC is not the same as a corresponding one of the at least one embedded MAC, after which any remaining instructions in the memory are not executed.