Built-in Hardware For Diagnosing Or Testing Within-system Component (e.g., Microprocessor Test Mode Circuit, Scan Path) Patents (Class 714/30)
  • Patent number: 8796047
    Abstract: In one aspect, a method of enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging is disclosed. Also provided is an arrangement for implementing the inventive method. In another aspect, a method and on-chip controller are disclosed for enhancing semiconductor chip process variability and lifetime reliability through a three-dimensional (3D) integration applied to electronic packaging. Also provided is an on-chip reliability/variability controller arrangement for implementing the inventive method. In yet another aspect, base semiconductor chips, each comprising a plurality of chiplets, are manufactured and tested. For a base semiconductor chip having at least one non-functional chiplet, at least one repair semiconductor chiplet is vertically stacked. A functional multi-chip assembly is formed, which provides the same functionality as a base semiconductor chip in which all chiplets are functional.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: August 5, 2014
  • Patent number: 8799713
    Abstract: A built-in self-test (BIST) diagnostic system tests the execution of a processor. The processor is arranged to execute a normal application for controlling a process that is external to the processor. The normal execution is executed in normal execution timeslots that have idle timeslots that are interspersed in time between the normal execution timeslots. A BIST controller is arranged to detect the presence of an idle timeslot in the execution of the processor and to use a scan chain to scan-in a first test pattern for a test application for testing the processor. The first test pattern is executed by the processor during the detected idle timeslot and a first result pattern generated by the execution of the first test pattern is scanned-out. The scanned-out first test pattern is evaluated to determine the presence of an error. The first test pattern application is conditionally interruptible.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: August 5, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Swathi Gangasani, Srinivasulu Alampally, Prohor Chowdhury, Srinivasa B S Chakravarthy, Padmini Sampath, Rubin Ajit Parekhji
  • Patent number: 8799712
    Abstract: Testing of an electrical device is achieved by providing a test access mechanism within the device that can receive scan frames from an external tester. The received scan frames contain stimulus data to be applied to circuitry within the device to be tested, a command for enabling a test control operation, and a frame marker bit to indicate the end of the scan frame pattern. The inputting of scan frames can occur continuously and simultaneous with a commanded test control operation.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: August 5, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 8799715
    Abstract: In one embodiment, an SOC includes multiple components including a CPU complex and one or more non-CPU components such as peripheral interface controllers, memory controllers, media components, etc. The SOC also includes an SOC debug control unit, which is coupled to receive detected debug events from the components. Each component may include a local debug control unit that is configured to monitor for various debug events within that component. The debug events may be specific to the component. The local debug control units may transmit detected events to the SOC debug control unit. The SOC debug control unit may detect one or more events from one or more components, and may halt the components of the SOC responsive to detecting the selected events.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: August 5, 2014
    Assignee: Apple Inc.
    Inventors: Manu Gulati, James D. Ramsay, Erik P. Machnicki, Jianlin Yu
  • Publication number: 20140215269
    Abstract: Systems, methods, and machine-readable and executable instructions are provided for operating a test infrastructure simulation. Operating a test infrastructure simulation can include executing a test on a number of units under test (UUT) coupled to a test infrastructure and determining capabilities of the test infrastructure based on results of the test executed on the number of UUTs coupled to the test infrastructure.
    Type: Application
    Filed: January 28, 2013
    Publication date: July 31, 2014
    Applicant: Hewlett-Packard Development Company, L.P.
    Inventor: Oh Sung
  • Patent number: 8793546
    Abstract: An integrated circuit comprises scan test circuitry and additional internal circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a plurality of scan chains, with each such scan chain comprising a plurality of flip-flops configurable to operate as a serial shift register. The plurality of scan chains are arranged in sets of two or more parallel scan chains. The scan test circuitry further comprises multiplexing circuitry, including a plurality of multiplexers each associated with a corresponding one of the sets of parallel scan chains and configured to multiplex scan test outputs from the parallel scan chains within the corresponding one of the sets of parallel scan chains. In one embodiment, one or more of the sets of parallel scan chains comprise respective pairs of parallel scan chains with each such pair corresponding to a single original scan chain.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: July 29, 2014
    Assignee: LSI Corporation
    Inventors: Ramesh C. Tekumalla, Prakash Krishnamoorthy, Parag Madhani
  • Patent number: 8793366
    Abstract: A method for diagnosing networks including networks of field bus systems utilizes an arrangement for diagnosing the networks. The arrangement includes at least two field bus diagnostic apparatuses with each of the field bus diagnostic apparatuses being assigned to a corresponding field bus.
    Type: Grant
    Filed: November 6, 2009
    Date of Patent: July 29, 2014
    Assignee: Trebing & Himstedt Prozessautomation GmbH & Co. KG
    Inventors: Stefan Trebing, Steffen Himstedt
  • Publication number: 20140208160
    Abstract: A segmented subsystem, for use within an automated test platform, includes a first subsystem segment including a first data sequencer configured to coordinate the execution of one or more instructions within the first subsystem segment. A second subsystem segment includes a second data sequencer configured to coordinate the execution of one or more instructions within the second subsystem segment.
    Type: Application
    Filed: January 24, 2013
    Publication date: July 24, 2014
    Applicant: LTX-Credence Corporation
    Inventors: WILLIAM A. FRITZSCHE, James Michael Jula, Timothy Alton, Russell Elliott Poffenberger, Michael E. Amy
  • Publication number: 20140208161
    Abstract: A scalable test platform includes a PCIe-based event fabric. One or more CPU subsystems are coupled to the PCIe-based event fabric and configured to execute an automated test process. One or more instrument subsystems are coupled to the PCIe-based event fabric and configured to interface one or more devices under test.
    Type: Application
    Filed: January 24, 2013
    Publication date: July 24, 2014
    Applicant: LTX-Credence Corporation
    Inventors: William A. Fritzsche, Jeffery D. Currin, Russell Elliott Poffenberger, Timothy Alton, Michael Gordon Davis
  • Patent number: 8788897
    Abstract: A path-based crosstalk fault model is used in conjunction with a built-in self-test (BIST) and software capability for automatic test pattern generation. The solution allows for test patterns to be generated that maximize switching activity as well as inductive and capacitive crosstalk. The path based fault model targets the accumulative effect of crosstalk along a particular net (“victim” path), as compared with the discrete nets used in conventional fault models. The BIST solution allows for full controllability of the target paths and any associated aggressors. The BIST combined with automatic test pattern generation software enables defect detection and silicon validation of delay defects on long parallel nets.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: July 22, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Nisar Ahmed, Corey Jason Goodrich, Xiao Liu, Chris Therrien
  • Patent number: 8788896
    Abstract: A scan chain lockup latch comprises at least one latching element and data input control circuitry configured to control application of data to a data input of the latching element responsive to a scan enable signal. The lockup latch is configured for coupling between first and second scan cells of a scan chain. The scan chain may be controllable between a scan shift mode of operation and a functional mode of operation responsive to the scan enable signal. The data input control circuitry may be configured to maintain the data input of the latching element at a constant logic value when the scan chain is in its functional mode of operation such that switching activity in the latching element is suppressed. The scan chain lockup latch and the associated scan chain may be implemented in scan test circuitry of an integrated circuit, for testing additional circuitry of that integrated circuit.
    Type: Grant
    Filed: January 11, 2012
    Date of Patent: July 22, 2014
    Assignee: LSI Corporation
    Inventor: Ramesh C. Tekumalla
  • Patent number: 8782468
    Abstract: Methods and apparatus relating to debugging complex multi-core and/or multi-socket systems are described. In one embodiment, a debug controller detects an event corresponding to a failure in a computing system and transmits data corresponding to the event to one of the other debug controllers in the system. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: July 15, 2014
    Assignee: Intel Corporation
    Inventors: Binata Bhattacharyya, Jayakrishna Guddeti, Keshavan K. Tiruvallur
  • Patent number: 8775881
    Abstract: Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: August 26, 2013
    Date of Patent: July 8, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Joe M. Jeddeloh
  • Patent number: 8768642
    Abstract: The present invention systems and methods facilitate configuration of functional components included in a remotely located integrated circuit die. In one exemplary implementation, a die functional component reconfiguration request process is engaged in wherein a system requests a reconfiguration code from a remote centralized resource. A reconfiguration code production process is executed in which a request for a reconfiguration code and a permission indicator are received, validity of permission indicator is analyzed, and a reconfiguration code is provided if the permission indicator is valid. A die functional component configuration process is performed on the die when an appropriate reconfiguration code is received by the die. The functional component configuration process includes directing alteration of a functional component configuration. Workflow is diverted from disabled functional components to enabled functional components.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: July 1, 2014
    Assignee: Nvidia Corporation
    Inventors: Michael B. Diamond, John S. Montrym, James M. Van Dyke, Michael B. Nagy, Sean J. Treichler
  • Patent number: 8769348
    Abstract: An electronic device capable of communicating with a plurality of servers includes a storage unit, a vibration unit, a control unit, and a communication unit. The storage unit stores a vibration threshold value. The vibration sensor senses a vibration magnitude of the electronic device. The control unit generates control signals and transmits the control signals to the servers via the communication unit to direct the servers to take certain actions to protect data when the vibration magnitude sensed by the vibration sensor is equal to or greater than the vibration threshold value.
    Type: Grant
    Filed: November 25, 2011
    Date of Patent: July 1, 2014
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Chao-Tsung Fan
  • Patent number: 8762801
    Abstract: A system includes a first device, a first storage element, a comparator and a second device. The first device is configured to test memory cells in an array of memory cells to detect defective memory cells. The defective memory cells include a first memory cell and a second memory cell. The first storage element is configured to store a first address of the first memory cell. The comparator is configured to compare a second address of the second memory cell to the first address.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: June 24, 2014
    Assignee: Marvell International Ltd.
    Inventors: Winston Lee, Albert Wu, Chorng-Lii Liou
  • Patent number: 8762779
    Abstract: A method for debugging a multi-core microprocessor includes causing the microprocessor to perform an actual execution of instructions and obtaining from the microprocessor heartbeat information that specifies an actual execution sequence of the instructions by the plurality of cores relative to one another, commanding a corresponding plurality of instances of a software functional model of the cores to execute the instructions according to the actual execution sequence specified by the heartbeat information to generate simulated results of the execution of the instructions, and comparing the simulated results with actual results of the execution of the instructions to determine whether they match. Each core outputs an instruction execution indicator indicating the number of instructions executed by the core each core clock. A heartbeat generator generates a heartbeat indicator for each core on an external bus that indicates the number of instructions executed by each core during each external bus clock cycle.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: June 24, 2014
    Assignee: Via Technologies, Inc.
    Inventors: Darius D. Gaskins, Jason Chen, Rodney E. Hooker
  • Publication number: 20140173342
    Abstract: A coherence system includes a storage array that may store duplicate tag information associated with a cache memory of a processor. The system may also include a pipeline unit that includes a number of stages to control accesses to the storage array. The pipeline unit may pass through the pipeline stages, without generating an access to the storage array, an input/output (I/O) request that is received on a fabric. The system may also include a debug engine that may reformat the I/O request from the pipeline unit into a debug request. The debug engine may send the debug request to the pipeline unit via a debug bus. In response to receiving the debug request, the pipeline unit may access the storage array. The debug engine may return to the source of the I/O request via the fabric bus, a result of the access to the storage array.
    Type: Application
    Filed: December 13, 2012
    Publication date: June 19, 2014
    Applicant: APPLE INC.
    Inventors: Harshavardhan Kaushikkar, Muditha Kanchana, Gurjeet S Saund, Odutola O Ewedemi
  • Publication number: 20140173343
    Abstract: A field programmable gate array (FPGA) includes a soft processor and a soft processor debug unit implemented by programmable logic on the FPGA. The FPGA includes a system on a chip (SOC) that includes a hard processor and a hard processor debug unit. The FPGA includes a bus bridge, coupled to an input output (IO) of the FPGA, operable to transmit data between the IO and the soft processor debug unit and the hard processor debug unit.
    Type: Application
    Filed: December 14, 2012
    Publication date: June 19, 2014
    Inventors: Muhammad Ahmed, Manoj Reghunath
  • Publication number: 20140173345
    Abstract: A scalable, reconfigurable Memory Built-In Self-Test (MBIST) architecture for a semiconductor device, such as a multiprocessor, having a Master and one or more Slave MBIST controllers is described. The MBIST architecture includes a plurality of MBISTDP interfaces connected in a ring with the Master MBIST controller. Each MBISTDP interface connects to at least one Slave controller for forwarding test information streamed to it from the Master MBIST controller over the ring. Test information includes test data, address, and MBIST test commands. Each MBISTDP interface forwards the information to the Slave controller attached thereto and to the next MBISTDP interface on the ring. Test result data is sent back to the Master MBIST controller from the MBISTDP interfaces over the ring.
    Type: Application
    Filed: December 18, 2012
    Publication date: June 19, 2014
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Atchyuth K. Gorti, Archana Somachudan
  • Publication number: 20140173346
    Abstract: A system-on-chip includes a storage controller, a read channel integrated circuit, a programmable state machine controller, a switching circuit, a buffer memory, and an interface to access the buffer memory. The switching circuit connects the storage controller or the programmable state machine controller to the read channel integrated circuit. The interface is used to store test control data in the buffer memory. In a given test mode, the switching circuit switchably connects the programmable state machine controller to the read channel integrated circuit. The programmable state machine controller is enabled to access the test control data from the buffer memory, and to process the test control data to generate test signals that are applied to operate the read channel integrated circuit and validate operation of the system-on-chip based on the operation of the read channel integrated circuit.
    Type: Application
    Filed: December 19, 2012
    Publication date: June 19, 2014
    Applicant: LSI Corporation
    Inventor: Sachin Shivanand Bastimane
  • Publication number: 20140173344
    Abstract: Some novel features pertain to a memory controller that includes a memory controller logic, a built-in-self-tester (BIST) logic, and a switch. The memory controller logic is for controlling memory on a memory die. The built-in-self tester (BIST) logic is for testing the memory. The switch is coupled to the BIST logic and the memory. In some implementations, the BIST logic bypasses the memory controller logic when testing the memory by accessing the memory through the switch. The switch may be controlled by the BIST logic. In some implementations, the switch is coupled to the memory controller logic. The switch may control data to the memory that is transmitted from the memory controller logic and the BIST logic based on priority of the data.
    Type: Application
    Filed: December 18, 2012
    Publication date: June 19, 2014
    Applicant: QUALCOMM INCORPORATED
    Inventors: Wootag Kang, Roberto F. Averbuj, Manish Shah
  • Publication number: 20140164834
    Abstract: The invention relates to a method and apparatus. In the method, a programmable random access memory testing circuit detects a signal to initiate testing of at least one random access memory circuit, the testing circuit being connected to a bus to which a processor and the at least one memory circuit is connected, the at least one memory circuit comprising at least a first memory block. The testing circuit determines that the bus is not reserved and reserves the bus. The testing circuit reads application data in a first memory block to a temporary memory of the testing circuit. The testing circuit executes marching test for the first memory block in a memory circuit. The testing circuit returns the application data back to the first memory block in the memory circuit. The testing circuit releases the bus.
    Type: Application
    Filed: November 18, 2013
    Publication date: June 12, 2014
    Applicant: KONE CORPORATION
    Inventor: Ferenc STAENGLER
  • Publication number: 20140164833
    Abstract: A built-in self-test for stacked memory architecture. An embodiment of a memory device includes a memory stack including one or more DRAM (dynamic random access memory) elements; and a system element for control of the memory stack. The system element includes a built-in self-test (BIST) engine to generate a write test event or a read test event for the memory stack, a test interface to receive test data for write test event or the read test events from the BIST engine, and a memory controller, the memory control to receive at least a portion of the test data from the test interface and to implement the write test event or read test event at the DRAM elements of the memory stack.
    Type: Application
    Filed: March 30, 2012
    Publication date: June 12, 2014
    Inventors: Darshan Kobla, David Zimmerman, Vimal K. Natarajan
  • Publication number: 20140164832
    Abstract: According to one embodiment, a test circuit is provided comprising a tester configured to perform a test routine comprising a plurality of test commands for testing an electronic circuit, wherein the tester comprises a checker configured to, if a test command of the plurality of test commands is to be performed, check, whether there is currently a state in which performing the test command could lead to a damage of the electronic circuit and configured to, in case it determines that there is currently a state in which performing the test routine could lead to a damage of the electronic circuit, output a signal indicating that performing the test routine could lead to a damage of the electronic circuit.
    Type: Application
    Filed: December 10, 2012
    Publication date: June 12, 2014
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Bernhard Moessler, Achim Osterloh
  • Patent number: 8751869
    Abstract: A microprogrammable electronic device has a code memory storing a software and/or firmware code having instructions. The microprogrammable electronic device is configured to compute a signature of the code stored in the code memory, and to detect any corruption of the code stored in the code memory on the basis of the computed signature. The microprogrammable electronic device is characterized by being further configured to operate according to instruction cycles, each divided into a respective first and a respective second operating phase; to read a first instruction from the code memory at the first operating phase of an instruction cycle; to decode and execute the read first instruction at the second operating phase of the instruction cycle; to read a second instruction from the code memory at the second operating phase of the instruction cycle; and to compute the signature on the basis of the read second instruction.
    Type: Grant
    Filed: August 2, 2010
    Date of Patent: June 10, 2014
    Assignee: C.R.F. Societa Consortile Per Azioni
    Inventors: Claudio Genta, Alberto Manzone
  • Publication number: 20140157051
    Abstract: The present invention discloses a method and a device to debug the Loongson CPU (a MIPS-structure CPU) and bridge chips. The device, including HT bus interfaces and the corresponding switches, connects the Loongson CPU and bridge chips through HT bus interfaces. Southbridge chips and northbridge chips with HT buses are selected in the following order: introducing the pins on the Loongson CPU and bridge chips into the debug device; debugging the pins on the Loongson CPU to identify whether there are any bugs with the pins; connecting the pins from the CPU and bridge chips to debug them. If the HT bus of the Loongson CPU fails to accord with the standard protocol, the problematic signal can be identified and further adjusted to improve the CPU. With the help of FPGA, multiple HT bus interfaces can be simulated. As a result, multiple chipsets can be linked to the Loongson CPU, which may be debugged simultaneously.
    Type: Application
    Filed: May 20, 2011
    Publication date: June 5, 2014
    Inventors: Zongyou Shao, Xinchun Liu, Xiaojun Yang, Chenming Zheng, Ying Wang, Hui Wang, Zhibin Hao, Faqing Liang, Wenhao Yao
  • Patent number: 8745456
    Abstract: An integrated circuit carries an intellectual property core. The intellectual property core includes a test access port 39 with test data input leads 15, test data output leads 13, control leads 17 and an external register present, ERP lead 37. A scan register 25 encompasses the intellectual property core and ERP lead 37 carries a signal indicating the presence of the scan register.
    Type: Grant
    Filed: August 16, 2013
    Date of Patent: June 3, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Lee D. Whetsel
  • Patent number: 8745455
    Abstract: In one embodiment, the present invention is directed to a logic analyzer such as may be implemented on a system-on-chip or another semiconductor device. The analyzer can include multiple lanes each having a filter to receive and filter debug data, a compressor to compress the debug data passed by the filter, a buffer, and a controller to store the compressed debug data into the buffer, where the compressed debug data can be stored without timing information. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 23, 2010
    Date of Patent: June 3, 2014
    Assignee: Intel Corporation
    Inventors: Ruben Ramirez, Michael J. Wiznerowicz, Sean T. Baartmans, Jason G. Sandri
  • Patent number: 8742786
    Abstract: A semiconductor device includes a monitor including a first element coupled between a first power supply line and a second power supply line, and a load for increasing a load value between the first element and the first power supply line or the second power supply line, and a determination unit which determines an operating state of the first element based on an output of the monitor.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: June 3, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Kazufumi Komura, Katsumi Furukawa, Keiichi Fujimura, Takayoshi Nakamura, Tohru Yasuda, Hirohisa Nishiyama, Nobuyoshi Nakaya, Kanta Yamamoto, Shigetaka Asano
  • Publication number: 20140149795
    Abstract: A disclosed apparatus includes a memory and circuitry that is configured to execute an operating system, and realize one or plural logical domains that provide a predetermined function as a computer and a hypervisor that manages the logical domain. The operating system is configured to: detect hardware to be diagnosed; upon detecting the hardware to be diagnosed, secure a memory area in the memory, which is used for diagnosis by the operating system; instruct a kernel of the operating system to ignore an error that will occur in the secured memory area; and output a diagnosis request that instructs to ignore the error and includes designation of the hardware to be diagnosed to the hypervisor. The hypervisor is configured to execute: upon receipt of the diagnosis request, perform a setting to ignore the error that will occur; and perform the diagnosis for the hardware.
    Type: Application
    Filed: February 4, 2014
    Publication date: May 29, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Yuichi MUSHA, Akihiro YAMAZAKI
  • Patent number: 8738971
    Abstract: A data processing apparatus configured to operate in a voltage and frequency operating region that is located beyond a safe region where errors do not arise, but within operating region limits such that the errors are rare. The data processing apparatus comprises: error detection circuitry and error recovery circuitry; the error detection circuitry being configured to determine if a signal sampled in the processing apparatus changes within a time window occurring after the signal has been sampled and during a same clock cycle as the sampling and to signal an error if the signal does change.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: May 27, 2014
    Assignee: ARM Limited
    Inventors: Frederic Claude Marie Piry, Luca Scalabrino, David Michael Bull
  • Patent number: 8732499
    Abstract: A state retention component is provided which is configured to form part of data processing circuitry. The state retention component is configured to hold a state value at a node of the data processing circuitry when the data processing circuitry enters a low power mode. The state retention component comprises a scan input, wherein the state retention component configured, when a scan enable signal is asserted, to read in the state value from a scan input value applied at the scan input, and a scan output, wherein the state retention component is configured, when the scan enable signal is asserted, to read out the state value to the scan output.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: May 20, 2014
    Assignee: ARM Limited
    Inventor: David Walter Flynn
  • Patent number: 8732523
    Abstract: A data processing apparatus has a plurality of storage elements residing at different physical locations within the apparatus, and fault history circuitry for detecting local transient faults occurring in each storage element, and for maintaining global transient fault history data based on the detected local transient faults. Analysis circuitry monitors the global transient fault history data to determine, based on predetermined criteria, whether the global transient fault history data is indicative of random transient faults occurring within the data processing apparatus, or is indicative of a coordinated transient fault attack. The analysis circuitry is then configured to initiate a countermeasure action on determination of a coordinated transient fault attack.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: May 20, 2014
    Assignee: ARM Limited
    Inventors: Emre Özer, Yiannakis Sazeides, Daniel Kershaw, Stuart David Biles
  • Patent number: 8730747
    Abstract: The semiconductor device including a memory circuit is configured to include a mode switching circuit additionally provided with a data comparison circuit which detects that a serial signal supplied to an input terminal for communication and a serial signal supplied to an input terminal used for a purpose other than communication are reversed from each other, a decoder circuit which detects that a serial signal carries predetermined data and which outputs a detection signal, a control signal generating circuit which generates a control signal, and a circuit which outputs a signal for switching to a test mode on the basis of the signals.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: May 20, 2014
    Assignee: Seiko Instruments Inc.
    Inventor: Takashi Nakamura
  • Publication number: 20140122929
    Abstract: A method and apparatus for distributed on-chip debug triggering is presented. A first bus includes a plurality of lines and a debugging state machine configurable to monitor the plurality of lines of the first bus. One or more nodes are configurable to detect triggering events and provide, in response to detecting one or more triggering events, signals to the debugging state machine using a first subset of the plurality of lines that is allocated to the node(s).
    Type: Application
    Filed: October 31, 2012
    Publication date: May 1, 2014
    Inventors: Scott P. Nixon, Eric M. Rentschler
  • Patent number: 8713370
    Abstract: A system, apparatus, and method for writing trace data to storage. Trace data is captured from one or more processors, and then the trace data is written to a trace buffer. The trace data includes program counters of instructions executed by the processors and other debug data. A direct memory access (DMA) controller in a non-real-time block of the system reads trace data from the trace buffer and then writes the trace data to memory via a non-real-time port of a memory controller.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: April 29, 2014
    Assignee: Apple Inc.
    Inventors: Timothy J. Millet, Shun Wai (“Dominic”) Go, Conrad H. Ziesler
  • Patent number: 8713391
    Abstract: A system for testing an integrated circuit, in which the system includes a deserializer, a frame sync module, and a diagnostic module. The deserializer is external to the integrated circuit and is configured to receive messages in a serial data format, wherein the messages include test results associated with the integrated circuit, and deserialize the messages into data frames. The frame sync module is configured to provide control code based on the data frames, wherein the control code includes, in a digital format, status information associated with the messages deserialized into the data frames. The diagnostic module is configured to generate, based on the control code, diagnostic data associated with states of the integrated circuit.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: April 29, 2014
    Assignee: Marvell International Ltd.
    Inventors: Saeed Azimi, Son Ho, Daniel Smathers
  • Patent number: 8713240
    Abstract: In one embodiment, a system-on-chip (SoC) can be configured to receive a request from a master agent in a fabric coupled to the master agent, send a show command grant to the master agent responsive to selection of the request by the fabric, receive a command portion of a transaction corresponding to the request in the fabric and determine a target agent to receive the transaction based on the command portion, and thereafter send a transaction grant to the master agent for the transaction. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: April 29, 2014
    Assignee: Intel Corporation
    Inventors: Sridhar Lakshmanamurthy, Mikal C. Hunsaker, Michael T. Klinglesmith, Blaise Fanning, Eran Tamari, Joseph Murray, Robert P. Adler
  • Patent number: 8713369
    Abstract: Debug circuitry is operated in a manner that facilitates debugging one or more hardware and/or software components that are included in a system that includes a system memory. The debug circuitry receives information from one of the hardware and/or software components and/or from the system memory, and ascertains whether the received information includes memory address parameters. If the received information includes memory address parameters, then the memory address parameters are used to retrieve data from the system memory. The retrieved data is supplied at an output port of the debug circuitry.
    Type: Grant
    Filed: May 8, 2011
    Date of Patent: April 29, 2014
    Assignee: Telefonaktiebolaget L M Ericsson (publ)
    Inventors: Philip Mansson, Magnus Malmberg
  • Patent number: 8713392
    Abstract: A circuitry testing module for testing an external circuit of a Light-Emitting Diode (LED) includes at least one logic unit and a latch circuit. Two input terminals of the at least one logic unit are connected to a first end and a second of the LED correspondingly. The output terminal of the at least one logic unit is connected to the latch circuit. If the external circuit works normally, the logic unit outputs a first logic operating signal to the latch unit, and the latch circuit outputs a first latch signal. If the external circuit does not work normally, the logic unit outputs a second logic operating signal to the latch unit, and the latch circuit outputs a second latch signal.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: April 29, 2014
    Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.
    Inventors: Xiong-Zhi Chen, Sung-Kuo Ku
  • Patent number: 8713371
    Abstract: A data processing apparatus for performing data processing operations in response to execution of program instructions and debug circuitry for performing operations. The data processing apparatus includes a data store for storing a current debug exception mask value. The data processing circuitry is configured to set the mask value to a first value in the data store in response to executing critical code and on termination of execution of the critical code to reset the mask value to not store the first value. The data processing circuitry is configured, in response to receipt of a control signal indicating a debug exception is to be taken, to allow the exception to be taken if the mask value is not set to the first value and not to allow said exception to be taken if the mask value is set to the first value.
    Type: Grant
    Filed: November 15, 2011
    Date of Patent: April 29, 2014
    Assignee: ARM Limited
    Inventors: Michael John Williams, Richard Roy Grisenthwaite
  • Patent number: 8707107
    Abstract: A computer-implemented method may include monitoring a computing system for evidence of potential data failures within the computing system. The computer-implemented method may also include detecting evidence that indicates a potential data failure while monitoring the computing system and identifying data implicated in the potential data failure based on the detected evidence. The computer-implemented method may further include initiating an action configured to proactively facilitate restoration of at least a portion of the data implicated in the potential data failure prior to determining whether the data implicated in the potential data failure needs to be restored. Various other methods, systems, and computer-readable media are also disclosed.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: April 22, 2014
    Assignee: Symantec Corporation
    Inventors: Arindam Panna, Nilesh Dhakras
  • Patent number: 8700955
    Abstract: A data processing system includes a plurality of data processors, debug logic, and linking logic. The debug logic is coupled to each data processor of the plurality of data processors, and is for providing an instruction for exiting debug mode to the plurality of data processors. The linking logic is coupled to the debug logic and to each of the plurality of data processors. The linking logic is for linking selected ones of the plurality of data processors with each other and to the debug logic. The debug logic provides the instruction for exiting the debug mode when the selected ones of the plurality of data processors are linked in parallel by the linking logic.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: April 15, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: William C. Moyer, Jimmy Gumulja, Gary L. Miller
  • Patent number: 8700957
    Abstract: Systems and methods for remotely performing testing or scanning of boards, devices and/or systems across a network to validate code stored in the subject circuits, including validation of non-volatile storage such as Flash memory and volatile storage such as RAM, containing stable content of known patterns.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: April 15, 2014
    Assignee: Electronic Warfare Associates, Inc.
    Inventors: George Bernard La Fever, Iser B. Flaum
  • Patent number: 8700956
    Abstract: A debug circuit of a microcomputer, providing an on-chip debug function, is provided as a measurement permission circuit for outputting a measurement permission signal to a timer that measures, as a measurement object, a time period between two events in a program execution period of the CPU, according to a user-specified condition. The measurement permission circuit includes an interrupt level register for setting an interrupt level that either permits or prohibits a time measurement operation of the timer, and a comparator for determining by comparison a high-low relationship between an interrupt level of an interrupt process executed by the CPU and an interrupt level set in the interrupt level register, and a determination result of the comparator is specified as the measurement permission signal.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: April 15, 2014
    Assignee: DENSO CORPORATION
    Inventors: Yuuki Asada, Naoki Ito, Kyouichi Suzuki, Norio Fujimori
  • Publication number: 20140095932
    Abstract: A system includes a processor and a plurality of circuits connected through an interconnection network, wherein associated to each circuit is a respective communication interface configured for exchanging data between the respective circuit and the interconnection network. In particular, a debug unit is associated with each communication interface. Each debug unit is configurable as a data-insertion point, wherein the debug unit transmits data by means of the respective communication interface to the interconnection network, or each debug unit is configurable as a data-reception point, wherein the debug unit receives data by means of the respective communication interface from the interconnection network.
    Type: Application
    Filed: September 26, 2013
    Publication date: April 3, 2014
    Applicants: STMicroelectronics S. r. I., STMicroelectronics (Grenoble 2) SAS
    Inventors: Daniele Mangano, Ignazio Antonino Urzi
  • Patent number: 8689067
    Abstract: A system and method for detecting transition delay faults decouples the test enable pins of the clock gating cells from other elements in the circuitry. The test enable pins are controlled during test mode by a unique signal, allowing the tester to independently control the clock gating logic of the circuitry. By being able to ungate the clock, the tester can ensure that the two clock pulses needed to check for transition delay faults will always be present.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: April 1, 2014
    Assignee: Marvell International Ltd.
    Inventor: Darren Bertanzetti
  • Patent number: 8683265
    Abstract: An embodiment of an electronic system includes a first electronic module, a second electronic module, a first debug circuit integrated with the first electronic module, a second debug circuit integrated with the second electronic module, and a communications interface between the first debug circuit and the second debug circuit. The first debug circuit is configured to determine that a triggering event has occurred, and to produce a first cross trigger signal on the communications interface in response to determining that the triggering event has occurred. The second debug circuit is configured to detect the first cross trigger signal on the communications interface, and to perform an action in response to detecting the first cross trigger signal.
    Type: Grant
    Filed: December 29, 2010
    Date of Patent: March 25, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Eric M. Rentschler, Steven J. Kommrusch, Elizabeth M. Cooper, Stephen Ennis
  • Patent number: 8683266
    Abstract: The object of the invention is in particular the validation of configuration of a system comprising a plurality of elements, at least one reference being associated with each element of the said plurality of elements. After at least one reference key has been calculated (410) according to at least one expected reference of each element of the said plurality of elements, a theoretical configuration report of the said system, comprising the said at least one reference key, is generated (420). Similarly, at least one verification key is calculated (455) according to at least one reference of each element of the said plurality of elements, and a real configuration report of the said system, comprising the said at least one verification key, is generated (460). A configuration error is detected if the values of the said verification key and reference key of the said real and theoretical configuration reports are different.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: March 25, 2014
    Assignee: AIRBUS Operations S.A.S.
    Inventors: Raphael Migliasso, Olivier Bastien, Miguel Estrada-Fernandez