Abstract: A technique tests whether an integrated computing system having server, network and storage components complies with a configuration benchmark expressed as rules in first markup-language statements such as XML. The rules are parsed to obtain test definition identifiers identifying test definitions in a second set of markup-language statements, each test definition including a test value and an attribute identifier of system component attribute. A management database is organized as an integrated object model of all system components. An interpreter invoked with the test definition identifier from each rule process each test definition to (a) access the management database using the attribute identifier obtain the actual value for the corresponding attribute, and (b) compare the actual value to the test value of the test definition to generate a comparison result value that can be stored or communicated as a compliance indicator to a human or machine user.

Abstract: A method, data processing system, and computer program product for testing a computer system. A sequencer tests the computer system using test modules arranged in a first sequence, wherein each of the test modules is for testing at least a portion of the computer system. The sequencer determines if an operator is available, in response to an interrupt generated by a test module. If an operator is available, the sequencer arranges the test modules into a second sequence based on a first policy. If an operator is unavailable, the sequencer arranges the test modules into a third sequence based on a second policy.

Abstract: Method, system and product for post silicon validation using a partial reference model. The method performed by a device having registers, the method comprising: first executing, by the device when operating in trace mode, a test-case, wherein during the execution utilizing a partial reference model to determine an expected value of at least one register; second executing, by the device when operating in non-trace mode, the test-case; and in response to said second executing, checking values of registers based on, at least in part, values determined during said first execution.

Abstract: An automation process verifies that a test bed includes a set of devices specified by at least one script which are to be executed by the automation process on the test bed. The test bed is locked and the set of devices is allocated to the automation process. Performance data collection and logging for the set of devices is started and the at least one script is executed on the set of devices. After executing the at least one script, the set of devices is de-allocated and the test bed is unlocked. A notification is generated indicating that the at least one script has been executed.

Abstract: An apparatus, system, and method are disclosed for probing a computer process. A probe parameter module determines a process identifier, a probe interval, and a probe action. The process identifier uniquely identifies a computer process. A start timer module starts a timer with a timer interval in response to the computer process entering an executing state on a processor core. The timer interval is based on the probe interval and on an amount of time elapsed between a probe start time and the computer process entering the executing state on the processor core. An action module executes the probe action in response to the timer satisfying the timer interval while the computer process is in the executing state on the processor core.

Abstract: The present disclosure generally relates to the testing of a system that includes software or hardware components. In some embodiments, a testing framework generates a set of test cases for a system under test using a grammar. Each test case may perform an action, such as provide an input to the system under test, and result in an output from the system under test. The inputs and outputs are then compared to the expected results to determine whether the system under test is performing correctly. Prior to generating the set of test cases from the grammar, the testing framework processes the grammar to identify attributes of the test cases to be derived from the grammar and facilitates the modification of the grammar.

Abstract: A controller that obtains data from an object device in obedience to an obtaining request from the processor includes an error setter that sets, when a pseudo failure mode that spuriously generates a failure is active, an error associated with a failure type of a pseudo failure to be generated in the data obtained from the object device in obedience to the obtaining request; and an error processor that notifies, when detecting an error in the data under a state where the pseudo failure mode is active, the processor of the failure response corresponding to the failure type associated with the detected error.

Abstract: Embodiments of a testcase checker system are disclosed herein. Embodiments of a testcase checker system may include an instruction set simulator configured to simulate execution of instructions of a testcase on a microprocessor using a reference model associated with an architecture of the microprocessor. The instruction set simulator may generate logging data associated with the each instruction based on the simulated execution of that instruction. The testcase checker system may also include checker module comprising a set of rules. Each of these rules may be associated with a boundedly undefined condition. The checker module is configured to receive the logging data associated with an instruction from the instruction set simulator and process the logging data based on the rules to determine if any of the rules are violated.

Abstract: A transmission device has a first input unit that inputs data, a second input unit that inputs data, a first information processing unit that outputs data resulting from information processing of data input by the first input unit or data input by the second input unit, a first holding unit that holds data output by the first information processing unit, a second holding unit that holds data output by the first information processing unit, a control information holding unit that holds control information, a first selection unit that selects, on the basis of the control information, either the data held by the first holding unit or the data held by the second holding unit, and a first output unit that returns data selected by the first selection unit to the first input unit, on the basis of the control information.

Abstract: A method includes receiving a first processing request for an application program under test. The method includes generating a second processing request for a model of the application program, wherein the second processing request is equivalent to said first processing request. The method includes communicating said first and second requests to said application program under test and said model of the application program respectively. The method includes receiving a first response data set from the application program under test and a second response data set from the model of the application program. The method includes comparing said first and second response data sets and generating a success indication if said comparing said first and second response data sets does not identify a difference. The method includes generating an error indication if said comparing said first and second response data sets identifies a difference between the first and second data sets.

Abstract: Test executive system and method of use. The system includes a test executive engine, configured to execute at least one test executive sequence to test at least one unit under test (UUT), a process model that specifies one or more function sequences for pre-test or post-test functionality for the test executive sequences, and a plug-in framework, configured to selectively incorporate one or more process model plug-in instances in the process model. Each process model plug-in instance specifies at least one respective function sequence for pre-test or post-test functionality for the test executive sequences.

Abstract: Test executive system and method of use. The system includes a test executive engine, configured to execute at least one test executive sequence to test at least one unit under test (UUT), a process model that specifies one or more function sequences for pre-test or post-test functionality for the test executive sequences, and a plug-in framework, configured to selectively incorporate one or more process model plug-in instances in the process model. Each process model plug-in instance specifies at least one respective function sequence for pre-test or post-test functionality for the test executive sequences.

Abstract: A failure reproducing apparatus according to the present invention includes a log analyzing unit that determines processes that have caused a failure when the failure has occurred in a server system, a target-value calculating unit that calculates a target value on the basis of execution time of each process, and a time-lag calculating unit that calculates a time lag. An execution control unit adjusts timing of outputting an execution command of each process to the server system on the basis of the target value and the time lag and executes a reproduction test.

Abstract: Measurement agents in a network failure detecting system each configure a group together with other measurement agents that receive a service from the same provision server, and form a link to create a tree structure with a predetermined measurement agent in the group at its top. The measurement agent then receives measurement results from the other measurement agents in the group, and narrows down candidates of a failure location based on the received measurement results. The measurement agent transmits the narrowed candidates of the failure location to a surveillance server or one of the other measurement agents. The surveillance server then receives the transmitted candidates of the failure location, and specifies the failure location based on the received candidates of the failure location.

Abstract: Embodiments of the invention include systems and methods for automatically predicting production yield for a circuit assembly according to attributes of its components and defect data mapped thereto. Embodiments receive a proposed design specification for a circuit assembly, including bill of materials (BOM) and schematic data, at a yield prediction environment. The yield prediction environment maps a set of attributes to each component in the BOM and maps a set of possible defects to each component according to its attributes. Defects may be further mapped to a manufacturing process assigned to populate each component in the circuit assembly. The defects are associated with predicted frequencies of occurrence, which can be used to roll up a yield prediction for the circuit assembly. Embodiments further allow “what-if” analysis to be performed so that different yield prediction results can be compared according to different form factor options and/or different manufacturing process options.

Abstract: A method and a device for planning an industrial automation arrangement, where an object model is generated from data objects, which represent automation components, and from relationships between these objects, a sequence of control actions by a user is used to select the objects from an object library and to relate them to one another. A plurality of sequences of control actions and their respective effects on the object model are stored as respective entity control trees with control steps, where at least two of the entity control trees are selected and used to generate a generalized type control tree using a first comparison, and the type of control tree is used to automatically plan the industrial automation arrangement.

Abstract: A method of preparing a test for an electronic system including a plurality of pieces of equipment interconnected by at least one communications link, in which method, in order to perform the test, use is made of a test bench appropriate for the electronic system under test, which test bench is connected to the system and controlled in application of a command sequence established from at least one informal functional specification; while preparing the test, the informal functional specification, the command sequence, and a link identifying the informal functional specification from which the command sequence was established are all recorded so that after execution of the command sequence and after the test results have been recorded, it is possible to read the link and identify unambiguously the informal functional specification that corresponds to the test results obtained.

Abstract: A system for validating a hardware platform is provided. The system includes a database that stores one or more test specifications, a compiler that generates a target image based on (i) a device driver obtained from a device driver generator, (ii) a platform independent target application code, (iii) a kernel source, and (iv) a run time environment, and a software driven validation generator that analyses the run time specification and the device programming specification and generates (i) one or more test cases based on (a) the one or more test specifications, and (b) the device programming specification, and (ii) a control software based on the test cases. The test cases include configurations that are specific to the hardware platform. The hardware platform is validated based on (i) an execution of the target image and the control software on the hardware platform, and (ii) the one or more test cases.

Abstract: A method, system, and computer program product detect soft failures as follows. A set of artifacts being generated by at least one process in a system is monitored. A number of artifacts being generated by the process is determined to be below a given threshold in response to the monitoring. The process is monitored in response to the determination. A current state of the process is determined in response to the analyzing. A notification is generated in response to the current state of the process including a set of abnormal behaviors.

Abstract: A method detects soft failures as follows. A set of artifacts being generated by at least one process in a system is monitored. A number of artifacts being generated by the process is determined to be below a given threshold in response to the monitoring. The process is monitored in response to the determination. A current state of the process is determined in response to the analyzing. A notification is generated in response to the current state of the process including a set of abnormal behaviors.

Abstract: An operation of a processor in respect to transactions is checked by simulating an execution of a test program, and updating a transaction order graph to identify a cycle. The graph is updated based on a value read during an execution of a first transaction and a second transaction that is the configured to set the memory with the read value. The test program comprises information useful for identifying the second transaction.

Abstract: A system and method for managing a test of a motherboard can create a first test data consisting of test items. In the first test data, one or more selected test items to perform can be identified. A second test data is obtained by performing a logical NOR operation on the test bits corresponding to the selected test items. After performing the test items, a third test data is created by setting the test bits corresponding to the selected test items that pass the test to the test bits of the selected test items in the first test data, and by setting the test bits corresponding to the selected test items that fail the test to the test bits of the test items that have not been selected in the first test data. By comparing the third with the test data, a test result of the motherboard is obtained.

Abstract: A method, system and computer-usable medium are disclosed for suppressing managed endpoint (MEP) child events in a network. A MEP multicast message is broadcast by an originating MEP. Responses received from peer MEPs within a selected time interval are processed to determine their respective IP address, MAC address, and VLAN. If this information is not currently stored in a table of peer MEP device information associated with the originating MEP, then it is added. The responding MEP is then marked in the peer MEP device table as having responded. Peer MEP devices that have responded to previous multicast messages, but have now failed to respond within the selected time interval, are determined. A MEP network event is generated, comprising the IP address of the device containing the MEP, the MAC address for inward-facing MEPs, the MAC address of the associated bridge, the port addresses for outward-facing MEPs, and associated VLAN information.

Abstract: Embodiments provide systems, devices, methods, and machine-readable medium for automated debugging of a design under test in a verification environment as part of electronic design automation. Embodiments may automatically identify inputs that are relevant to a bug for a device under test. A failing test run may be taken and rerun several times with small changes in the inputs. If the test is passing, the mutated inputs may be important to reproduce the bug and may be marked as “suspicious”. The result of this process may be a list of suspicious inputs and a shorter and simpler test that still fails. The shorter test may be rerun and fields of the inputs recorded. New tests may be created with mutated fields. Mutated fields that result in passing tests may be considered suspicious fields. Suspicious inputs and fields may be presented to a user as part of an electronic design process.

Abstract: A test method which tests a processing device includes: obtaining a maximum number of processing units with which the processing device as a test target can simultaneously parallel process a plurality of threads; specifying a number of threads, causing the processing device as the test target to parallel process the threads, and obtaining a processing time corresponding to the number of threads; and outputting information indicating that the processing device as the test target is normal when the number of threads for which the processing time is more than or equal to a threshold matches the maximum number of processing units which can simultaneously parallel process, or outputting information indicating that the processing device as the test target is abnormal when the number of threads does not match.

Abstract: Some embodiments of the invention relate to an embedded processing system. The system includes a memory unit to store a plurality of operating instructions and a processing unit coupled to the memory unit. The processing unit can execute logical operations corresponding to respective operating instructions. An input/output (I/O) interface receives a first time-varying waveform and provides an I/O signal that is based on the first time-varying waveform. A comparison unit coupled to the processing unit and adapted to selectively assert an error signal based on whether the I/O signal has a predetermined relationship with a reference signal, wherein the predetermined relationship holds true during normal operation but fails to hold true when an unexpected event occurs and causes an unexpected change at least one of the I/O signal and reference signal.

Abstract: Instruction fetch unit (IFU) verification is improved by dynamically monitoring the current state of the IFU model and detecting any predetermined states of interest. The instruction address sequence is automatically modified to force a selected address to be fetched next by the IFU model. The instruction address sequence may be modified by inserting one or more new instruction addresses, or by jumping to a non-sequential address in the instruction address sequence. In exemplary implementations, the selected address is a corresponding address for an existing instruction already loaded in the IFU cache, or differs only in a specific field from such an address. The instruction address control is preferably accomplished without violating any rules of the processor architecture by sending a flush signal to the IFU model and overwriting an address register corresponding to a next address to be fetched.

Abstract: A test system uses an instrumented browser to identify events that were not successfully captured during a client web session. The identified events can be used to modify a capture system that captures the client web session. Alternatively, the test system may generate replay rules that are used by a replay system to infer the missed events while replaying of the previously captured client web session. The events can include changes to Document Object Models (DOMs) for web pages used during the web sessions. The DOMs can be used to identify significant web session events and force replay sessions into the correct states.

Abstract: A method for problem determination and resolution in an information technology (IT) system includes receiving a problem ticket, searching a database for a plurality of problem features based on data included in the problem ticket, extracting the plurality of problem features from the database, and generating a problem signature corresponding to the problem ticket, wherein the problem signature comprises at least one non-textual feature extracted from the plurality of problem features.

Abstract: A method for detecting a failure in a serial topology. The method may comprise sending a predetermined pattern to a plurality of devices communicatively connected to an initiator in a serial topology; receiving a return result from each of the plurality of devices in response to the predetermined pattern; recognizing a problem associated with a particular device among the plurality of devices, the problem being recognized based on the return result from the particular device; sending a plurality of test patterns to the particular device; receiving a plurality of test results from the particular device in response to the plurality of test patterns; and determining a cause of the problem based on the plurality of test results, the cause of the problem being at least one of: a cable failure and a device failure.

Abstract: Systems and methods are described that dynamically reprioritize test cases for Model-Based Testing (MBT) during test execution. Test case execution is prioritized according to their potential to detect uncovered failures within a design model.

Abstract: In one embodiment, a protocol aware circuit for automatic test equipment, which includes a protocol generation circuit constructed to retrieve protocol unique data and format the protocol unique data with a selected protocol definition corresponding to a device under test for testing the device under test. The protocol generation circuit may be constructed to retrieve the selected protocol definition from a protocol definition table.

Abstract: A control apparatus includes a lower layer control unit configured to perform control of a load, an upper layer control unit configured to control the lower layer control unit, a communication unit configured to perform communication between the upper layer control unit and the lower layer control unit via a communication line, a detection unit configured to detect power supply voltage of the lower layer control unit, wherein the upper layer control unit detects communication abnormality of the communication unit and notifies the communication abnormality, the upper layer control unit notifying abnormality of power supply voltage of the lower layer control unit, in such a manner as to be identified from the communication abnormality of the communication unit.

Abstract: A communication system includes a switch that switches output ports according to an address of transmission data; a storing unit that stores a first set of addresses associated with the switch; a determining unit that determines, when a second set of addresses including in the transmission data a response to which is not received matches the first set of addresses in the storing unit, that there is a failure in the switch associated with the first set of addresses.

Abstract: A first test script that includes at least one first step for executing a test of a test portal is provided in a computing device. An indication that an event has occurred in response to the test is received in the computing device. A second test script that includes at least one second step for executing the test is generated in the computing device, the at least one second step being at least in part a response to the event.

Abstract: A simulator is partitioned into a functional component and a behavior prediction component and the components are executed in parallel. The execution path of the functional component is used to drive the behavior prediction component and the behavior prediction component changes the execution path of the functional component.

Abstract: A failure management device includes a stored position obtainer that obtains stored position data that represents a position at which failure data is generated by an information processing apparatus when a failure is occurring; a failure data obtainer that obtains the failure data generated by the information processing apparatus from a memory device, communicably connected to the information processing apparatus and the failure management device, on the basis of the stored position data; and a configuration controller that changes, on the basis of the failure data obtained by the failure data obtainer, a configuration of the failure management device so as to conform to that of the information processing apparatus. This configuration makes it possible to easily reproduce the failure occurred in the information processing apparatus and consequently, a reproducing test can be accomplished efficiently.

Abstract: Service providers strive to maintain networks with high levels of availability and performance. To maintain the networks, the service providers measure performance and perform network diagnostics. Measuring performance and performing network diagnostics typically involves manual verification of functionality or performing individual tests between user agents. Service providers who maintain networks and service providers who use networks can dynamically run tests with operations of a signaling protocol (e.g., session initiation protocol) to diagnose network problems and determine appropriate responses. An agent manager can coordinate the dynamic tests across multiple user agents to gather more information to increase problem diagnosis accuracy.

Abstract: Instruction fetch unit (IFU) verification is improved by dynamically monitoring the current state of the IFU model and detecting any predetermined states of interest. The instruction address sequence is automatically modified to force a selected address to be fetched next by the IFU model. The instruction address sequence may be modified by inserting one or more new instruction addresses, or by jumping to a non-sequential address in the instruction address sequence. In exemplary implementations, the selected address is a corresponding address for an existing instruction already loaded in the IFU cache, or differs only in a specific field from such an address. The instruction address control is preferably accomplished without violating any rules of the processor architecture by sending a flush signal to the IFU model and overwriting an address register corresponding to a next address to be fetched.

Abstract: Systems and methods are described that dynamically reprioritize test cases for Model-Based Testing (MBT) during test execution. Test case execution is prioritized according to their potential to detect uncovered failures within a design model.

Abstract: Mechanisms are provided for controlling a fidelity of a simulation of a computer system. A model of the system is received that has a plurality of components. A representation of the plurality of individual components of the system is generated. A component is assigned to be a fidelity center having a highest possible associated fidelity value. Fidelity values are assigned to each other component in the plurality of individual components based on an affinity of the other component to the fidelity center. The system is simulated based on assigned fidelity values to the components in the plurality of individual components.

Abstract: Aspects of the invention relate to techniques for fault diagnosis based on dynamic circuit design partitioning. According to various implementations of the invention, a sub-circuit is extracted from a circuit design based on failure information of one or more integrated circuit devices. The extraction process may comprise combining fan-in cones of failing observation points included in the failure information. The extraction process may further comprise adding fan-in cones of one or more passing observation points to the combined fan-in cones of the failing observation points. Clock information of test patterns and/or layout information of the circuit design may be extracted and used in the sub-circuit extraction process. The extracted sub-circuit may then be used for diagnosing the one or more integrated circuit devices.

Abstract: Model-based testing is performed by repeatedly constructing a test strategy in which each test stimulus will lead to increased test coverage regardless of the nondeterministic choices made by the system under test, and following said strategy until coverage is increased. As soon as no such strategy exists, testing stops.

Abstract: A meta attribute useful for functional coverage is computed based on values comprised by two or more matching fields in a trace. The two or more matching fields may be comprised by a single entry of the trace or by a plurality of entries of the trace. A definition of the meta attribute may define which fields of the entries comprise values useful for computation of the meta attributes. The matching entries may be identified based on identifying values within the entries.

Abstract: Various embodiments related to identifying regions including physical defects in semiconductor devices are disclosed. For example, one embodiment includes receiving an electrical test mismatch reported for a scan chain; identifying a suspect logical region including a plurality of logic cones electrically connected with the scan chain; adjusting a scope of the suspect logical region by simulating data flow within the logic cones, generating simulated scan chain output based on the simulated data flow within the logic cones, and excluding at least one of the logic cones from the suspect logical region based on a comparison of the electrical test mismatch and the simulated scan chain output; after adjusting the scope of the suspect logical region, generating a candidate defect region, the candidate defect region being defined to include physical instantiations of logical cells and logical interconnections included in the suspect logical region; and displaying the candidate defect region.

Abstract: A diagnostic module delivery server includes a diagnostic selecting unit that reads a failure rate of a component from a component database that stores therein the failure rates of the components obtained based on the maintenance history of the components constituting a maintenance target server. Furthermore, the diagnostic selecting unit determines whether to diagnose the component in accordance with the result of comparing the read failure rate of the component and a failure rate reference value that is stored in a diagnostic reference value database. Furthermore, the diagnostic module delivery server transmits, to the maintenance target server, a diagnostic module that is used to diagnose the component in which it is determined, by the diagnostic selecting unit, that the diagnostics is to be performed.

Abstract: A method for software processing includes obtaining change information, which records changes that have been performed in respective locations in software code. The change information is processed so as to assign to at least some of the locations respective priorities, which are indicative of respective likelihoods that the locations contain program faults. The at least some of the locations are presented to a user in accordance with the assigned priorities.

Abstract: A method, system, and computer usable program product for energy-efficient soft error failure detection and masking are provided in the illustrative embodiments. A soft error is injected to occur during execution of a set of instructions. If an output of the execution of the set of instructions is incorrect, a record is made of the instruction that was affected by the injected soft error and led to the incorrect result. This identified instruction is designated as vulnerable to the soft error. Several soft errors are injected with different input data sets over several executions of the same set of instructions, and a probability of each instruction in the instruction set is computed, the probability of an instruction accounting for the vulnerability of the execution of the instruction sets to errors that affect the instruction. A report including several probabilities of instruction vulnerabilities is produced.

Abstract: A method and device for predicting faults in a distributed heterogeneous IT system (100), the method comprising: creating a local checkpoint (19) in an explorer node (10) of said system (100), said local checkpoint (19) reflecting the state of said explorer node (10); running a path exploration engine (14) on said local checkpoint (19) in order to predict faults, wherein a plurality of possible inputs (71) are used by said exploration engine (14) in order to explore different paths, wherein path exploration comprises sending messages to remote client nodes (20), and receiving messages from said remote clients (20); wherein said received messages do not reveal checkpoints of said other nodes, so as to avoid leakage of any confidential information.

Abstract: A system and method is disclosed that has the ability to automatically derive a test execution plan for parallel execution of test cases, while considering the complex dependencies across the test cases and preserving the semantics of test execution. The execution plan, so generated, provides for balanced workload distribution and scheduling of the test cases for improving the test execution cycles of the test suites in a cost effective manner.