Abstract: A system for validating a hardware platform is provided. The system includes a database that stores one or more test specifications, a compiler that generates a target image based on (i) a device driver obtained from a device driver generator, (ii) a platform independent target application code, (iii) a kernel source, and (iv) a run time environment, and a software driven validation generator that analyses the run time specification and the device programming specification and generates (i) one or more test cases based on (a) the one or more test specifications, and (b) the device programming specification, and (ii) a control software based on the test cases. The test cases include configurations that are specific to the hardware platform. The hardware platform is validated based on (i) an execution of the target image and the control software on the hardware platform, and (ii) the one or more test cases.

Abstract: A method, system, and computer program product detect soft failures as follows. A set of artifacts being generated by at least one process in a system is monitored. A number of artifacts being generated by the process is determined to be below a given threshold in response to the monitoring. The process is monitored in response to the determination. A current state of the process is determined in response to the analyzing. A notification is generated in response to the current state of the process including a set of abnormal behaviors.

Abstract: A method detects soft failures as follows. A set of artifacts being generated by at least one process in a system is monitored. A number of artifacts being generated by the process is determined to be below a given threshold in response to the monitoring. The process is monitored in response to the determination. A current state of the process is determined in response to the analyzing. A notification is generated in response to the current state of the process including a set of abnormal behaviors.

Abstract: An operation of a processor in respect to transactions is checked by simulating an execution of a test program, and updating a transaction order graph to identify a cycle. The graph is updated based on a value read during an execution of a first transaction and a second transaction that is the configured to set the memory with the read value. The test program comprises information useful for identifying the second transaction.

Abstract: A system and method for managing a test of a motherboard can create a first test data consisting of test items. In the first test data, one or more selected test items to perform can be identified. A second test data is obtained by performing a logical NOR operation on the test bits corresponding to the selected test items. After performing the test items, a third test data is created by setting the test bits corresponding to the selected test items that pass the test to the test bits of the selected test items in the first test data, and by setting the test bits corresponding to the selected test items that fail the test to the test bits of the test items that have not been selected in the first test data. By comparing the third with the test data, a test result of the motherboard is obtained.

Abstract: A method, system and computer-usable medium are disclosed for suppressing managed endpoint (MEP) child events in a network. A MEP multicast message is broadcast by an originating MEP. Responses received from peer MEPs within a selected time interval are processed to determine their respective IP address, MAC address, and VLAN. If this information is not currently stored in a table of peer MEP device information associated with the originating MEP, then it is added. The responding MEP is then marked in the peer MEP device table as having responded. Peer MEP devices that have responded to previous multicast messages, but have now failed to respond within the selected time interval, are determined. A MEP network event is generated, comprising the IP address of the device containing the MEP, the MAC address for inward-facing MEPs, the MAC address of the associated bridge, the port addresses for outward-facing MEPs, and associated VLAN information.

Abstract: Embodiments provide systems, devices, methods, and machine-readable medium for automated debugging of a design under test in a verification environment as part of electronic design automation. Embodiments may automatically identify inputs that are relevant to a bug for a device under test. A failing test run may be taken and rerun several times with small changes in the inputs. If the test is passing, the mutated inputs may be important to reproduce the bug and may be marked as “suspicious”. The result of this process may be a list of suspicious inputs and a shorter and simpler test that still fails. The shorter test may be rerun and fields of the inputs recorded. New tests may be created with mutated fields. Mutated fields that result in passing tests may be considered suspicious fields. Suspicious inputs and fields may be presented to a user as part of an electronic design process.

Abstract: A test method which tests a processing device includes: obtaining a maximum number of processing units with which the processing device as a test target can simultaneously parallel process a plurality of threads; specifying a number of threads, causing the processing device as the test target to parallel process the threads, and obtaining a processing time corresponding to the number of threads; and outputting information indicating that the processing device as the test target is normal when the number of threads for which the processing time is more than or equal to a threshold matches the maximum number of processing units which can simultaneously parallel process, or outputting information indicating that the processing device as the test target is abnormal when the number of threads does not match.

Abstract: Some embodiments of the invention relate to an embedded processing system. The system includes a memory unit to store a plurality of operating instructions and a processing unit coupled to the memory unit. The processing unit can execute logical operations corresponding to respective operating instructions. An input/output (I/O) interface receives a first time-varying waveform and provides an I/O signal that is based on the first time-varying waveform. A comparison unit coupled to the processing unit and adapted to selectively assert an error signal based on whether the I/O signal has a predetermined relationship with a reference signal, wherein the predetermined relationship holds true during normal operation but fails to hold true when an unexpected event occurs and causes an unexpected change at least one of the I/O signal and reference signal.

Abstract: Instruction fetch unit (IFU) verification is improved by dynamically monitoring the current state of the IFU model and detecting any predetermined states of interest. The instruction address sequence is automatically modified to force a selected address to be fetched next by the IFU model. The instruction address sequence may be modified by inserting one or more new instruction addresses, or by jumping to a non-sequential address in the instruction address sequence. In exemplary implementations, the selected address is a corresponding address for an existing instruction already loaded in the IFU cache, or differs only in a specific field from such an address. The instruction address control is preferably accomplished without violating any rules of the processor architecture by sending a flush signal to the IFU model and overwriting an address register corresponding to a next address to be fetched.

Abstract: A test system uses an instrumented browser to identify events that were not successfully captured during a client web session. The identified events can be used to modify a capture system that captures the client web session. Alternatively, the test system may generate replay rules that are used by a replay system to infer the missed events while replaying of the previously captured client web session. The events can include changes to Document Object Models (DOMs) for web pages used during the web sessions. The DOMs can be used to identify significant web session events and force replay sessions into the correct states.

Abstract: A method for problem determination and resolution in an information technology (IT) system includes receiving a problem ticket, searching a database for a plurality of problem features based on data included in the problem ticket, extracting the plurality of problem features from the database, and generating a problem signature corresponding to the problem ticket, wherein the problem signature comprises at least one non-textual feature extracted from the plurality of problem features.

Abstract: A method for detecting a failure in a serial topology. The method may comprise sending a predetermined pattern to a plurality of devices communicatively connected to an initiator in a serial topology; receiving a return result from each of the plurality of devices in response to the predetermined pattern; recognizing a problem associated with a particular device among the plurality of devices, the problem being recognized based on the return result from the particular device; sending a plurality of test patterns to the particular device; receiving a plurality of test results from the particular device in response to the plurality of test patterns; and determining a cause of the problem based on the plurality of test results, the cause of the problem being at least one of: a cable failure and a device failure.

Abstract: Systems and methods are described that dynamically reprioritize test cases for Model-Based Testing (MBT) during test execution. Test case execution is prioritized according to their potential to detect uncovered failures within a design model.

Abstract: In one embodiment, a protocol aware circuit for automatic test equipment, which includes a protocol generation circuit constructed to retrieve protocol unique data and format the protocol unique data with a selected protocol definition corresponding to a device under test for testing the device under test. The protocol generation circuit may be constructed to retrieve the selected protocol definition from a protocol definition table.

Abstract: A control apparatus includes a lower layer control unit configured to perform control of a load, an upper layer control unit configured to control the lower layer control unit, a communication unit configured to perform communication between the upper layer control unit and the lower layer control unit via a communication line, a detection unit configured to detect power supply voltage of the lower layer control unit, wherein the upper layer control unit detects communication abnormality of the communication unit and notifies the communication abnormality, the upper layer control unit notifying abnormality of power supply voltage of the lower layer control unit, in such a manner as to be identified from the communication abnormality of the communication unit.

Abstract: A communication system includes a switch that switches output ports according to an address of transmission data; a storing unit that stores a first set of addresses associated with the switch; a determining unit that determines, when a second set of addresses including in the transmission data a response to which is not received matches the first set of addresses in the storing unit, that there is a failure in the switch associated with the first set of addresses.

Abstract: A first test script that includes at least one first step for executing a test of a test portal is provided in a computing device. An indication that an event has occurred in response to the test is received in the computing device. A second test script that includes at least one second step for executing the test is generated in the computing device, the at least one second step being at least in part a response to the event.

Abstract: A simulator is partitioned into a functional component and a behavior prediction component and the components are executed in parallel. The execution path of the functional component is used to drive the behavior prediction component and the behavior prediction component changes the execution path of the functional component.

Abstract: Service providers strive to maintain networks with high levels of availability and performance. To maintain the networks, the service providers measure performance and perform network diagnostics. Measuring performance and performing network diagnostics typically involves manual verification of functionality or performing individual tests between user agents. Service providers who maintain networks and service providers who use networks can dynamically run tests with operations of a signaling protocol (e.g., session initiation protocol) to diagnose network problems and determine appropriate responses. An agent manager can coordinate the dynamic tests across multiple user agents to gather more information to increase problem diagnosis accuracy.

Abstract: A failure management device includes a stored position obtainer that obtains stored position data that represents a position at which failure data is generated by an information processing apparatus when a failure is occurring; a failure data obtainer that obtains the failure data generated by the information processing apparatus from a memory device, communicably connected to the information processing apparatus and the failure management device, on the basis of the stored position data; and a configuration controller that changes, on the basis of the failure data obtained by the failure data obtainer, a configuration of the failure management device so as to conform to that of the information processing apparatus. This configuration makes it possible to easily reproduce the failure occurred in the information processing apparatus and consequently, a reproducing test can be accomplished efficiently.

Abstract: Instruction fetch unit (IFU) verification is improved by dynamically monitoring the current state of the IFU model and detecting any predetermined states of interest. The instruction address sequence is automatically modified to force a selected address to be fetched next by the IFU model. The instruction address sequence may be modified by inserting one or more new instruction addresses, or by jumping to a non-sequential address in the instruction address sequence. In exemplary implementations, the selected address is a corresponding address for an existing instruction already loaded in the IFU cache, or differs only in a specific field from such an address. The instruction address control is preferably accomplished without violating any rules of the processor architecture by sending a flush signal to the IFU model and overwriting an address register corresponding to a next address to be fetched.

Abstract: Systems and methods are described that dynamically reprioritize test cases for Model-Based Testing (MBT) during test execution. Test case execution is prioritized according to their potential to detect uncovered failures within a design model.

Abstract: Mechanisms are provided for controlling a fidelity of a simulation of a computer system. A model of the system is received that has a plurality of components. A representation of the plurality of individual components of the system is generated. A component is assigned to be a fidelity center having a highest possible associated fidelity value. Fidelity values are assigned to each other component in the plurality of individual components based on an affinity of the other component to the fidelity center. The system is simulated based on assigned fidelity values to the components in the plurality of individual components.

Abstract: Aspects of the invention relate to techniques for fault diagnosis based on dynamic circuit design partitioning. According to various implementations of the invention, a sub-circuit is extracted from a circuit design based on failure information of one or more integrated circuit devices. The extraction process may comprise combining fan-in cones of failing observation points included in the failure information. The extraction process may further comprise adding fan-in cones of one or more passing observation points to the combined fan-in cones of the failing observation points. Clock information of test patterns and/or layout information of the circuit design may be extracted and used in the sub-circuit extraction process. The extracted sub-circuit may then be used for diagnosing the one or more integrated circuit devices.

Abstract: Model-based testing is performed by repeatedly constructing a test strategy in which each test stimulus will lead to increased test coverage regardless of the nondeterministic choices made by the system under test, and following said strategy until coverage is increased. As soon as no such strategy exists, testing stops.

Abstract: A meta attribute useful for functional coverage is computed based on values comprised by two or more matching fields in a trace. The two or more matching fields may be comprised by a single entry of the trace or by a plurality of entries of the trace. A definition of the meta attribute may define which fields of the entries comprise values useful for computation of the meta attributes. The matching entries may be identified based on identifying values within the entries.

Abstract: Various embodiments related to identifying regions including physical defects in semiconductor devices are disclosed. For example, one embodiment includes receiving an electrical test mismatch reported for a scan chain; identifying a suspect logical region including a plurality of logic cones electrically connected with the scan chain; adjusting a scope of the suspect logical region by simulating data flow within the logic cones, generating simulated scan chain output based on the simulated data flow within the logic cones, and excluding at least one of the logic cones from the suspect logical region based on a comparison of the electrical test mismatch and the simulated scan chain output; after adjusting the scope of the suspect logical region, generating a candidate defect region, the candidate defect region being defined to include physical instantiations of logical cells and logical interconnections included in the suspect logical region; and displaying the candidate defect region.

Abstract: A diagnostic module delivery server includes a diagnostic selecting unit that reads a failure rate of a component from a component database that stores therein the failure rates of the components obtained based on the maintenance history of the components constituting a maintenance target server. Furthermore, the diagnostic selecting unit determines whether to diagnose the component in accordance with the result of comparing the read failure rate of the component and a failure rate reference value that is stored in a diagnostic reference value database. Furthermore, the diagnostic module delivery server transmits, to the maintenance target server, a diagnostic module that is used to diagnose the component in which it is determined, by the diagnostic selecting unit, that the diagnostics is to be performed.

Abstract: A method for software processing includes obtaining change information, which records changes that have been performed in respective locations in software code. The change information is processed so as to assign to at least some of the locations respective priorities, which are indicative of respective likelihoods that the locations contain program faults. The at least some of the locations are presented to a user in accordance with the assigned priorities.

Abstract: A method, system, and computer usable program product for energy-efficient soft error failure detection and masking are provided in the illustrative embodiments. A soft error is injected to occur during execution of a set of instructions. If an output of the execution of the set of instructions is incorrect, a record is made of the instruction that was affected by the injected soft error and led to the incorrect result. This identified instruction is designated as vulnerable to the soft error. Several soft errors are injected with different input data sets over several executions of the same set of instructions, and a probability of each instruction in the instruction set is computed, the probability of an instruction accounting for the vulnerability of the execution of the instruction sets to errors that affect the instruction. A report including several probabilities of instruction vulnerabilities is produced.

Abstract: A method and device for predicting faults in a distributed heterogeneous IT system (100), the method comprising: creating a local checkpoint (19) in an explorer node (10) of said system (100), said local checkpoint (19) reflecting the state of said explorer node (10); running a path exploration engine (14) on said local checkpoint (19) in order to predict faults, wherein a plurality of possible inputs (71) are used by said exploration engine (14) in order to explore different paths, wherein path exploration comprises sending messages to remote client nodes (20), and receiving messages from said remote clients (20); wherein said received messages do not reveal checkpoints of said other nodes, so as to avoid leakage of any confidential information.

Abstract: A system and method is disclosed that has the ability to automatically derive a test execution plan for parallel execution of test cases, while considering the complex dependencies across the test cases and preserving the semantics of test execution. The execution plan, so generated, provides for balanced workload distribution and scheduling of the test cases for improving the test execution cycles of the test suites in a cost effective manner.

Abstract: A method of assessing a computer program under actual working conditions according to one embodiment comprises executing the computer program multiple times under actual working conditions, in response to each unhandled exception encountered during execution of the computer program, creating a corresponding stack frame signature to characterize the state of the program, and comparing the stack frame signatures to determine which unhandled exceptions are likely to have resulted from similar features.

Abstract: A test for testing at least one of hardware or software in a first environment is generated. A desired test configuration is selected based on information regarding respective hardware or software. Test elements are automatically generated based on the desired test configuration, the test elements adapted to test at least one of the hardware or software. At least one of the hardware or software is automatically tested using a subset of the test elements. A result of testing is produced.

Abstract: Methods and apparatus useful for improving the performance of testing and diagnostic operations on user circuit designs potentially across multiple phases of the development lifecycle and across multiple implementation technologies are described. As one example, a single testing and diagnostic stimulus source can variously provide test pattern data to different potential instantiations of the user circuit design by supporting and selectively utilizing a number of DUT-facing communication channels.

Abstract: Method, system and computer program product for template-based vertical microcode instruction trace generation. An exemplary embodiment includes an instruction trace generation method, including generating a testcase for a millicoded instruction in an instruction trace pool, wherein the millicoded instruction is included in a parent instruction trace, processing the testcase to generate a millicode instruction trace snippet, editing the millicode instruction trace snippet to generate a templatized millimode snippet, processing the parent instruction trace, accessing the templatized millimode snippet, updating the templatized millimode snippet with a value from the parent instruction trace, and generating a millicoded instruction trace from the updated templatized millimode snippet.

Abstract: A debugger is operated in a host PC, and in response to operation of the debugger, first and second microprocessors execute an identical debug operation in parallel via first and second debug I/F devices. The host PC obtains internal information (dump results) from the first and second microprocessors via the first and second debug I/F devices and compares internal information (dump results) from the first and second microprocessors to perform failure analysis.

Abstract: The present invention relates to an exception handling test apparatus and method. The exception handling test apparatus includes a generation module configured to generate a modified device driver based on a defect model and information obtained from the device manager, a hooking module configured to hook the device driver using the modified device driver, a scanning module configured to collect test information returned from the hooked modified device driver to the application while the application operates, and an analysis module configured to analyze the collected test information.

Abstract: A method of testing a computer, the method has designating a register as an input-only register having a setting of a value which does not cause an exception interruption with an execution of a specific type of instruction, generating a test instruction array having a plurality of instructions for a test, by assigning a register excluding the input-only register as an output destination of an execution result of each of the plurality of instructions, executing the plurality of instructions included in the generated test instruction array, and evaluating the execution results by the computer.

Abstract: An electronic card (4) comprising a processing unit (7), able to receive a command originating from a diagnostic module (6) and a command originating from a simulation system (3). The electronic card (4) comprises means of managing the execution priority of the command originating from the simulation system (3) relative to the command originating from the diagnostic module (6). A diagnostic system of an electronic card comprising a diagnostic module and means of managing the execution priority of the commands. A simulation method is associated with the electronic card (4). For use in particular for analysing malfunctions on electronic cards (4) incorporated in integration simulators (1).

Abstract: A method and system for subnet defect diagnostics through fault compositing is disclosed. A testing apparatus generates callout data for an integrated circuit device under test. A computer received the callout data, which includes a list of faults. Each fault of the list of faults has associated with it one or more failures and/or conflicts. In order to explain the failures, two or more faults are selected and composited, yielding a composite fault having a composite conflict count. The composite fault is assigned a score based on the composite conflict count, which score determines a candidate composite that best explains the faults of the list of faults. This procedure may be repeated to explain all the failures.

Abstract: A low cost error-based program testing apparatus and method are provided. The testing apparatus according to an embodiment of the present invention generates error programs by adding errors to a test target program, selects a test target error program associated with test data among the error programs using error information obtained through the error addition, receives the test data to execute the test target error program, and tests for presence/absence of the errors. Accordingly, it is possible to reduce a text execution time and testing costs.

Abstract: A method of regression testing a software application in an execution environment is disclosed. The software application interacts with a data storage and is run a first time. While running the software application for the first time, interactions of the software application with the data storage are monitored. Also while running the software application for the first time, first output data written from the software application to the data storage are recorded, and input data received by the software application from the data storage are recorded. The software application is run a second time after the first time. While running the software application the second time, when the software application calls for data from the data storage, at least a portion of the recorded input data is provided to the software application, and, when the software application writes data to the data storage, second output data written by the software application are recorded.

Abstract: An operation management system 12 alleviates the burden on an administrator 103 who carries out reappearance monitoring of a failure that occurred in a computer system 11. The operation management system 12 detects one or more detected events occurring in the computer system 11, and selects a first causal laws code 180 included in a causal laws information 168 based on the causal laws information 168 and the detected event. The operation management system 12, in a case where the composition of the computer system 11 has been changed to eliminate the cause of generation of the detected event, selects a second causal laws code 180 included in a post-change causal laws information 168 based on the post-change causal laws information 168 and the first causal laws code 180, and notifies the administrator 103 of information related to the selected second causal laws code 180.

Abstract: Disclosed in various embodiments are systems and methods providing for storage of mass data such as metrics. A plurality of data models are generated in the server from a stream of metrics describing a state of a system. Each of the metrics is associated with one of a plurality of consecutive periods of time, and each data model represents the metrics associated with a corresponding one of the consecutive periods of time. The data models are stored in a data store and each of the metrics is discarded after use in generating at least one of the data models.

Abstract: Disclosed are an approach form managing and assigning addresses in a connectivity platform that allows for proprietary connectivity modules (Providers) to plug into the operating system. In this disclosure, when a user/application/computing device, connects to another user on another computing device an address is generated for that user. However, because of a limited number of addresses that are available in an address space, it is necessary to ensure that a conflicting address is not present. To ensure this the connectivity platform determines if the address assigned is in conflict with another address associated with users that are located on the other computing devices. If an address is found to be in conflict the connectivity platform reassigns the address until a non-conflicting address is found. If a non-conflicting address cannot be found the connectivity platform blocks the connection between the user and the other user.

Abstract: A computer-readable medium encoded with an instruction check program for making a computer to check a status of execution of an instruction by an I/O simulator that performs an operation simulation according to a structure of an I/O area of a microcomputer, the instruction check program when executed by a computer causes the computer to perform a method including obtaining specification information of the microcomputer describing an input and an output condition of a hardware resource in the I/O area, detecting a simulation of a reference instruction to the hardware resource executed by the I/O simulator, determining correctness of the reference instruction by comparing a content of the simulation of the reference instruction detected by the detecting with the input and output condition of the hardware resource included in the obtained specification information, and outputting an error signal when it is determined that the reference instruction is incorrect.

Abstract: A method includes capturing data that is representative of actions performed by each of a plurality of human user operated clients as they interact with an online software application, loading at least one or more portions of the captured data into one or more automated simulation clients, and using the one or more automated simulation clients to perform load testing of an online server system. A system includes a data capturing stage, one or more automated simulation clients, and a configuration stage.

Abstract: A test apparatus that tests a device under test outputting a data signal and a clock signal indicating a timing at which the data signal is to be sampled, comprising an acquiring section that acquires the data signal output by the device under test, at a timing corresponding to the clock signal; a buffer section that includes a plurality of entries, buffers the data signal acquired by the acquiring section at the timing corresponding to the clock signal sequentially in the entries, and outputs the data signal buffered in the entries at a timing of a timing signal generated according to a test period of the test apparatus; and a judging section that judges pass/fail of the device under test based on a result of a comparison between the data signal output from the buffer section and an expected value.