Abstract: Techniques are disclosed for memory management in a streams processing environment. Certain aspects of the present disclosure provide a method generally including monitoring, via a streams manager for a distributed application, an amount of memory used by a group of executing processes, and for each group, comparing the amount of memory used by the group against a memory threshold, and determining whether the memory used by the group exceeds a first threshold, and reducing memory usage by the group when the memory used by the group exceeds the first threshold.

Abstract: Techniques are disclosed for memory management in a streams processing environment. Certain aspects of the present disclosure provide a method generally including monitoring, via a streams manager for a distributed application, an amount of memory used by a group of executing processes, and for each group, comparing the amount of memory used by the group against a memory threshold, and determining whether the memory used by the group exceeds a first threshold, and reducing memory usage by the group when the memory used by the group exceeds the first threshold.

Abstract: Monitoring a level of utilization is provided. An initial numerical range based, at least in part, on a count of service channels of a device is determined. A candidate numerical range, defined by an upper value and a lower value, based, at least in part, on the initial numerical range, is determined. A level of utilization of a first measurement interval of the device is estimated by: repeatedly updating the lower value and the upper value based, at least in part, on the level of utilization, until the lower value and the upper value differ less than a pre-determined threshold; and determining an estimated level of utilization based, at least in part, on the lower value and the upper value. The estimated level of utilization is reported.

Abstract: In an approach for utilizing overlay hooks to increase code coverage, a processor inserts an overlay hook in program code at a location within the program code corresponding to a condition statement. A processor executes the program code. Upon reaching the overlay hook, a processor branches to a set of instructions operative to document an outcome of the condition statement. A processor executes the condition statement. A processor records the outcome of the condition statement.

Abstract: A system and method to select a packet format based on a number of executed threads is disclosed. In a particular embodiment, a method includes determining, at a multi-threaded processor, a number of threads of a plurality of threads executing during a time period. A packet format is determined from a plurality of formats based at least in part on the determined number of threads. Data associated with execution of an instruction by a particular thread is stored in accordance with the selected format in a memory (e.g., a buffer).

Abstract: Input sequence information may be analyzed and quantified using n-gram analysis of inputs received by an application. The sequences of inputs may be represented by n-grams, and the frequency of the various n-grams may indicate the ‘real world’ uses of the application in production, which may be compared to a test suite whose coverage may be quantified using a similar n-gram analysis. A coverage factor may compare the observed inputs to the application in production to the test suite for the application. The n-grams may be further quantified or prioritized by resource utilization and several visualizations may be generated from the data.

Abstract: A test system registers a series of tests that reference different software enhancements added to an application within a database system. The test system enables individual software enhancements referenced by the tests and then runs log lines through the application to produce test structured query language (SQL). The database system compares the test SQL with baseline SQL produced by the application without enabling the software enhancements. The database system executes the test SQL and captures performance metrics when the test SQL is different from the baseline SQL. Comparing SQL results avoids processing and capturing performance metrics for log lines not affected by the software enhancements. Incrementally running the log lines with one software enhancement enabled at a time also allows the test system to isolate the performance impact of individual software enhancements on the database system.

Abstract: Techniques for using functional testing to detect run-time impacts of code modifications. A method includes accessing a workflow including a plurality of stages for processing reads. The stages are defined based on modifiable code and include a first stage for aligning reads with a corresponding portion of a reference data set and a second stage for collectively analyzing data corresponding to the aligned reads. The method includes identifying functional testing specifications to correspond with the workflow, including a definition of which stages are to be performed during functional testing, a reduced reference data set, and a set of reads. The method includes performing the functional testing using the reduced reference data set and the set of reads, detecting a result generated via the performance, and outputting the result.

Abstract: Periodicity similarity between two different tracer objectives may be used to identify additional input parameters to sample. The tracer objectives may be individual portions of a large tracer operation, and each of the tracer objectives may have separate set of input objects for which data may be collected. After collecting data for a tracer objective, other tracer objectives with similar periodicities may be identified. The input objects from the other tracer objectives may be added to a tracer objective and the tracer objective may be executed to determine a statistical significance of the newly added objective. An iterative process may traverse multiple input objects until exhausting possible input objects and a statistically significant set of input objects are identified.

Abstract: An application list reading part 220 reads an application list 122. An application collecting part 230 acquires a source code 111 of an installed application indicated by the application list 122. The application collecting part 230 also acquires a source code 111 of an additional application. A program analyzing part 240 performs program analysis concerning a new execution program 123 using the source codes 111. If a bug will not occur in the new execution program 123, a program creating part 250 creates a new execution program 123. Then, a program updating part 260 writes the new execution program 123 to an electronic control device 121 and adds an additional application name to the application list 122.

Abstract: Systems and methods for generating a language-independent representation of a software project's structure from its code comprises: generating a language-specific representation of code structure from a software project; augmenting the language-specific representation with additional, inferred information about its components; and mapping from language-specific components to language-independent components.

Abstract: Debugger system, method and computer program product for debugging instructions.

Abstract: A diagnostic workflow file can be used to control the future diagnostic actions taken by a debugger without user interaction with the debugger when it executes. The diagnostic workflow file is used by a debugger during a debug session. The debugger performs the actions directed by the diagnostic workflow file to simulate an interactive live debug session. The diagnostic workflow file can include conditional diagnostic operations whose execution depends on the state of program variables, diagnostic variables and diagnostic primitives in the debug session.

Abstract: Methods for automatically identifying and instrumenting application classes and methods for a particular application are described. In some embodiments, application code (e.g., bytecode or source code) associated with the particular application may be parsed to identify classes and methods within the application code and to identify terminal components (e.g., methods or function calls) and non-terminal components (e.g., control flow statements). Once the terminal components and non-terminal components have been identified, a complexity model and a corresponding score for each of the classes and methods within the application code may be determined. The complexity model may be used to estimate the number of computations that may be required if a particular class or method is used by the particular application. Application classes and methods corresponding with a score that is greater than a threshold may be instrumented by inserting probes into the identified classes and methods.

Abstract: A method for setting one or more breakpoints within executable program code of an embedded device is described. The method comprises copying at least one area of non-volatile memory (NVM) of the embedded device, comprising at least one instruction at which a breakpoint is to be set, into at least one area of overlay memory replacing within the overlay memory the at least one instruction at which a breakpoint is to be set with a breakpoint operation code, and enabling a mapping of the at least one area of NVM, comprising the at least one instruction at which a breakpoint is to be set, to the at least one area of overlay memory during execution of the program code within the embedded device.

Abstract: A method for using a retain block in application code executing on a virtual machine includes identifying an instruction in application code, the instruction pertaining to an object, determining the instruction is part of a retain block, prior to executing the instruction, determining whether the instruction is to cause the object to be modified, and when the instruction is to cause the object to be modified, storing data indicating a first state of the object in a retain block store and causing the first state of the object to be modified using a second state. Also, the method includes in response to an error occurring during an execution of the instruction, returning the object from the second state to the first state using the stored data.

Abstract: Systems and methods described here include embodiments for generating component test code for use in an application test generation program used to test an application under test. Certain embodiments include a computer server running the application test generation program with an integrated custom engine and function libraries, the custom engine configured to allow a user to define a component, allow the user to select at least one application area, allow the user to define a component step for the defined component, wherein defining a component step includes, an object repository associated with the selected application area, at least one object option associated with the selected object repository, wherein the selection of the object option determines subsequent sets of object options for selection by the user, repeating, and to generate the component test code, via associations in the function libraries between component test code portions and the defined component steps.

Abstract: A system and method of debugging a multi-threaded process with at least one running thread and at least one suspended thread is disclosed. Embodiments utilize a blocking function to block the thread of a process while other threads are allowed to run. The blocking function may be executed in a suspended thread by a debugger under control of a thread blocking controller. The other threads may implement interprocess communication channels for enabling communication between the process and another application. A simulated user interface (UI) of a debugger enables interaction with users while a hardware simulation thread is blocked, where blocking of the hardware simulation thread may be implemented by a thread blocking component implemented externally to the debugger. Where a thread blocking controller is implemented within the debugger, a debugger UI may interact with a user while the hardware simulation thread is blocked and interprocess communication threads are running.

Abstract: In determining code coverage, execution data indicative of portions of a program that have been executed for testing is received. The program is analyzed based on the execution data and a control flow for the program. Based on the analysis, it is determined that additional portions of the program, which are not indicated by the execution data, have also been executed. Related methods, systems, and computer program products are also discussed.

Abstract: The current application is directed to crosscutting functionalities, including byte-code instrumentation, error logging, and other such crosscutting functionalities. These crosscutting functionalities generally violate, or run counter to, modern code-development strategies and programming-language features that seek to partition logic into hierarchically organized compartments and modules with related functionalities, attribute values, and other common features. In particular, the current application is directed to byte-code instrumentation introduced into a computer program for collecting data, such as execution traces, elapsed times for routine execution, and other information at run time for logging and subsequently manual, semi-automatic, or automatic analysis. The current application is particularly directed to byte-code instrumentation that automatically filters collected data in order to log only data having greatest value for subsequent analysis.

Abstract: Provided are fault injection testing apparatus and method which inject faults that may occur in a system or a source file that a user wants to examine and examine which processes are performed by the system or source file when the faults occur.

Abstract: The present invention relates to the field of debugging of compiled programs in a hardware security module such as a microprocessor card. A module according to the invention includes a microprocessor and a compiled program to be executed by the microprocessor in order to carry out an operation. The compiled program includes at least one debugging instruction which whether or not it is executed does not modify the execution of the operation. And, the hardware security module includes an element of inhibiting or activating the debugging instruction during the execution of the compiled program.

Abstract: Embodiments of the present application relate to a code coverage rate determination method, a code coverage rate determination system, and a computer program product for determining code coverage rate. A code coverage rate determination method is provided. The method includes retrieving source code of a program, determining theoretical number of log file output points included in the source code and location information of the log file output points, retrieving log files actually outputted during the execution of the program, determining an actual number of log file output points of the actual outputted log files based on the location information of the corresponding log file output points recorded in each log file, and determining a code coverage rate of the program based on the theoretical number of log file output points and the actual number of the log file output points of the actual outputted log files.

Abstract: An integrated circuit includes a processor core, a clock control circuit and a debugging circuit. The processor core processes target software. The clock control circuit determines whether an electrical connection exists between the processor core and an external debugger and generates a determination result. The clock control circuit generates an output clock signal based on the determination result. The external debugger performs a debugging operation for the target software. The output clock signal is selectively activated based on the determination result and an input clock signal. The debugging circuit provides information with respect to the debugging operation for the target software to the external debugger based on the output clock signal.

Abstract: Various aspects provide forced halt functionality for a processor to facilitate troubleshooting of processor hang situations. In the event that the processor initiates a transaction that does not receive a completion acknowledgement, halt detection logic can initiate a forced halt sequence that causes the processor to abort all pending transactions and transition to a debug state so that the internal state of the processor can be viewed. In addition, the processor can maintain a record of the processor state at the time that the hung transaction was dispatched, which can be viewed during debug mode to facilitate determining a cause of the hung transaction.

Abstract: We describe techniques which relate to bi-directional, in particular backwards, debugging of computer programs. Thus we describe identifying processes with shared memory access, such as threads or multicore processes, by arranging process (thread) memory ownership to deliberate provoke memory page faults to identify and handle concurrent memory access by multiple threads in such a manner as to enable deterministic replay, and hence backwards debugging.

Abstract: The present disclosure involves systems and computer-implemented methods for installing software hooks. One process includes identifying a target method and a hook code, where the hook code is to execute instead of at least a portion of the target method, and wherein the target method and the hook code are executed within a managed code environment. A compiled version of the target method and a compiled version of the hook code are located in memory, where the compiled versions of the target method and the hook code are compiled in native code. Then, the compiled version of the target method is modified to direct execution of at least a portion of the compiled version of the target method to the compiled version of the hook code. The non-compiled version of the target method may be originally stored as bytecode. The managed code environment may comprise a managed .NET environment.

Abstract: A facility is provided to enable operator message commands from multiple, distinct sources to be provided to a coupling facility of a computing environment for processing. These commands are used, for instance, to perform actions on the coupling facility, and may be received from consoles coupled to the coupling facility, as well as logical partitions or other systems coupled thereto. Responsive to performing the commands, responses are returned to the initiators of the commands.

Abstract: A facility is provided to enable operator message commands from multiple, distinct sources to be provided to a coupling facility of a computing environment for processing. These commands are used, for instance, to perform actions on the coupling facility, and may be received from consoles coupled to the coupling facility, as well as logical partitions or other systems coupled thereto. Responsive to performing the commands, responses are returned to the initiators of the commands.

Abstract: The present invention relates to a communication test apparatus. The communication test apparatus includes an insertion module configured to insert a test agent into the process control block, a hooking module configured to hook a test target to a test code using the test agent when an event-related to communication occurs between the plurality of processes, a scanning module configured to collect pieces of test information about communication between the plurality of processes when the test target is hooked to the test code, and a logging module configured to store the pieces of test information collected by the scanning module.

Abstract: A method and system for providing a self-test configuration in a device is disclosed. The method and system comprise providing a self-test mechanism in a kernel space of a memory and enabling a hook in a user space of the memory, wherein the hook is in communication with the self-test mechanism. The method and system also include running the self-test driver and utilizing the results.

Abstract: The disclosure discloses a method and a system for detecting an abnormality of a network processor. The method comprises the following steps: an abnormality detection operation code is added into an execution flow of each thread in a network processor, and the network processor sets a flag bit corresponding to a current thread in an abnormality protection flag data area in a shared memory to a first flag when executing the abnormality detection operation code in the current thread; and when a period of a timer is expire, a coprocessor detects all the flag bits in the abnormality protection flag data area in the shared memory, determines that a thread corresponding to a flag bit which is not the first flag is abnormal when detecting that not all the flag bits are the first flag, and sets all the flag bits to a second flag when detecting that all the flag bits are the first flag.

Abstract: A method, system, and computer program product for reversibly instrumenting a computer software application is described. The method may comprise creating a map indicating a plurality of locations of application instruction sections within instructions of a computer software application. The method may further comprise inserting a plurality of instrumentation sections into the computer software application instructions. The method may also comprise updating the map to indicate the locations of the instrumentation sections within the computer software application instructions, where the indications in the map of the locations of the instrumentation sections are distinguishable from the indications in the map of the locations of the application instruction sections.

Abstract: A flexible system for collecting and reporting instrumentation metrics relating to performance of a software product. Computing devices that execute the software product receive a manifest that specifies the manner in which instrumentation metrics are collected and reported, including what instrumentation metrics are collected. Based on the manifest, an instrumentation metrics client associated with a software product may retrieve instrumentation data from a software product or other sources. The metrics client may then generate one or more instrumentation metrics, based on the instrumentation data, in accordance with instructions in the manifest. The metrics client may then take one or more actions based on the instrumentation metrics and the manifest, such as reporting the information to an instrumentation metrics server for aggregation and analysis by the metrics server or performing escalation actions that can modify the metrics collected and reported.

Abstract: A method for debugging an application includes obtaining first and second fusible operation requests; if there is a break point between the first and the second operation request, generating a first set of compute kernels including programs corresponding to the first operation request, but not to the second operation request; and generating a second set of compute kernels including programs corresponding the second operation request, but not to the first operation request; if there is no break point between the first and the second operation request, generating a third set of compute kernels which include programs corresponding to a merge of the first and second operation requests; and arranging for execution of either the first and second, or the third set of compute kernels, further including debugging the first or second set of compute kernels when there is a break point set between the first and second operation requests.

Abstract: While system-directed checkpointing can be implemented in various ways, for example by adding checkpointing support in the memory controller or in the operating system in otherwise standard computers, implementation at the hypervisor level enables the necessary state information to be captured efficiently while providing a number of ancillary advantages over those prior-art methods. This disclosure details procedures for realizing those advantages through relatively minor modifications to normal hypervisor operations. Specifically, by capturing state information in a guest-operating-system-specific manner, any guest operating system can be rolled back independently and resumed without losing either program or input/output (I/O) continuity and without affecting the operation of the other operating systems or their associated applications supported by the same hypervisor.

Abstract: A computer program product for handling communication link problems between a first communication means and a second communication means. Data signals, control signals and/or error information are transferred between the first communication means and the second communication means using the communication link. The method includes activating a static identification pattern in the first communication means representing an error information, and stopping a clock signal (Clk) inside the first communication means to freeze a present error condition, in response to a communication link problem being detected, and transferring the activated static identification pattern permanently and/or repeatedly to the second communication means using the communication link.

Abstract: A test controller performs a test of a test-target component of a test-target system so as to generate at least one fail event indicating a possible fault in the test-target component. A trouble-shooting and analysis tool probes the test controller and/or hardware of the test-target system to investigate potential causes of the fail event other than a fault of said software component. The trouble-shooting and analysis tool then analyzes fail data including probe data to evaluate potential causes of the fail event.

Abstract: Described is a probabilistic concurrency testing mechanism for testing a concurrent software program that provides a probabilistic guarantee of finding any concurrent software bug at or below a bug depth (that corresponds to a complexity level for finding the bug). A scheduler/algorithm inserts priority lowering points into the code and runs the highest priority thread based upon initially randomly distributed priorities. When that thread reaches a priority lowering point, its priority is lowered to a value associated (e.g., by random distribution) with that priority lowering point, whereby a different thread now has the currently highest priority. That thread is run until its priority is similarly lowered, and so on, whereby all schedules needed to find a concurrency bug are run.

Abstract: Provided are a computer program product, system, and method for managing traces to capture data for memory regions in a memory. A trace includes a monitor parameter used by a trace procedure to monitor data in a memory device. A frequency is determined at which the trace procedure monitors the memory device. The trace procedure is invoked at the determined frequency to perform trace procedure operations comprising determining a region in the memory device according to the monitor parameter and copying data in the determined region to trace data in a data space.

Abstract: A method for identifying, based on instructions stored externally to a processor containing a cache memory, a functional portion of the cache memory, then loading cache test code into the functional portion of the cache memory from an external source, and executing the cache test code stored in the cache memory to test the cache memory on a cache-line-granular basis and store fault information.

Abstract: The system and method provide establishment of hooks in a send-path at inter-object interfaces of a layered stack of the storage driver and hooks in the completion-path execution sequence of storage driver of a storage system, the completion-path hook inserts replacement storage response messages to simulate the specified storage access error.

Abstract: The present invention enables program codes to be shared among processors 211. To prevent the debug operation of one processor 211 from affecting the debug operation of the other processors 211, when detecting a breakpoint during execution of a program code, a debugger 410 or a debugger stub 520 controls the execution of the program code while exchanging breakpoint information 800 with the other debuggers 410 or the other debugger stubs 520. Furthermore, a circuit 170 is created which prevents the program code being carelessly rewritten due to thermal runaway, a bug, and the like of a processor 211, and the protection setting by the protection logic 71 in the circuit 170 is released only in case the processor 211 accesses each of a plurality of registers from 65 to 67 in specified order.

Abstract: A debugging apparatus and method are provided. The debugging apparatus may include a breakpoint setting unit configured to store a first instruction corresponding to a breakpoint in a table, stop a program currently being executed, and insert a breakpoint instruction including current location information of the first instruction into the breakpoint; and an instruction execution unit configured to selectively execute one of the breakpoint instruction and the first instruction according to a value of a status bit.

Abstract: A method and apparatus for controlling a processor to execute in a single step mode such that a single instruction from the instruction stream is executed, the processor determines if the single instruction is one of at least one predetermined type of instruction and stores a type indicator in a data storage location and a diagnostic exception is taken after the processor has processed the single instruction. Additionally, a diagnostic operation is performed including accessing the type indicator stored in the data storage location and, when the single instruction was not one of the predetermined type, controlling the processor to continue executing instructions in the single step mode, and, when the single instruction was one of the at least one predetermined type, controlling the processor to exit the single step mode and not execute the next instruction within the instruction stream as a single instruction followed by an exception.

Abstract: Embodiments relate to building, by a computing device, a pseudo-random dynamic instruction stream that comprises instructions configured to perform a transaction execution. The computing device may cause the transaction execution to be tested in a multi-processing system based on the instruction stream. A status of the test may be output to one or more output devices.

Abstract: Method for providing programming support to a debugger are disclosed. The method includes defining at least one debugger programming statement, and instructing the debugger to execute the at least one debugger programming statement which modifies a least a portion of the computer program during execution of the computer program without recompiling the computer program. The debugger may be instructed to execute the at least one debugger programming statement at a specified position of the computer program. The at least one debugger programming statement may include a delete instruction that instructs the debugger to prevent one or more programming statements at a specified position in the computer program from being executed. The debugger may be instructed to execute the at least one debugger programming statement instead of one or more programming statements at a specified position in the computer program without recompiling the computer program.

Abstract: Embodiments of the invention include methods, apparatuses, and systems for automatically identifying a synchronization sub-pattern associated with a test pattern. A test and measurement instrument is triggered in response to a first instance of a trigger pattern in a data stream. A trigger-to-trigger counter begins counting at the time of the first trigger event. The test and measurement instrument is again triggered in response to a second instance of the trigger pattern in the data stream. The count is ended at this time. The count is then compared to a predefined length of the test pattern, and if equal, it is automatically determined that the trigger pattern is the unique synchronization sub-pattern associated with the test pattern.

Abstract: System, and computer program product for providing programming support to a debugger are disclosed. The debugger executes at least one debugger programming statement which modifies at least a portion of the computer program during execution of the computer program without recompiling the computer program. The debugger may be instructed to execute the at least one debugger programming statement at a specified position of the computer program. The at least one debugger programming statement may include a delete instruction that instructs the debugger to prevent one or more programming statements at a specified position in the computer program from being executed. The debugger may be instructed to execute the at least one debugger programming statement instead of one or more programming statements at a specified position in the computer program without recompiling the computer program.

Abstract: A test system that enables real-time interactive debugging of a device under test (DUT) using native customer code. A translation module may format, in real time, debug commands, corresponding to a user input, into a format recognizable by instruments in a tester. The user input may be a test program or test instructions written in a high-level programming language. The translation module may translate the user's debug commands into lower-level test instrument commands, based on which the tester may apply control signals to a processor in the DUT to test subsystems of the DUT. A result of the test may be provided to the translation module, which may, in real time, format another debug command, or provide an indication of the result to the user. The translation module may thus enable a user to step-through and modify native customer code in an interactive manner to debug a DUT.