Abstract: System(s) and method(s) facilitate testing and manipulating an application internally within a client-server configuration coordinated by a communicator object. A client test-object conveys a test to a server test-object through a remoting channel and over disparate processes, e.g., a test process and designer process. A service in an application developer intermediates communication across a communicator thread and a designer thread. In response to a test, information is received in the client end as a serialized wrapper object. Manipulation is accomplished by deserializing and modifying the received information, and then transmitting the information in a serialized object through the remoting channel across processes, and via the intermediary service component across threads in the designer process. Testing and manipulation can facilitate optimizing an application, improving application's functionality as well as a user experience.

Abstract: A method for enhancing debugger performance of hardware assisted breakpoints across multiple units includes deferring all active location breakpoints within the multiple modules, and subsequently activating each valid location breakpoint in a present one of the multiple modules being entered.

Abstract: The present invention relates to debugging of computer programs, and in particular to bi-directional debugging.

Abstract: A computer-implemented method for verifying a RAIM/ECC design using a hierarchical injection scheme that includes selecting marks for generating an error mask, selecting a fixed bit mask based on the selected marks, determining whether to inject errors into at least one of a marked channel and at least one marked chip of a channel; and randomly injecting errors into the at least one of the marked channel and the at least one marked chip when determined.

Abstract: According to the invention, an IP core is clocked during a debugging operation by switching from the clock used for testing the device under test to a clock oscillator or any other free-running clock source.

Abstract: A method and system of checkpointing single process application groups and multi-process application groups. In an exemplary embodiment, the method may include creating at least one full checkpoint for each application in an application group, and creating at least one incremental application checkpoint for each application in the application group. Further, each of the at least one incremental application checkpoint may be automatically merged against a corresponding full application checkpoint. Further, checkpointing may be synchronized across all applications in the application group. In the exemplary embodiment, each application may use both fork( ) and exec( ) in any combination.

Abstract: A debug method for computer system is disclosed. The method includes the following steps. Firstly, a first index is increased. Next, a first debug data to a jth debug data are received via a debug port of controller. Then, the first debug data to the jth debug data are sequentially stored to a first memory block of a storage unit of the controller according to the second index of controller. Afterwards, the (i+1)th debug data to the jth debug data are copied to the second memory block from the first memory block according to the increased first index before a controller's power supply is removed or the computer system enters a sleep state. Lastly, an application is implemented so that the second memory block is read according to the first index; wherein, i and j are integers.

Abstract: Method and systems for allocating test scripts across a plurality of test machines is described. A set of test scripts may be maintained where the set of test scripts includes a plurality of test scripts for allocation to a plurality of test machines. A first request for a first test script task may be received from a first test machine of a plurality of test machines. A determination may be made as to whether each test script within the set of test scripts has been allocated. If not, a first unallocated test script to allocate to the first test machine may be determined, and a first test script task may be allocated to the first test machine where the first test script task includes the first unallocated test script. The first unallocated test script then may be identified as an allocated test script in the set of test scripts.

Abstract: A method and system for performing parallel tasks in a computer system includes invoking a single-threaded operating environment in a computer, invoking under the single-threaded operating environment a first task to be performed by a first processor, invoking under the single-threaded operating environment a second task to be performed by a second processor, while the first task is still being performed, and receiving results from the first and second tasks.

Abstract: A method, system and program product for recording a program execution comprising recording processor context for each thread of the program, results of system calls by the program, and memory pages accessed by the program during an execution interval in a checkpoint file. Processor context includes register contents and descriptor entries in a segment descriptor table of the operating system. System calls are recorded for each program thread, tracked by an extension to the operating system kernel and include returned call parameter data. Accessed memory pages are recorded for each program process and include data, libraries and code pages. The program address space, processor context, and program threads are reconstructed from checkpoint data for replaying the program execution in a different operating system environment.

Abstract: A checking system is described for determining whether a component is thread safe in the course of interacting with two or threads in a client environment. The checking system uses a manual, automatic, or semi-automatic technique to generate a test. The checking system then defines a set of coarse-grained observations for the test, in which the component is assumed to exhibit linearizability when interacting with threads. The set of coarse-grained observations may include both complete and “stuck” histories. The checking system then generates a set of fine-grained observations for the tests; here, the checking system makes no assumptions as to the linearizability of the component. The checking system identifies potential linearizability errors as those entries in the set of fine-grained observations that have no counterpart entries in the set of coarse-grained observations. The checking system may rely on a stateless model checking module to perform its functions.

Abstract: For some data processing systems, it is important to be able to handle overlapping debug events generated by a shared set of debug resources which are trying to cause both exception processing and debug mode entry. However, exception processing and debug mode entry generally have conflicting requirements. In one embodiment, exception priority processing is initially given to the software debug event. Normal state saving is performed and the first instruction of the debug exception handler is fetched, but not executed. Priority is then switched from the software debug event to the hardware debug event and a debug halted state is entered. Once processing of the hardware debug event has been completed, priority is returned to the software debug event and the debug exception handler is executed.

Abstract: Techniques for creating a virtual appliance in a virtualization environment are provided. The techniques include implementing a framework, wherein the framework comprises a knowledge representation scheme for describing library knowledge to specify one or more libraries that are used for interaction between two or more appliance components, and using the framework to instrument the one or more libraries via use of the library knowledge, record each of one or more communication parameter values in an original environment, and package one or more disk images, wherein the one or more disk images contain the one or more instrumented libraries, the one or more communication parameter values, and translation logic, to create a virtual appliance.

Abstract: In one embodiment, the invention comprises partial fault tolerant stream processing applications. One embodiment of a method for implementing partial fault tolerance in a stream processing application comprising a plurality of stream operators includes: defining a quality score function that expresses how well the application is performing quantitatively, injecting a fault into at least one of the plurality of operators, assessing an impact of the fault on the quality score function, and selecting at least one partial fault-tolerant technique for implementation in the application based on the quantitative metric-driven assessment.

Abstract: A runtime system implemented in accordance with the present invention provides an application platform for parallel-processing computer systems. Such a runtime system enables users to leverage the computational power of parallel-processing computer systems to accelerate/optimize numeric and array-intensive computations in their application programs. This enables greatly increased performance of high-performance computing (HPC) applications.

Abstract: System for testing a multitasking computation architecture, comprising a set of processors linked by data communication channels, comprising a generating stage for generating sequences of test instructions based on characteristics of said processors comprising programming rules for the computation processors, characterized in that it comprises a control stage for the stage for generating sequences based on data representative of the data communication channels.

Abstract: In an embodiment, a method of testing an error correction scheme includes selectively observing and controlling data at one or more intermediate test points within an error correction circuit. Erroneous data may be selectively injected at a first intermediate test point and data related to the erroneous data may be observed at a second intermediate test point.

Abstract: A data processing system is provided with breakpoint circuitry having breakpoint registers which can specify a variety of different types of breakpoint conditions. These breakpoint conditions include register access breakpoints which are triggered when an access is made to either a general purpose register or a configuration register. The breakpoints can also include input/output port access breakpoints which are triggered when an access is made to a predetermined one of a plurality of input/output ports by an appropriate program instruction or in another way.

Abstract: A method and apparatus for efficient register checkpointing is herein described. A transaction is detected in program code. A recovery block is inserted in the program code to perform recovery operations in response to an abort of the first transaction. A roll-back edge is potentially inserted from an abort point to the recovery block. A control flow edge is inserted from the recovery block to a entry point of the transaction. Checkpoint code is inserted before the entry point to backup live-in registers in backup storage elements and recovery code is inserted in the recovery block to restore the live-in registers from the backup storage elements in response to an abort of the transaction.

Abstract: A software component is executed to carry out a task, the task including a subtask. An external function is called to perform the subtask, the external function executing in a separate thread or process. The component receives an observation recorded by the external function, the observation including an identifier of a possible error condition and instance data associated with the possible error condition. The possible error condition being a cause of the failure of the external function to carry out the subtask. If the task cannot be completed, then a new observation is recorded along with the received observation, the new observation being related to a possible error condition of the component, which is a cause of the failure of the component to carry out the task. When the task can be completed despite the failure of the external function, the observation recorded by the external function is cleared.

Abstract: A debug support device for debugging a multiprocessor configured by a plurality of unit processors a unit processor stop section realized by a plurality of the unit processors executing a program for each of the threads, and any one of the plurality of unit processors performing a process of stopping a unit processor executing a thread in which exception handling occurs together with unit processors executing other threads when the exception handling of software occurs by a break point of a part of the plurality of threads; and a debugging execution section for performing a debugging process of detecting information about a state of the plurality of unit processors stopped by the unit processor stop section.

Abstract: The present invention certifies control modules of engineered safety feature instruments for a power plant automatically. The control modules can be tested before storing or operating. The test is done with enhanced testing speed and saved cost. Thus, safety of the control modules is confirmed.

Abstract: A data storage device (DSD) tester is disclosed for testing a DSD. The DSD tester comprises control circuitry operable to receive production line data through an interface, wherein the production line data is related to the DSD. The control circuitry executes a DSD test on the DSD, and transmits failure data generated by the DSD test and the production line data to a failure information database.

Abstract: A data storage device (DSD) tester for testing a DSD is disclosed. The DSD tester comprises control circuitry operable to receive a DSD log from the DSD, wherein the DSD log comprises at least one entry identifying at least one error condition. A sequence of commands associated with the error condition is executed in order to determine whether the DSD is defective.

Abstract: A test case manager selects a first test case and a second test case from a plurality of test cases. The test case manager provides the first test case to a first processor and provides the second test case to a second processor. As such, the first processor executes the first test case and the second processor executes the second test case. After the execution, the test case manager loads the first test case onto the second processor and loads the second test case onto the first processor. In turn, the first processor executes the second test case and the second processor executes the first test case.

Abstract: A test system for performing tests on devices under test (DUTs) includes a storage device storing test data for performing the tests on the DUTs, a shared processor for generating the test data, storing the test data in the storage device and generating a test control signal including one or more test instructions for executing the tests, and, for each DUT, a dedicated processor configured to receive a test control signal from the shared processor, and in response to the test control signal, transfer the test data for one of the test instructions to the DUT to execute that test instruction and verify the completion of that test instruction.

Abstract: A method is provided for generating a test case for testing a program, which can include analyzing instructions of the program to identify basic blocks and superblocks, each basic block containing at least one executable instruction, and each superblock containing a plurality of basic blocks. The method can include executing instructions by a processor to perform determining respective weights of superblocks, each weight representing a number of basic blocks which require execution when the superblock is executed; determining the constraints which cause a superblock having a high weight to be executed, and using the determined constraints to generate a test case which, upon execution of the program, causes the high weight superblock to be executed.

Abstract: The invention relates to a data processing system comprising a central processing unit, a first memory coupled to the central processing unit for storing variable data values, an eventing engine coupled to the central processing, a debug module coupled to the central processing unit and to the eventing engine for receiving the variable data values by way of the eventing engine in real time and configured to trigger breakpoints; and an interface to connect to an external device. Both event-based variable watching and debugging can occur contemporaneously by a user using an external device connected to the interface.

Abstract: A method for unit testing of business processes for Web services, including steps of mapping the Web service description language (WSDL) elements of a process under test and its partner processes into equivalent Object-Oriented language (OO) elements, and performing testing on the process under test based on Object-Oriented unit testing frameworks. Each Web service interface of the process under test and its partner processes is mapped into an equivalent OO interface, partner stubs are generated on basis of the OO interfaces of the partner processes, WSDL binding and service port information are defined for the generated partner stubs, test cases are formed which contain test logic describing the service invocations between the process under test and its partner processes, and the test cases are executed, wherein the partner stub and its associated mock object collectively implement the service of a corresponding partner process.

Abstract: A method of instrumentation, preferably a computer implemented method for instrumentation, in a program which contains an original program. The original instruction is copied into a user address space which has an unused stack space. When a breakpoint is encountered the original instruction is executed out-of-line in the unused stack space by single stepping. Using this debugging in a multithreaded environment is advantageous as all threads will switch into the unused stack space and execute the breakpoint.

Abstract: Disclosed is a method for running a first code generated by a Software-based Redundant Multi-Threading (SRMT) compiler along with a second code generated by a normal compiler at runtime, the first code including a first function and a second function, the second code including a third function. The method comprises running the first function in a leading thread and a tailing thread (104); running the third function in a single thread (106), the leading thread calls the third function and running the second function in the leading thread and the tailing thread (108), the third function calls the second function. The present disclosure provides a mechanism for handling function calls wherein SRMT functions and binary functions can call each other irrespective of whether the callee function is a SRMT function or a binary function and thereby dynamically adjusts reliability and performance tradeoff based on run-time information and user selectable policies.

Abstract: Disclosed is a method for running a first code generated by a Software-based Redundant Multi-Threading (SRMT) compiler along with a second code generated by a normal compiler at runtime, the first code including a first function and a second function, the second code including a third function. The method comprises running the first function in a leading thread and a tailing thread (104); running the third function in a single thread (106), the leading thread calls the third function and running the second function in the leading thread and the tailing thread (108), the third function calls the second function. The present disclosure provides a mechanism for handling function calls wherein SRMT functions and binary functions can call each other irrespective of whether the callee function is a SRMT function or a binary function and thereby dynamically adjusts reliability and performance tradeoff based on run-time information and user selectable policies.

Abstract: An apparatus comprising an initiator circuit and a target circuit. The initiator circuit may be configured to (i) communicate with a network through a first interface and (ii) generate testing sequences to be sent to the network. The target circuit may be configured to (i) receive the testing sequences from the network through a second network interface and (ii) respond to the testing sequences.

Abstract: A system for testing a video memory reliability of a video card includes an input module, a data read/write module, a data processing module, a data comparison module, and an output module. The input module is capable of activating a testing program which includes an original image file. The data read/write module is capable of writing the original image file in the video memory from the testing program, and reading the image file data stored in the video memory during the writing process for storing the read image file data to form a new image file. The data processing module is capable of calculating hash values of the original and new image files using hash function(s). The data comparison module is capable of comparing hash values, and outputting the comparison result. The output module is capable of indicating whether the video card is normal according to the comparison result.

Abstract: Method and systems for allocating test scripts across a plurality of test machines is described. A set of test scripts may be maintained where the set of test scripts includes a plurality of test scripts for allocation to a plurality of test machines. A first request for a first test script task may be received from a first test machine of a plurality of test machines. A determination may be made as to whether each test script within the set of test scripts has been allocated. If not, a first unallocated test script to allocate to the first test machine may be determined, and a first test script task may be allocated to the first test machine where the first test script task includes the first unallocated test script. The first unallocated test script then may be identified as an allocated test script in the set of test scripts.

Abstract: A debugger includes: a plurality of processor cores; and a scheduler configured to control an allocation of a plurality of basic modules to the processor cores based on an execution rule for enabling parallel execution of a program that is divided into the basic modules that are executable asynchronously with one another, the program being defined with the execution rule of the basic modules for executing the basic modules in time series, wherein the scheduler includes a break point setting module configured to set a group of break points that are designated through a graphical user interface.

Abstract: When events are traced, the timing stream is used to associate events with instructions and indicate pipeline advances precluding the recording of stall cycles. Additional information is needed in the trace stream to identify an overlay whose execution of code is in a system where overlays or a memory management unit are used. In the case of PC trace, additional information is added when the memory system contents is changed. Information describing the configuration change is inserted into the export streams by placing this information in a message buffer. As long as a message word is available for output, it becomes the next export word as the output of message words is continuous.

Abstract: Conventionally, when executing a plurality of programs while being synchronized by a plurality of debuggers, an interface has been required for performing a particular coordination between the debuggers. In the present invention, programs are synchronously executed without coordination between the debuggers by performing a control method including a step for maintaining a program execution state in the debuggers to be different from an actual program execution state, so that the program execution is retained, if necessary, in response to a program execution request from a debugger.

Abstract: The present disclosure is directed toward a method for restoring a computer processor to a previous state. Described is a processor/memory architecture that may store successive instructions/data into a pushdown stack. As instructions are loaded and executed, the loading and executing of new instructions may be suspended. The instruction execution and memory stack then may be restored to a previous processor state in terms of instructions, processor memory state, register values, etc.

Abstract: There is provided a system and method for performing testing on a database system comprising a query optimizer, the query optimizer having an optimizer plan space comprising a plurality of query plans. An exemplary method comprises generating a plurality of queries programmatically according to a template query by varying at least one of an operation, a predicate or a parameter to produce a plurality of query plans. The exemplary method also comprises optimizing the plurality of queries using the query optimizer to collect the plurality of query plans and selecting a subset of queries from the plurality of queries using the query optimizer, the subset of queries comprising queries with distinct query plans that substantially cover the optimizer plan space. The exemplary method additionally comprises executing the subset of queries on the database system to identify an inefficiency of the database system.

Abstract: Described herein are systems and methods for managing testing functionalities. One such method includes receiving, from a test tool, data indicative of a user-created test script, being a data-bound test script in the present example. The data-bound test script is created for testing a target application, and is bound to a predetermined data set. This received data is then processed, thereby to define data indicative of an unbound test script. A user interface is provided for allowing a user to associate the unbound test script with one or more data sets selected from a repository of stored data sets. Responsive to a user command, data indicative of a new data-bound test scripts is defined based on the association of the unbound test script with the selected one or more data sets. This new defined data-bound test script is executable via the test tool. For example, instructions are provided to the test tool such that those scripts are executed for the testing of the target application.

Abstract: A method for setting a breakpoint includes the following: receiving an input specifying a location for insertion of a breakpoint in the executable program; determining a breakpoint address for insertion of the breakpoint in the executable program based on the specified location of the breakpoint; writing a breakpoint instruction into a second machine-accessible medium at the breakpoint address; and locking a line containing the breakpoint instruction into the second machine-accessible medium to prevent the breakpoint instruction from being overwritten.

Abstract: In one aspect of the invention, a method provides a calibrated critical-failure model for a printing process of a critical feature by virtue of a classification of an optical parameter space according to at least two print-criticality levels. Print failure of a respective critical feature is judged on the basis of a print-failure criterion for the critical feature. The respective print-criticality level is ascertained from test-print-simulation data at a sampling point of a process window for a given point in an optical-parameter space, and from a failure rule. An advantage achieved with the method is that it comprises ascertaining the predefined optical-parameter set from the test-print-simulation data at only one sampling point of the process window, which sampling point is identical for all test patterns. This saves processing time and processing complexity by reducing the number of ascertained optical-parameter sets and their processing in the subsequent scanning and classifying steps.

Abstract: Provided are a software reliability test method using selective fault activation, a test area restriction method, a workload generation method and a computing apparatus for testing software reliability using the same. The software reliability test method registers a test target module. The software reliability test method injects a fault into a fault injection target function when a caller of the fault injection target function is included in the registered module, in a case of calling the fault injection target function.

Abstract: The invention provides a method and system for persistent context-based behavior injection in a computing system, such as in a redundant storage system or another system having a layered or modular architecture. Behaviors that are injected can be specified to have triggering conditions, such that the behavior is not injected unless the conditions are true. Triggering conditions may include a selected ordering of conditions and a selected context for each behavior. In a system having a layered architecture, behavior injection might be used to evaluate correct responses in the face of cascaded errors in a specific context or thread, other errors that are related by context, concurrent errors, or multiple errors. Behavior injection uses non-volatile memory to preserve persistence of filter context information across possible system errors, for reporting of the results of behavior injection, and to preserve information across recovery from system errors. Multiple behavior injection threads are also provided.

Abstract: A method for the monitoring and modification of communications in a communications system and a related communications system with a number of intercommunicating first nodes in which the intercommunication comprises desired communications and may comprise undesired communications; in which the system also comprises a further node for monitoring and modifying the communications; in which the further node comprises means for modifying the undesired communications and/or introducing further communications to change the operation of the system.

Abstract: The present invention is a smart card device that can be debugged and software developed using at least one interrupt endpoint without adding an additional port. At least one memory stores a debug monitor program and instructions for completing smart card transactions. An interface is defined by a plurality of communication pipes and respective endpoints, including at least one interrupt endpoint. A microprocessor is operatively connected to the interface and memory and configures the interrupt endpoint as a debug port for debugging and software development using the debug monitor program.

Abstract: An apparatus for processing data includes diagnostic mechanisms for providing watch point and breakpoint functionality. Semaphores are associated with the watch points and are provided with hardware support within the diagnostic circuitry serving to monitor whether or not accesses to watch point data is being made in accordance with the permissions set up and noted in the semaphore data.

Abstract: An embodiment of a method of maintaining operation of a cluster of computing devices includes an initial step of detecting a suspended kernel process on a first of the computing devices. In addition to the step of detecting the suspended kernel process the method includes the step of issuing a first signal that causes a cluster management process to disregard the first of the computing devices when determining if there exists a quorum of the computing devices.

Abstract: A system and a method dynamically adjusts the quality of service guarantees for virtual servers based upon the resource demands experienced by the virtual servers. Virtual server resource denials are monitored to determine if a virtual server is overloaded based upon the resource denials. Virtual server resources are modified dynamically to respond to the changing resource requirements of each virtual server. Occasionally, a physical host housing a virtual server may not have additional resources to allocate to a virtual server requiring increased resources. In this instance, a virtual server hosted by the overloaded physical host is transferred to another physical host with sufficient resources.