Abstract: Methods and apparatuses for fault detection in a component associated with an application programming interface platform are provided. In an embodiment, the component is determined to have been invoked to process a transaction. A forward progress counter is monitored to determine whether the component is processing the transaction, wherein the forward progress counter increments at determined intervals when the component is processing the transaction. A test transaction is executed for the component when a determination is made that the forward progress counter has not incremented for a threshold fault period. A fault alarm indicator is generated based on the determination that the forward progress counter has not incremented for the threshold fault period.

Abstract: A system and method for debugging dynamically generated application code is provided. The system and method compare a received script chunk of the application to the contents of script tags of a source document, and if the script chunk does not match any of the contents of the script tags, it is identified as dynamically generated code. The identified dynamically generated code may then be stored in a separate file for further display and debugging.

Abstract: A system, method, and product are disclosed for testing multiple threads simultaneously. The threads share a real memory space. A first portion of the real memory space is designated as exclusive memory such that the first portion appears to be reserved for use by only one of the threads. The threads are simultaneously executed. The threads access the first portion during execution. Apparent exclusive use of the first portion of the real memory space is permitted by a first one of the threads. Simultaneously with permitting apparent exclusive use of the first portion by the first one of the threads, apparent exclusive use of the first portion of the real memory space is also permitted by a second one of the threads. The threads simultaneously appear to have exclusive use of the first portion and may simultaneously access the first portion.

Abstract: A debugger debugs processes that execute shared instructions so a breakpoint set for one process will not cause a breakpoint to occur in the other processes. A breakpoint is set by recording the original instruction at the desired location and writing a trap instruction to the shared instructions at that location. When a process encounters the breakpoint, the process passes control to the debugger for breakpoint processing if the breakpoint was set at that location for that process. If the trap was not set at that location for that process, the cacheline containing the trap is copied to a small scratchpad memory, and the virtual memory mappings are changed to translate the virtual address of the cacheline to the scratchpad. The original instruction is then written to replace the trap instruction in the scratchpad, so the process can execute the instructions in the scratchpad thereby avoiding the trap instruction.

Abstract: A processing apparatus includes: first and second register files, the latter holding a part of data in the former; an operation unit to operate on data in the second register file and to output data; an instruction unit to issue a write instruction to write, to both register files, the output data and an error detection code for it, and first and second occurrence instructions; a first control unit to issue a first generation instruction when receiving the write instruction and the first occurrence instructions; and a first generation unit to generate a first simulated fault data to output it to the first register file when receiving the first generation instruction, and to output the output data and the error detection code to the first register file in absence of the first generation instruction. Similar second control and generation units are also provided mutatis mutandis.

Abstract: The present invention features an operational system test method, comprising defining a fault model, inserting a test agent, hooking a test location, collecting test information, and removing the test agent. The invention also features an operational system test method, comprising defining a fault model, inserting a test agent, identifying a memory area according to a test location, hooking the identified memory area, collecting test information, and removing the test agent.

Abstract: Described are a circuit and a method of analyzing and correcting a fault occurring in operation of the circuit during a power gating sequence. The method includes executing a modification of the power gating sequence that includes maintaining operation of a trace capture buffer (TCB); recording, in the TCB, events occurring during the executing; and correcting the fault based on analysis of the events recorded in the TCB. The circuit includes a plurality of components including a TCB, and a switch configured to maintain power to the TCB in a first state and turn off power to the TCB in a second state.

Abstract: A test configuration resource manager and a method of managing test configuration resources in a network test system. A computer readable storage medium may store instructions that, when executed, cause a computing device to receive a user input identifying a portion of a first test configuration, store the identified portion of the first test configuration as a test configuration resource in a library of test configuration resources, receive a user input identifying a stored test configuration resource, retrieve the identified stored test configuration resource, and incorporate the retrieved test configuration resource into a second test configuration. The library of test configuration resources may include one or more of port resources, protocol resources, and traffic resources.

Abstract: There is disclosed a method and apparatus for editing test configurations. The method includes displaying a graphical representation of a test configuration to be tested by a test system on a user interface and receiving user input identifying network topology to be added to the test configuration, the network topology including a device group defined by a number of emulated traffic sources, a set of protocols and a number of ports. The method further includes updating the graphical representation of the test configuration to include the network topology; the graphical representation of the network topology including graphical representations of the test system, the emulated traffic sources, the set of protocols, and the number of ports connecting the emulated traffic sources to the test system.

Abstract: A method for handling communication link problems between a first communication means and a second communication means. Data signals, control signals and/or error information are transferred between the first communication means and the second communication means using the communication link. The method includes activating a static identification pattern in the first communication means representing an error information, and stopping a clock signal (Clk) inside the first communication means to freeze a present error condition, in response to a communication link problem being detected, and transferring the activated static identification pattern permanently and/or repeatedly to the second communication means using the communication link.

Abstract: An image processing apparatus includes a microprocessor unit which acquires information about the attribute of a print job from the received print job, determines which method is suitable as a printing method for the print job, performs a first printing method in which a print process is started before a raster image processing (RIP) process on all pages included in the print job is ended or a second printing method in which a print process is started after the RIP process on all pages included in the print job is ended, based on the attribute information, and decides the printing method determined as suitable for the print job as the printing method to be executed on the print job.

Abstract: A method and device for pass-by breakpoint setting and debugging. The pass-by breakpoint setting method comprises: receiving a breakpoint setting command; determining an instruction at a breakpoint in a source program code according to the breakpoint setting command; if one of the instruction at the breakpoint and an instruction prior to the instruction at the breakpoint is a relative jump instruction, setting an instruction duplicate, and setting the instruction at the breakpoint in the source program code as a first abnormal instruction.

Abstract: An instruction is assuredly transmitted. A test apparatus that tests a device under test, includes a test unit that tests a device under test by exchanging a signal with the device under test, a control apparatus that controls the test unit; and a relay apparatus that relays communication between the test unit and the control apparatus, where the control apparatus transmits an instruction to be given to the test unit a plurality of times to the test unit, and the test unit receives the instruction transmitted the plurality of times from the control apparatus, and executes the instruction once.

Abstract: In one embodiment, the invention comprises partial fault tolerant stream processing applications. One embodiment of a method for implementing partial fault tolerance in a stream processing application comprising a plurality of stream operators includes: defining a quality score function that expresses how well the application is performing quantitatively, injecting a fault into at least one of the plurality of operators, assessing an impact of the fault on the quality score function, and selecting at least one partial fault-tolerant technique for implementation in the application based on the quantitative metric-driven assessment.

Abstract: The disclosure discloses a method and a system for detecting an abnormality of a network processor. The method comprises the following steps: an abnormality detection operation code is added into an execution flow of each thread in a network processor, and the network processor sets a flag bit corresponding to a current thread in an abnormality protection flag data area in a shared memory to a first flag when executing the abnormality detection operation code in the current thread; and when a period of a timer is expire, a coprocessor detects all the flag bits in the abnormality protection flag data area in the shared memory, determines that a thread corresponding to a flag bit which is not the first flag is abnormal when detecting that not all the flag bits are the first flag, and sets all the flag bits to a second flag when detecting that all the flag bits are the first flag.

Abstract: According to exemplary embodiments, a computer implemented method for functional testing of a processor design includes accessing a test template from a library of test templates, wherein the test template is configured to test a first selected function of the processor and inputting the test template to an automated test generation tool executed by a computer. The method further includes generating an instruction sequence based on the test template by the automated test generation tool and injecting an event instruction to the instruction sequence during the generating of the instruction sequence by the automated test generation tool, the injecting of the event instruction preserving testing of the first selected function of the processor and the event instruction being configured to test a second selected function of the processor. The method includes verifying a function of the processor by analyzing responses of the processor to the instruction sequence.

Abstract: Detecting defects in deployed systems, in one aspect, identify one or more monitoring agents used in a computer program. Total execution metric of the computer program and execution metric associated with the one or more monitoring agents are measured and the measure execution metric is compared with a specified overhead criteria. The execution of the one or more monitoring agents is adjusted based on the comparing step while the computer program is executing to meet the specified overhead criteria.

Abstract: A program can be instrumented to test the program. The test instruments are classified, and concurrency constraints applied based on the classifications. A testing tool determines classifications of a plurality of test instruments in the instrumented program. The testing tool prevents concurrent instantiation of multiple of the plurality of test instruments in a first classification of the classifications. Multiple of the plurality of test instruments in a second classification of the classifications are concurrently instantiated.

Abstract: Techniques for analyzing software in which un-instrumented components can be discovered and conditionally instrumented during a runtime of the software. Initially, software such as an application can be configured with a baseline set of instrumented components such as methods. As the application runs, performance data gathered from the instrumentation may indicate that the performance of some methods is below expectations. To analyze this, any methods which are callable from a method at issue are discovered, such as by inspecting the byte code of loaded classes in a JAVA Virtual Machine (JVM). To limit and focus the diagnosis, the instrumentation which is added to the discovered components can be conditional, so that the instrumentation is executed only in a specified context. The context can involve, e.g., a specified sequence of components in which a discovered component is called, and/or transaction data in which a discovered component is called.

Abstract: A data processing apparatus is disclosed, said data processing apparatus comprising a plurality of devices, trace logic associated with at least one of said plurality of devices, and tagging logic associated with at least one of said plurality of devices, said tagging logic being operable to: select at least one item, said at least one item comprising an activity to be monitored; provide said at least one selected item with tag data identifying said at least one item as an item to be monitored; and said trace logic being operable to: detect tagged items processed by said at least one device; and output trace information relating to at least some of said detected tagged items.

Abstract: In one embodiment, the invention comprises partial fault tolerant stream processing applications. One embodiment of a method for implementing partial fault tolerance in a stream processing application comprising a plurality of stream operators includes: defining a quality score function that expresses how well the application is performing quantitatively, injecting a fault into at least one of the plurality of operators, assessing an impact of the fault on the quality score function, and selecting at least one partial fault-tolerant technique for implementation in the application based on the quantitative metric-driven assessment.

Abstract: Methods and systems are provided to estimate the time to implement a regression test. A productivity table may be defined and stored in a host computer system, where the productivity table indicates the time expected to perform a plurality of automation script types at a plurality of complexity levels. The host computer system may receive a list of test flows to be used in conducting a regression test and a selection of a complexity level for each of the listed test flows. Complexity levels may be defined by, and a complexity level for a test flow may be selected based upon a variety of system- and test-related criteria. The total implementation time may be determined based on the complexity levels assigned to test flows in the regression test, the type of scripts used, and the productivity table.

Abstract: A runtime system implemented in accordance with the present invention provides an application platform for parallel-processing computer systems. Such a runtime system enables users to leverage the computational power of parallel-processing computer systems to accelerate/optimize numeric and array-intensive computations in their application programs. This enables greatly increased performance of high-performance computing (HPC) applications.

Abstract: A debug method for computer system is disclosed. The method includes the following steps. Firstly, a first index is increased. Next, a first debug data to a jth debug data are received via a debug port of controller. Then, the first debug data to the jth debug data are sequentially stored to a first memory block of a storage unit of the controller according to the second index of controller. Afterwards, the (i+1)th debug data to the jth debug data are copied to the second memory block from the first memory block according to the increased first index before a controller's power supply is removed or the computer system enters a sleep state. Lastly, an application is implemented so that the second memory block is read according to the first index; wherein, i and j are integers.

Abstract: In order to protect a software program, at least one corruption function is included in the program. Also included in the program is at least one instruction that causes the program to be directed to the corruption function. An available breakpoint is then set such that, when the starting location of the corruption function is reached, an exception is generated and the handling of the exception causes the corruption function not to run. This has the effect that, if a malicious user attempts to use the available hardware breakpoint to perform unauthorized actions on the software program, the corruption function will run, and the software program will be unusable.

Abstract: A handheld electronic device testing system and a method for testing a handheld electronic device installed with an open operating platform and installed with a test instruction execution program are introduced. The test instruction execution program executes a functional test based on a test instruction received. The testing method involves integrating various test programs with a pre-stored test program library, sending sequentially an instruction to the test instruction execution program with each of the test programs through a transmission line in a scheduled manner, and recording a test result to achieve automated testing.

Abstract: Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. Stuffing instructions in a processing pipeline of a multi-threaded digital signal processor provides for operating a core processor process and a debugging process within a debugging mechanism. Writing a stuff instruction into a debugging process registry and a stuff command in a debugging process command register provides for identifying a predetermined thread of the multi-threaded digital signal processor in which to execute the stuff instruction. The instruction stuffing process issues a debugging process control resume command during a predetermined stage of executing on the predetermined thread and directs the core processor to perform the stuff instruction during the debugging process. The core processor may then execute the stuffed instruction in association with the core processor process and the debugging process.

Abstract: A method and system provide processing instructions in a multi-threaded process including the use of breakpoint instructions for generating debugging event(s). A debugging event is generated in response to the execution of breakpoint instructions and executes debugging instructions in response to the debugging event. The debugging instructions debug processing instructions in the multi-threaded processor by transitioning at least one or more threads into a debugging mode. A debugging return is generated for reporting the executing debugging instructions in the subset of the threads of the multi-threaded processor.

Abstract: A system, method, and product are disclosed for testing multiple threads simultaneously. The threads share a real memory space. A first portion of the real memory space is designated as exclusive memory such that the first portion appears to be reserved for use by only one of the threads. The threads are simultaneously executed. The threads access the first portion during execution. Apparent exclusive use of the first portion of the real memory space is permitted by a first one of the threads. Simultaneously with permitting apparent exclusive use of the first portion by the first one of the threads, apparent exclusive use of the first portion of the real memory space is also permitted by a second one of the threads. The threads simultaneously appear to have exclusive use of the first portion and may simultaneously access the first portion.

Abstract: An application builder system and methodology enables a user to create an application using a builder (“builder application”); interactively edit the builder application by adding and removing application objects; interactively edit the properties of the application objects, including a new property called “debug level”; interactively set values of parameters for a code generator, including the value of a new parameter called “debug level”; invoking the code generator to automatically generate application code; and running the resulting generated application.

Abstract: A system and method for testing a control module includes a microprocessor, where the microprocessor has a programming environment. The programming environment has a test data structure, a configuration data structure, and a monitor data structure each containing data. At least one test data instance is associated with the test data structure and at least one configuration data instance is associated with the configuration data structure. The configuration data instance is a diagnostic test that monitors a parameter of the microprocessor, and the monitor data structure creates the test data instance such that each test data instance corresponds to one of the configuration data instances. The program includes a first control logic for associating the test data structure, the configuration data structure and the monitor data structure as part of a core infrastructure portion of the programming environment, where the core infrastructure portion of the program is static.

Abstract: A method includes capturing data that is representative of actions performed by each of a plurality of human user operated clients as they interact with an online software application, loading at least one or more portions of the captured data into one or more automated simulation clients, and using the one or more automated simulation clients to perform load testing of an online server system. A system includes a data capturing stage, one or more automated simulation clients, and a configuration stage.

Abstract: A particular system includes a processor and a network interface configured to send and receive messages via a network using an asynchronous computer communication protocol. The system may include two or more buffers, such as an ingress buffer and an egress buffer. The system may include a memory accessible to the processor. The memory may include first node instructions that are executable by the processor to implement one or more functions of a first node. The memory may also include one or more script callbacks. The script callbacks may be executable by the processor to at least one of provide: the first content to a test script to be modified before the first content is provided to the first node instructions from the ingress buffer, and provide the second content to the test script to be modified before the outgoing message is provided to the egress buffer.

Abstract: One embodiment described herein is directed to a method practiced in a computing environment. The method includes acts for determining test suite effectiveness for testing for concurrency problems and/or product faults. The method includes identifying a plurality of synchronization primitives in a section of implementation source code. One or more of the synchronization primitives are iteratively modified and a same test suite is run for each iteration. For each iteration, a determination is made whether or not the test suite returns an error as a result of modifying one or more synchronization primitives. When the test suite does not return an error, the method includes providing to a user an indication which indicates at least one of a test adequacy hole for the test suite; an implementation source code fault; or an equivalent mutant of the implementation source code.

Abstract: A high-level integrated circuit (“IC”) modeling system (400) includes a first co-simulator (418) modeling a first portion of an IC system and a second co-simulator (419) modeling a second portion of the IC system, each co-simulator operating according to initial simulation operating conditions (426). A co-simulation synchronization interface (424) is configured to automatically change at least one of the initial simulation operating conditions to a triggered operating condition (428) in response to a user-selected triggering signal.

Abstract: The invention is directed to instrumenting object code of an application and/or an operating system on a target machine so that execution trace data can be generated, collected, and subsequently analyzed for various purposes, such as debugging and performance. Automatic instrumentation may be performed on an application's object code before, during or after linking. A target machine's operating system's object code can be manually or automatically instrumented. By identifying address space switches and thread switches in the operating system's object code, instrumented code can be inserted at locations that enable the execution trace data to be generated. The instrumentation of the operating system and application can enable visibility of total system behavior by enabling generation of trace information sufficient to reconstruct address space switches and context switches.

Abstract: A processor implementation supports selection of an execution mode for debug instruction instances based on respective addresses thereof in addressable memory can provide an attractive mechanism for executing debug instructions in a way that allows some instances of the instructions to operate with debug semantics while suppressing other instances by executing them with no-operation (NOP) semantics. In some embodiments, selection of operative execution semantics may be based on attributes of a memory page in which a particular debug instruction instance resides. In some embodiments, portions of an address space may be delimited (e.g., using values stored in bounding registers and addresses of particular debug instruction instances compared against the delimited portions to select appropriate execution semantics. In some embodiments, both types of evaluations may be used in selecting appropriate execution semantics for a particular debug instruction instance.

Abstract: Aspects relate to a cognitive agent that performs functions associated with a desired result. The functions performed by cognitive agent supplement other activities performed at a same time. In such a manner, the cognitive agent can function as a surrogate for a user. A performed activity can trigger implementation of another activity that is an extension of the performed activity. Cognitive agent can perform functions that can be represented as an avatar. Further, cognitive agent can be associated with a diagnostics component that evaluates an operating condition. Based on the operating condition cognitive agent can implement automatic actions associated with mitigating failures and/or prolonging the life of machinery.

Abstract: The claimed subject matter provides a method for detecting a data race. The method includes inserting a plurality of breakpoints into a corresponding plurality of program locations. Each of the program locations accesses a plurality of memory locations. Each of the program locations is selected randomly. The method also includes detecting one or more data races for the memory locations in response to one or more of the breakpoints firing. Additionally, the method includes generating a report describing the one or more data races.

Abstract: The present invention discloses a method to record trace data in a way that significantly reduces the time required to search for specific events, to create an index, to create a histogram, or to analyze the protocol. During capture, the analyzer recognizes infrequent events and sets an Event-Present Flag (“EP Flag”) indicating that a specific event has occurred. The trace is divided into pages, with a separate set of Event-Present Flags for each page indicating whether an event occurred in that page of the trace. This division of a trace into separate pages results in significant efficiencies.

Abstract: A method is provided for controlling ROM parameters embedded in a microprocessor software executable without modifications to the underlying source code. The method includes: presenting a software program having a plurality of machine instructions of a finite number of fixed lengths in an executable form; searching through the machine instructions of the executable and finding at least one appropriate instruction defined in a read only memory space to replace; defining a replacement instruction for identified machine instructions in the software program; and replacing identified machine instructions in the executable form of the software program with the replacement instruction. The replacement instruction may be further defined as a branch instruction that references an address outside an address space for the software program.

Abstract: Techniques are described for debugging a processing element (or elements) in a stream based database application in a manner that reduces the impact of debugging the processing element (or elements) on the overall running environment by selectively fusing (or un-fusing) processing elements running on a group of compute nodes. In addition to fusing and un-fusing processing elements or otherwise modifying a state of the stream application, a debugging application and stream manager may modify data flows within the application stream in a variety of ways to minimize any disruption resulting from a debugging session.

Abstract: A Design-Under-Test (DUT) may be designed to perform speculative execution of a branch path prior to determination whether the branch path is to be performed. Verification of the operation of DUT in respect to the speculative execution is disclosed. A template may be used to generate a plurality of tests. In addition to standard randomness of the tests to various parameters in accordance with the template, the tests may also differ in their respective speculative execution paths. The tests are partitioned by a generator into portions to be placed in speculative paths and portions to be placed in non-speculative paths. The generator may provide for a variance in portions. The generator may provide for nested speculative paths.

Abstract: A system, method, and product are disclosed for testing multiple threads simultaneously. The threads share a real memory space. A first portion of the real memory space is designated as exclusive memory such that the first portion appears to be reserved for use by only one of the threads. The threads are simultaneously executed. The threads access the first portion during execution. Apparent exclusive use of the first portion of the real memory space is permitted by a first one of the threads. Simultaneously with permitting apparent exclusive use of the first portion by the first one of the threads, apparent exclusive use of the first portion of the real memory space is also permitted by a second one of the threads. The threads simultaneously appear to have exclusive use of the first portion and may simultaneously access the first portion.

Abstract: A method is provided for isolating errors which occur when code supplied by independent software vendors (ISV code) interacts with code supplied by a primary vendor (host code). Code suspected of containing ISV code with host code is executed. If the results are in error, the code is scanned and then compared with a master host code. Any differences are stored in a delta file, including locations in the host code where ISV code hooks into the host code. The code is then modified to by-pass the hooks to ISV code to generate a side-executable code and both codes are executed and the results are compared. A lack of substantial difference in the results is indicative that the ISV code adversely affects the host code while a difference between the results is indicative of an error in the modified code.

Abstract: A fuzz testing system is described herein that represents event sources, channels, processors, and consumers as first-class entities in an application. Abstracting event-related entities allows fuzzing through injecting, dropping, reordering, and delaying events from within the application. This translates into the ability to localize the areas under test and perform fuzzing in a systematic manner. In some embodiments, the fuzz testing system tests concurrent asynchronous and event-based code, and can generate event streams based on a given statistical distribution. Representing events, event sources, processors, and sinks as first-class objects provides easy access to the event handlers and facilitates implementing fuzzing by introducing event processors between the source and the sink. Thus, the fuzz testing system improves the testability of applications and APIs with asynchronous behavior and provides a uniform framework for introducing fuzz testing into such applications.

Abstract: Installation files are annotated, which annotations may trigger system snapshots to be taken at a plurality of points during the execution of the installation files and/or collected. During a test run, the generated snapshots are examined incrementally to determine whether the installation is success or failure at that point. Checkpoint snapshots are stored, and those indicating failure are recorded with description of the error and/or remediation that suggest how the errors may be resolved or fixed. During a production run, the annotated installation files may be executed and the checkpoint snapshots generated during the production run may be compared with those stored of the test run to incrementally identify and resolve potential problems in the production run.

Abstract: Processing units are configured to capture the unit state in unit level error status registers when a runtime error event is detected in order to facilitate debugging of runtime errors. The reporting of warnings may be disabled or enabled to selectively monitor each processing unit. Warnings for each processing unit are propagated to an exception register in a front end monitoring unit. The warnings are then aggregated and propagated to an interrupt register in a front end monitoring unit in order to selectively generate an interrupt and facilitate debugging. A debugging application may be used to query the interrupt, exception, and unit level error status registers to determine the cause of the error. A default error handling behavior that overrides error conditions may be used in conjunction with the hardware warning protocol to allow the processing units to continue operating and facilitate in the debug of runtime errors.

Abstract: In a data processing system, a marked bit is used to identify a data access instruction throughout the pipeline to indicate that the instruction meets user-specified criteria (e.g., a meets a data address range of interest). Based on the marked bit, an in-order program correlation message is generated which indicates when the data access instruction occurs relative to the instruction stream. The marked bit is also used to generate an in-order data trace message. As a result, the trace streams including only data access instructions meeting user-specified criteria may be post-processed and correlated precisely.

Abstract: A system and a method dynamically adjusts the quality of service guarantees for virtual servers based upon the resource demands experienced by the virtual servers. Virtual server resource denials are monitored to determine if a virtual server is overloaded based upon the resource denials. Virtual server resources are modified dynamically to respond to the changing resource requirements of each virtual server. Occasionally, a physical host housing a virtual server may not have additional resources to allocate to a virtual server requiring increased resources. In this instance, a virtual server hosted by the overloaded physical host is transferred to another physical host with sufficient resources.