Abstract: Provided is a method for testing an apparatus including a first to third processors, a first circuit that connects the first and second processors, and a second circuit that connects the second and third processors. The method includes generating a test instruction sequence by prepending an additional instruction sequence to a certain instruction sequence which includes an instruction(s) for controlling the apparatus to execute a process using the first circuit. The additional instruction sequence does not change an operation result of an instruction included in the certain instruction sequence. The test instruction sequence includes an instruction(s) for controlling the apparatus to execute a process using the second circuit. The test method includes judging whether the first and second circuits are faulty, by controlling the apparatus to execute the test instruction sequence from a beginning of the certain instruction sequence, and from a beginning of the additional instruction sequence, respectively.

Abstract: An Availability Management Framework (AMF) configuration describes how configuration entities of a highly available system are grouped and includes information on service provision and service protection policies against resource failure. The AMF configuration defines a set of failure types for each component and each node, and specifies a failure rate and a recommended recovery for each failure type. A method for evaluating service availability receives the AMF configuration as input, and analyzes it to obtain an actual recovery that the highly available system is to perform when the given component fails. The method maps the AMF configuration to a stochastic model that captures the dependencies among the components and among the configuration entities at multiple levels of the hierarchy. The method utilizes the model to calculate the service availability of the AMF configuration based on the failure rate, the actual recovery and the dependencies.

Abstract: A method for determining correctness of a transformation between a first finite state automaton (FSA) and a second FSA, wherein the first FSA comprises a representation of a regular expression, and the second FSA comprises a transformation of the first FSA includes determining a third FSA, the third FSA comprising a cross product of the second FSA and a post-processor; determining whether the first FSA and the third FSA are equivalent; and in the event that the first FSA is determined not to be equivalent to the third FSA, determining that the transformation between the first FSA and the second FSA is not correct.

Abstract: Processing for file system volume error detection and processing for resultant error correction are separated to support system availability and user satisfaction. File system volumes for storing data structures are proactively scanned while the volumes remain online to search for errors or corruptions thereon. Found errors are scheduled to be corrected, i.e., spot corrected, dependent on the severity of the identified errors, error correction scheduling and/or at the determination of a file system administrator and/or user, to assist in maintaining minimal user and file system impact. When spot correction is initialized, one file system volume at a time is taken offline for correction. Spot correction verifies prior logged corruptions for the offline volume, and if independently verified, attempts to correct the prior noted corruptions. Volumes are retained offline only for the time necessary to verify and attempt to correct prior noted volume corruptions.

Abstract: Logic circuits provide networks to simulate the functions of neural networks of the brain, and can discriminate degrees of state, and combinations of degrees of state, corresponding to a number of neurons. Logic circuits comprise Recursive AND NOT Conjunctions (RANCs), or AND NOT gates. A RANC is a general logic circuit that performs conjunctions for 2n possible combinations of truth values of n propositions. The RANCs function dynamically, with capabilities of excitation and inhibition. Networks of RANCs are capable of subserving a variety of brain functions, including creative and analytical thought processes. A complete n-RANC produces all conjunctions corresponding to the 2n possible combinations of truth values of n propositions.

Abstract: An automation process verifies that a test bed includes a set of devices specified by at least one script which are to be executed by the automation process on the test bed. The test bed is locked and the set of devices is allocated to the automation process. Performance data collection and logging for the set of devices is started and the at least one script is executed on the set of devices. After executing the at least one script, the set of devices is de-allocated and the test bed is unlocked. A notification is generated indicating that the at least one script has been executed.

Abstract: A method, apparatus and software is disclosed, for use in a computerised storage system comprising one or more replaceable units, for managing testing of one or more replacement units, where the storage system is automatically placed in a testing mode in response to a given unit being replaced and if testing fails the storage system automatically fails back to a service mode.

Abstract: Data structure errors, or corruptions, identified during, e.g., normal computing device system processing, file system processing or user access processing, are verified prior to the file system identifying the error for offline correction or notifying the user or system administrator a data structure error exists. Identified data structure corruptions are verified while the file system volumes are maintained online and otherwise accessible to other processing tasks and user access. Verified data structure corruptions are logged for further corrective processing. Data structure corruptions that cannot be verified, i.e., false positives, are not further processed and are not identified to file system administrators or users as corruptions, freeing the file system to concentrate on normal processing and true, verifiable errors.

Abstract: Method, apparatus and computer program product are configured to perform computer monitoring activities; to collect information regarding computer system status during the computer monitoring activities; to detect a problem in dependence on the information collected during the computer monitoring activities; and to determine whether to launch a diagnostic probe when the problem is detected. The monitoring activities may be performed on a periodic or event-driven basis. The determination whether to launch a diagnostic probe is based on a rule included in a hierarchy of rules. The hierarchy of rules is based on problem tickets; system logs; and computer system configuration information.

Abstract: A method of testing components of a computing device by obtaining a serial number of the computing device, and searching a database for test results of the computing device by using the serial number. The method determines whether the computing device has passed an electronic circuitry test when the electronic circuitry test result of the computing device has been found in the database, and tests components of the computing device when the computing device has passed the electronic circuitry test. A component test result of the computing device is saved in the database, and displayed on the display.

Abstract: Input messages are received at respective ports (10, 11, 12) of a message controller 4 from a plurality of external devices (100, 110, 120) which use different protocols. When an incoming message arrives at an input port a message object is created, the message object including a label identifying the respective input port. The conversion and subsequent handling of the messages uses program data which is retrieved from a program data store (5) according to the label indicating the input port. The program data retrieved is thus specified by the input port and allows conversion of messages into a common protocol to allow subsequent processing of the messages. This architecture allows the same program data to be called for external devices using the same protocol. Other processes may also be called from the program data store, covering functions such as validation, data enrichment, and exception handling processes.

Abstract: Systems and methods for recovering from a fault in an array of data storage devices are provided. Fault recovery includes determining that a first data storage device of the array of data storage devices is more likely to fail that other storage devices of the array of data storage devices. A second data storage device in the array of data storage devices is selected to be used in recovering from a failure of the first data storage device. Data from the first data storage device is stored at the second storage device. In the event of a failure at the first data storage device, data storage operations are performed using the second storage device.

Abstract: In one aspect, a method of testing a device for use in a storage area network (SAN) system includes receiving recorded messages including messages from a host and from a storage array and messages to a host and to a storage array, sending the recorded messages from the host and the storage array to a device under test, receiving messages from the device under test in response to the recorded messages sent and determining whether the device under test functions identically to a validated device based on the messages from the device under test being substantially identical to the recorded messages.

Abstract: Systems and methods for detecting faults in a system. The method comprising maintaining diagnostic history for one or more system components; receiving system information about operational state and relational interaction among system components; determining if one or more system components are to be examined, in response to performing an analysis of the diagnostic history, wherein the analysis is performed to determine if the diagnostic history includes any information that may indicate that certain system components or combinations of components are suspected of causing a problem detected in the system, wherein the diagnostic history is maintained based on an at least one examination performed on said one or more components when said one or more components were installed in a system other than the system in which the problem is detected.

Abstract: A runtime system implemented in accordance with the present invention provides an application platform for parallel-processing computer systems. Such a runtime system enables users to leverage the computational power of parallel-processing computer systems to accelerate/optimize numeric and array-intensive computations in their application programs. This enables greatly increased performance of high-performance computing (HPC) applications.

Abstract: Method, apparatus and computer program product for correlating performance events in a data processing system. A first event is received at one of a first device and a second device of the data processing system, and a second event is received at one of the first device and the second device. A type of a connection between the first device and the second device is identified to form an identified type of connection, and a relationship between the first event and the second event is determined based on the identified type of connection between the first device and the second device.

Abstract: Various exemplary embodiments relate to a method and related network node including one or more of the following: determining that a diagnostic test should be performed on a hardware component of a plurality of hardware components, wherein the plurality of hardware components support a plurality of agent devices and at least one agent device of the plurality of agent devices is assigned to at least one of the plurality of hardware components; ensuring that no agent device of the plurality of agent devices is assigned to the hardware component; and after ensuring that no agent device of the plurality of agent devices is assigned to the hardware component, performing the diagnostic test on the hardware component, wherein at least one other hardware component of the plurality of hardware components continues operation during performance of the diagnostic test.

Abstract: An electronic card (4) comprising a processing unit (7), able to receive a command originating from a diagnostic module (6) and a command originating from a simulation system (3). The electronic card (4) comprises means of managing the execution priority of the command originating from the simulation system (3) relative to the command originating from the diagnostic module (6). A diagnostic system of an electronic card comprising a diagnostic module and means of managing the execution priority of the commands. A simulation method is associated with the electronic card (4). For use in particular for analysing malfunctions on electronic cards (4) incorporated in integration simulators (1).

Abstract: A system and method for improving the yield rate of a multiprocessor semiconductor chip that includes primary processor cores and one or more redundant processor cores. A first tester conducts a first test on one or more processor cores, and encodes results of the first test in an on-chip non-volatile memory. A second tester conducts a second test on the processor cores, and encodes results of the second test in an external non-volatile storage device. An override bit of a multiplexer is set if a processor core fails the second test. In response to the override bit, the multiplexer selects a physical-to-logical mapping of processor IDs according to one of: the encoded results in the memory device or the encoded results in the external storage device. On-chip logic configures the processor cores according to the selected physical-to-logical mapping.

Abstract: A system, method, and product are disclosed for testing multiple threads simultaneously. The threads share a real memory space. A first portion of the real memory space is designated as exclusive memory such that the first portion appears to be reserved for use by only one of the threads. The threads are simultaneously executed. The threads access the first portion during execution. Apparent exclusive use of the first portion of the real memory space is permitted by a first one of the threads. Simultaneously with permitting apparent exclusive use of the first portion by the first one of the threads, apparent exclusive use of the first portion of the real memory space is also permitted by a second one of the threads. The threads simultaneously appear to have exclusive use of the first portion and may simultaneously access the first portion.

Abstract: A method for determining correctness of a transformation between a first finite state automaton (FSA) and a second FSA, wherein the first FSA comprises a representation of a regular expression, and the second FSA comprises a transformation of the first FSA includes determining a third FSA, the third FSA comprising a cross product of the second FSA and a post-processor; determining whether the first FSA and the third FSA are equivalent; and in the event that the first FSA is determined not to be equivalent to the third FSA, determining that the transformation between the first FSA and the second FSA is not correct.

Abstract: Some embodiments of the present invention provide a system that analyzes data from a computer system. During operation, the system obtains the sensor data from a component in the computer system using a set of sensors. Next, the system transmits the sensor data to a microcontroller unit (MCU) coupled to the sensors and stores the sensor data in internal memory of the MCU. Finally, the system assesses the integrity of the component by analyzing the sensor data using a pattern-recognition apparatus in the MCU.

Abstract: A method for use in a computerized storage system comprising one or more replaceable units, for managing testing of one or more replacement units, where the storage system is automatically placed in a testing mode in response to a given unit being replaced and if testing fails the storage system automatically fails back to a service mode.

Abstract: This invention is a method of operating a system having multiple finite state machines and a controller controlling an operational state of each finite state machine. Upon selection by the controller of a changed operational state, each finite state machine determines if it supports the changed operational state. If the finite state machine supports the changed operational state, it enters the changed operational state. If the finite state machine does not support the changed operational state, it enters an offline state. The controller may also determine whether a changed operational state is supported by each finite state machine.

Abstract: A method for error control in an overall system having multiple installations, the installations communicating with one another via a data transmission system having a predefined transmission bandwidth, at least one installation component of each installation transmitting a predefined piece of information in a defined time slot of the transmission bandwidth of the data transmission system.

Abstract: A system, method, and product are disclosed for testing multiple threads simultaneously. The threads share a real memory space. A first portion of the real memory space is designated as exclusive memory such that the first portion appears to be reserved for use by only one of the threads. The threads are simultaneously executed. The threads access the first portion during execution. Apparent exclusive use of the first portion of the real memory space is permitted by a first one of the threads. Simultaneously with permitting apparent exclusive use of the first portion by the first one of the threads, apparent exclusive use of the first portion of the real memory space is also permitted by a second one of the threads. The threads simultaneously appear to have exclusive use of the first portion and may simultaneously access the first portion.

Abstract: One preferred embodiment of the present invention provides a system and method for evaluating the performance of a network interface sub-system of an inter-messaging network of voice mail systems. This preferred embodiment includes a network query device that connects to the inter-messaging network and requests a test data file to be retrieved from a particular voice mail network interface sub-system in the inter-messaging network. The requests for the test data file are generated according to user command. Accordingly, the performance of a network interface sub-system in the inter-messaging network, as represented by the result of the request attempt, is evaluated according to a defined level of performance, such as a preferred time limit. Other systems and methods are also provided.

Abstract: A control device includes: memory diagnosis means for setting a power-on status when an electric power is turned on and diagnosing an ECC memory; restarting means for restarting the control device when the memory diagnosis means detects a correctable error of the ECC memory during the power-on status of the ECC memory; and operation processing means for resetting the power-on status and performing a normal operation when the memory diagnosis means does not detect a correctable error of the ECC memory, while performing the normal operation when a correctable error of the ECC memory is detected because of the restart of the control device by soft reset after the reset of the power-on status but when the control device is not in the power-on status.

Abstract: Methods and systems for detecting one or more anomalous devices are disclosed. For each of a plurality of devices, semi-structured data may be received from the device. For each pair of devices, of the plurality of devices, a similarity measurement may be determined between semi-structured data from a first device of the pair of devices and semi-structured data from a second device of the pair of devices. One or more anomalous devices may then be identified and one or more remedial actions may be performed for the one or more identified anomalous devices.

Abstract: A smart card comprises a storage unit in which various data are stored, a communication unit to perform data communication with an external apparatus, and a processing unit which executes processing corresponding to a command received via the communication unit. The processing unit of the smart card detects data judged to have data abnormality from the data stored in the storage unit in a case where the command received from the external apparatus is an abnormal data confirmation command, and notifies the external apparatus of response data including information indicating the data in which the data abnormality has been detected by the detection.

Abstract: A communications architecture utilizes modules arranged in a daisy-chain, each module supporting multiple input and output ports. Point-to-point links are arranged so that a first output link of each of multiple modules connects to the next module in the chain, and a second output link connects to a module after it, and inputs arranged similarly, so that any single module can be by-passed in the event of malfunction. Multiple chains may be cross-linked and/or serviced by hubs or chains of hubs. Preferably, the redundant links are used in a non-degraded operating mode to provide higher bandwidth and/or reduced latency of communication. The exemplary embodiment is a memory subsystem in which the modules are buffered memory chips.

Abstract: A logical central processing unit (logical CPU) selects a target device. When the target device is shared by another logical CPU, the logical CPU determines whether the logical CPU is in charge of exclusively making diagnosis of the target device. When the target device is not shared by another logical central processing unit or when the logical CPU is exclusively in charge of making diagnosis of the target device, the logical CPU makes diagnosis of the target device and stores a result of diagnosis in a storage unit.

Abstract: A multiprocessor system is disclosed. The multiprocessor system includes plural processor cores to which control to be performed is allocated. The multiprocessor system includes a monitoring processor which detects an abnormal operation that has occurred in a specific processor core to which control having a higher priority order than control to be allocated to processor cores other than the specific processor core is allocated. When the monitoring processor detects the abnormal operation in the specific processor core, the monitoring processor allocates the control having the higher priority order to one of the processor cores other than the specific processor core.

Abstract: This invention is to provide a technology for taking out trace information externally without lacking under the condition of limited output bandwidth. A semiconductor integrated circuit provided includes: a processing unit which can perform arithmetic processing according to a predetermined program and can output trace information with respect to the arithmetic processing; and a trace compression unit which can compress the trace information outputted from the processing unit. The trace compression unit includes a storage device, a comparator unit which can compare trace information stored in the storage device and the trace information newly outputted from the processing unit, and a trace information compression controller which can compress trace information to be externally outputted, based on the comparison result of the comparator unit.

Abstract: An image management system includes a first storage device configured to store a list of image identifiers indexed by one or more image property descriptors, wherein each of the image identifiers corresponds to a digital image, an index processor in communication with the first storage device, configured to write the image identifiers and the associated image property descriptors for each image identifier in the image index storage, and a search processor in communication with the first storage device, configured to receive a specified image property descriptor and to identify one or more image identifiers that match the specified image property descriptor.

Abstract: A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device determines whether to initialize to a standard protocol or to an advanced protocol. Upon determining to initialize to the advanced protocol, the second remote device then waits for a synchronization point sequence.

Abstract: A runtime system implemented in accordance with the present invention provides an application platform for parallel-processing computer systems. Such a runtime system enables users to leverage the computational power of parallel-processing computer systems to accelerate/optimize numeric and array-intensive computations in their application programs. This enables greatly increased performance of high-performance computing (HPC) applications.

Abstract: A method for automatically diagnosing malfunction in device is provided. The method includes: acquiring a sort identification code from a hardware code of the malfunctioning device connected to the diagnostic apparatus; determining the access address of the diagnostic program on the server according to the determined sort identification code in a diagnostic program access address table; accessing the diagnostic program from the server according to the determined access address of the diagnostic program; applying the diagnostic program to the malfunctioning device to generate a diagnosis; and generating a diagnostic report of the generated diagnosis.

Abstract: A test system for testing various functions of electronic devices includes a master device and a simulation control device. The master device is connected to an input device and the electronic devices through the simulation control device. The master device records input signals of the input device and generate simulation signals according to the input signals. The simulation control device simulates the input signals of the input device according to the simulation signals to test the electronic devices.

Abstract: A network guidelines estimator (NGE) estimates a network load for each software application operating in a test network to determine network load metrics for each software application. A network load estimator (NLE) estimates a network load for one or more software applications concurrently operating in a production network responsive to the network load metrics of each of the one or more software applications. A network load analyzer (NLA) analyzes the network load for the one or more software applications concurrently operating in the production network to determine an actual network load for the production network.

Abstract: A system can test network performance of an electronic device via transmitting a testing file with a first designated name to a number of computers connected to the electronic device, obtaining comparison files from the number of computers after running the testing file, and replacing the names of the comparison files with standard names. The network performance of the electronic device can be confirmed via contents of the comparison files.

Abstract: According to the method for configuring an information system (1), components (2) are provided for the information system (1) and component-specific error susceptibility data (3) on the individual components (2). For a given system configuration (5), error susceptibility information (7) is determined for the information system (1) in this given system configuration (5) as a function of the component-specific error susceptibility data (3). The error susceptibility information (7) is evaluated with reference to given evaluation criteria (8). In a subsequent step, the information system (1) is configured in the given system configuration (5) if the error susceptibility information (7) satisfies the given evaluation criteria (8). By means of the method, it is achieved that only system configurations are accepted that satisfy requirements specified by the evaluation criteria (8) with respect to the reliability of the information system (1).

Abstract: An apparatus for selecting a candidate for a failure component causing errors from a plurality of components included in a network system, the apparatus includes a processor for executing a procedure. The procedure includes determining a relation class of a relation among the plurality of components on the basis of configuration information of the network system, each of the relations being classified into one of the relation classes in accordance with a direction of an error propagation, determining an investigation range for each component having an error on the basis of investigation information including an error type of an error occurred in the each component and an investigation direction corresponding to the relation class, the investigation range being a set of the components to be investigated, and selecting a component on the basis of an appearance frequency of each component in the investigation ranges as the candidate.

Abstract: A test method for a data processing device includes determining both a current state of the device and a desired state of the device. A set of instructions to transition the data processing device from the current state to the target state is obtained by initially selecting a first source state from a set of possible source states and corresponding instructions that can transition the device to the desired state. The instruction associated with the first source state is placed on an instruction stack. The source state and instruction selection process is repeated until the selected source state corresponds to the current state of the device under test. The instructions in the stack are applied to the device under test, and the resulting device state compared to the specified state to determine a test result.

Abstract: A technique of performing a workflow on a plurality of task servers involves starting a plurality of task server processes on the plurality of task servers. Each task server provides an operating system which is constructed and arranged to locally run a respective task server process. The technique further involves receiving a workflow which includes a set of dependency-related predefined activities, and placing task identifiers in a queue structure based on the received workflow. The task identifiers identify tasks to be performed in a distributed manner by the plurality of task server processes started on the plurality of task servers. Each task is a specific execution of a dependency-related predefined activity of the workflow. Progress in performing the workflow is made as the plurality of task server processes (i) claim task identifiers from the queue structure and (ii) perform the tasks identified by the claimed task identifiers.

Abstract: An integrated bus controller and power supply device includes a typical or standard bus controller and a bus power supply disposed in a common housing, the size and external configuration of which may match a standard bus controller device associated with a typical I/O communication network. The bus controller may store and implement one or more control routines using one or more field devices connected to the I/O communication network while the bus power supply generates and provides the appropriate power signal to the bus of the I/O communication network, the power signal being used to power the field devices connected to the I/O communication network.

Abstract: A method, apparatus, and computer instructions for processing trace data in a logical partitioned data processing system. A partition causing an exception is identified in response to detecting the exception. The partition is one within a set of partitions in the logical partitioned data processing system. The trace data for the identified partition is stored in an error log or other data structure for a machine check interrupt handler.

Abstract: A disclosed example method involves at a network management module, receiving a request for logical circuit data associated with a network circuit. In addition, the example method involves requesting the logical circuit data from a legacy logical element in communication with a network device of the network circuit. The logical circuit data is received from the legacy logical element. The logical circuit data is indicative of whether the network circuit has failed.

Abstract: A mechanism for isolating failures in a digital system is provided. In one embodiment, a fault table is defined for each unit in the system. Related faults are ordered within the table to reflect the time-order in which the faults would be activated during operation of the associated unit. When multiple related faults are reported for a given unit in the system, the fault that is first located when a linear search of the corresponding fault table is conducted is considered the source of the failure within the unit. If faults are reported for multiple units, the source of the failure for the system is identified using at least one of primary and second priority values assigned to the faults, timestamps obtained when the faults are reported, and an order in which the faults are logged.

Abstract: An electronic device is provided which comprises a microprocessor for executing a program code and a first hardware code path verifying (CPV) stage coupled to the microprocessor. The hardware CPV stage comprises a first error detection code (EDC) generator configured to continuously determine an error detection code on a continuous sequence of code relating to an actually executed portion of the program code and to compare the actual error detection code with a predetermined error code so as to verify correct execution of the program code and to indicate an error.