Abstract: Described herein are systems and methods for fast boot from non-volatile (“NV”) memory. The exemplary embodiments relate to systems and methods for significant improvements in performance speed with simple implementations. One embodiment relates to a non-transitory computer readable storage medium including a set of instructions executable by a processor, the set of instructions operable to identify a page fault, determine whether the page fault occurred due to a read from a NV memory, copy a page from the NV memory to a random-access memory (“RAM”) storage, and create an identity mapping for the page in the RAM storage.

Abstract: A remote data memory access method for use in a computer system having a plurality of nodes, each node using a respective memory and remote data memory access between nodes being performed by transferring user data from the memory used by one node to the memory used by another node, the method comprising: maintaining memory correctness information of the user data at a subunit level; selecting subunits of user data for transfer in dependence upon memory correctness information of each subunit; and selectively transferring the subunits so selected. The method preferably involves transferring the memory correctness information of at least the selected subunits of user data, in addition to the selected subunits of user data. The memory correctness information may be compressed prior to transfer.

Abstract: Various techniques are described for improving the performance of a shared-nothing database system in which at least two of the nodes that are running the shared-nothing database system have shared access to a disk. Specifically, techniques are provided for recovering the data owned by a failed node using multiple recovery nodes operating in parallel. The data owned by a failed node is reassigned to recovery nodes that have access to the shared disk on which the data resides. The recovery logs of the failed node are read by the recovery nodes, or by a coordinator process that distributes the recovery tasks to the recovery nodes.

Abstract: A storage management device includes a management unit for managing a storage device assigned thereto and a temporary storage unit assigned thereto. The management unit comprises a backup unit for, when data is written into the storage device, storing the data in the previously assigned temporary storage unit before the writing of the data into the storage device is completed, and a take-over unit for, when data which is already stored in the temporary storage unit, but which is not yet written into the storage device exists when the storage device and the temporary storage unit are assigned, writing the not-yet-written data into the storage device.

Abstract: In a method for managing test results of an electronic device, the electronic device includes one or more expansion slots. The method selects a hard disk drive to insert into each expansion slot, executes a read-write test on each expansion slot, and saves test result(s) of the tests on each expansion slot into a file. Before managing the test results, the method sets a file name for each expansion slot for which test results is to be managed, and selects a test item from the read-write test. The method determines test results which expansion slots with are required to be managed and determines a test order of the expansion slots. After the test results are imported, the method amends a file name corresponding to each expansion slot according to the test order, and manages the test results of each expansion slot.

Abstract: Described are embodiments of an invention for blocking write access to memory modules of a solid state drive. The solid state drive includes a controller access module or a memory access module that controls write access to the solid state drive and the memory modules of the solid state drive. Upon determining that a memory module has failed, the failed memory module or the entire solid state memory device is configured to be read only to prevent an errant write of data over critical data. Further, a failed memory module, or solid state device memory having a failed memory module, may be replaced upon failure.

Abstract: An application can specify reliability values via a communication path between the application and the registers. Application reliability could increase if the application itself could specify the timeout and retry values. For instance, some errors might be prevented if the timeout value is lengthened by a short amount. A longer timeout value would result in slower performance because the memory component could not be accessed during the timeout period. However, resolving errors in memory devices would prevent unrecoverable error indicators from being returned to the application, which would in turn limit application and system crashes.

Abstract: Methods and apparatus automatically identify certain types of data storage system problems, such as a flawed storage device or an incompatibility between a data storage system and a data storage device or an incompatibility between the storage system and a user computer. The existence of such a problem may be highlighted to a user through an indicator on the storage system and/or through a “dashboard” application being executed by the user computer, and the problem may be automatically corrected by automatically downloading a fix (e.g., new firmware or a “patch”) from a server (e.g., a server managed by the storage device manufacturer, a server managed by the storage system manufacturer and/or a server managed by a third party) and automatically implementing the fix.

Abstract: In a storage system, a first loop and a second loop are connected to a controller, and at least one of the first loop and the second loop is connected to existing storage devices (which are physical storage devices other than additional storage devices, which are physical storage devices which are additionally provided). In processing for additional provision, after having disconnected all of the existing storage devices from the first loop, the controller connects an additional storage device to the first loop. And the controller acquires, via said first loop, an address acquired by this additional storage device, and makes a first suitability decision as to whether or not this address is appropriate. And, if the result of this first suitability decision is negative, then the controller blocks up this additional storage device whose address has been acquired.

Abstract: Provided is a storage system, including: one or more disk drives storing data; a disk controller for controlling data access to the disk drive; a power supply controller for autonomously turning off a power source of the disk drive according to the data access status to the disk drive, and autonomously turning on the power source of the disk drive, which was turned off, after the lapse of a prescribed period from the time the power source was turned off irrespective of the data access status to the disk drive; and a media inspection unit for inspecting a failure in the disk drive in which the power source thereof was autonomously turned on irrespective of the data access status to the disk drive.

Abstract: A method, system and computer program product for generating device fingerprints and authenticating devices uses initial states of internal storage cells after each of a number multiple power cycles for each of a number of device temperatures to generate a device fingerprint. The device fingerprint may include pairs of expected values for each of the internal storage cells and a corresponding probability that the storage cell will assume the expected value. Storage cells that have expected values varying over the multiple temperatures may be excluded from the fingerprint. A device is authenticated by a similarity algorithm that uses a match of the expected values from a known fingerprint with power-up values from an unknown device, weighting the comparisons by the probability for each cell to compute a similarity measure.

Abstract: An interleave control which accesses a plurality of memory elements. A logical address is converted into a real address composed of a memory element selection address and a memory element address. The logical address of a CPU that has a logical address space divided into N area is converted into the real address decided in a way number W, and the memory elements are accessed by the interleave control. A real address area utilization information is prepared that is common to all the way numbers by dividing the real address space formed of a plurality of memory elements into areas (N×Wmax) based upon multiplying the area number N of the logical address space and the maximum way number Wmax, and utilization prohibition information is recorded in the area including the abnormal portion of the real address area utilization information when the abnormality of the memory element is detected.

Abstract: As a semiconductor storage device that can efficiently perform a refresh operation, provided is a semiconductor storage device comprising a non-volatile semiconductor memory storing data in blocks, the block being a unit of data erasing, and a controlling unit monitoring an error count of data stored in a monitored block selected from the blocks and refreshing data in the monitored block in which the error count is equal to or larger than a threshold value.

Abstract: A method for testing hard disks under an extensible firmware interface (EFI) provides a device tree of hard disks. Nodes of the device tree represent block devices or file systems of the hard disks. Devices paths and handles corresponding to each of the device paths are obtained from the device tree. Parent controller handles of each of the device paths are obtained. If there are parent controller handles the same as the obtained handles, the parent controller handles the same as the obtained handles are deleted. The computer determines that a number of the hard disks is equal to a number of the device paths corresponding to the remained parent controller handles. Nodes information of each of the device paths corresponding to the remained parent controller handles are determined as hard disk information of each of the hard disks.

Abstract: A random permutation code is described which provides efficient repair of data nodes. A specific implementation of a permutation code is also described, followed by description of a MISER-Permutation code. Finally, an optimal repair strategy is explained that involves an iterative process of downloading the most effective available parity data, updating costs of remaining parity data, and repeating until the data is recovered.

Abstract: To make available a backup copy of source data in a multi-site storage system, the source data is provided at a first storage site and an operational copy of the source data is provided at a second storage site. In response to a request to create a backup copy of the source data, the backup copy of the source data is produced at each of the first and second storage sites. In response to failure that causes the first storage site to be unavailable, recovery of a version of the source data is enabled based on accessing the backup copy of the source data at the second storage site, and accessing the operational copy of the source data at the second storage site.

Abstract: A system and method test serial attached SCSI (SAS) hard disk drives (HDDs) of a computing device. The computing device includes a SAS backpanel, and the SAS backpanel includes one or more connectors that are respectively connected to the SAS HDDs. An identification (ID) of each of the connectors and an SCSI address of each of the SAS HDDs are obtained. A predefined file is created, and the obtained ID of each connector and the SCSI address of each SAS HDD are recorded into the predefined file. An SCSI address of a SAS HDD to be tested is obtained from the predefined file, and functions of the SAS HDD are tested. An ID of the connector connected to the SAS HDD is obtained from the predefined file, and is displayed on a display device if one or more of the functions are abnormal.

Abstract: The embodiments described herein generally relate to methods and systems for using an extended patching procedure for correction or repair of logical data portions, pages, or sectors of a computer data storage device. The extended patching procedure targets for repair not only the page(s) appearing to be defective or unusable based on a failed read operation for a data transfer request, but also additional pages. Determining the additional pages to include for automatic patching is based on: statistical distribution analyses to include pages within the physical or logical vicinity of the original page, information about the underlying storage device technology or Input/Output (I/O) subsystem, and/or historical data about error conditions for areas related to the original page. Preemptively patching pages based on extended page lists improves system performance by reducing the total number of costly repair processes and by avoiding situations involving correction actions that fail to resolve.

Abstract: A method and system of migratory hardware diagnostic testing is disclosed. In one embodiment, a method includes performing a diagnostic test of a hardware component of a first partition of a server using a first test module embedded in the first partition in response to a receipt of a test command, and storing context data associated with the diagnostic test of the hardware component in a memory associated with the hardware component, where the context data indicates a current state of the diagnostic test of the hardware component. Further, the method includes analyzing the context data upon a receipt of an instruction for a migration of the hardware component to a second partition of the server, and continuing the diagnostic test of the hardware component using a second test module embedded in the second partition based on the context data if the migration is performed.

Abstract: A memory module includes an electronic printed circuit board with at least one contact strip, a plurality of integrated memory components, at least one first and one second buffer component, and a number of conductor tracks, which proceed from the contact strip and which are arranged on or in the printed circuit board. The conductor tracks include data lines, control lines and address lines. The conductor tracks lead from the contact strip to the buffer components or to one of the buffer components. The printed circuit board has conductor tracks that are interposed between the first buffer component and the second buffer component and that lead from the first buffer component to the second buffer component.

Abstract: A redundant and fault tolerant solid state disk (SSD) includes a determination module configured to identify a first solid state disk controller (SSDC) configured to connect to a flash array and a second SSDC configured to connect to the flash array. A capture module is configured to capture a copy of an I/O request received by the first SSDC from a port of a dual port connector, and/or capture a copy of an I/O request received by the second SSDC from a port of the dual port connector, and identify a write I/O request from the I/O request. A detection module is configured to detect a failure in the first SSDC. A management module is configured to manage access to a flash array by the first SSDC and the second SSDC. An error recovery and failover module is configured to automatically reassign work from the first SSDC to the second SSDC.

Abstract: Embodiments are described for managing memory faults. An example system can include a memory controller module to manage memory cells and report memory faults. An error buffer module can store memory fault information received from the memory controller. A notification module can be in communication with the error buffer module. The notification module may generate a notification of a memory fault in a memory access operation. A system software module can provide services and manage executing programs on a processor. In addition, the system software module can receive the notifications of the memory fault for the memory access operation. A notification handler may be activated by an interrupt when the notification of the memory fault in the memory access operation is received.

Abstract: Testing system capable of detecting different kinds of memory faults of a memory under I/O compression includes a data pattern selection circuit, writing pattern selection units, reading pattern selection units, and a data comparison circuit. The data pattern selection circuit converts a testing data into different data patterns by the writing pattern selection units and accordingly writes to the corresponding memory data ends in order to allow the corresponding memory cells to store the data with the corresponding data pattern. The data comparison circuit executes reverse-converting through the reading pattern selection units for comparing if the data stored in the memory cells corresponding to each memory data end are matched and accordingly determines if a failure memory cell exists in the memory.

Abstract: Embodiments include a file system data structure and file system recognition APIs that may allow an operating system to identify a partition of a storage device as having a valid file system, even if the operating system does not know how to access the file system a priori. File systems can implement these data structures in a standardized, known location within a partition on the storage device such that an operating system may use APIs or other functions to examine the known location for the presence of these data structures. Information on how to interpret the data structure may be obtained using a network or other source.

Abstract: An apparatus and method for a processor-memory unit for use in system-in-package (SiP) and system-in-package (SiP) integrated circuit devices. The apparatus includes a processing module, a memory module and a programmable system module. The programmable system module is configured to function as an interface between the memory module and the processing module, or as an interface between the memory module and a testing device. The invention facilitates integration and testing of processor-memory units including functional components having different communication protocols.

Abstract: A system and method for mitigating memory errors in a computer system. Faulty memory is identified and tested by a memory manager of an operating system. The memory manager may perform diagnostic tests while the operating system is executing on the computer system. Regions of memory that are being used by software components of the computer system may also be tested. The memory manager maintains a stored information about faulty memory regions. Regions are added to the stored information when they are determined to be faulty by a diagnostic test tool. Memory regions are allocated to software components by the memory manager after checking the stored information about faulty memory regions. This ensures a faulty memory region is never allocated to a software component of the computer system.

Abstract: Apparatus and methods for Cyclic Redundancy Check (CRC) error injection between storage controllers and storage devices in a storage system. A plurality of bridge devices are configured in a storage system each coupled persistently coupled to a corresponding one of the plurality of storage devices. Each bridge device may couple to one or more Serial Attached SCSI (SAS) initiators for transferring exchanges between one or more SAS initiators and the attached target storage device. Each bridge device receives parameters from a SAS initiator or an administrative client directing the bridge regarding injection of CRC errors. A log memory in each bridge may log information regarding the injected CRC errors.

Abstract: A semiconductor memory device includes a memory cell array, a mode setting circuit, a parity data generation unit, and a data error detection and correction unit. The memory cell array has a plurality of first memory banks for storing normal data, and a predetermined number of second memory banks less than the number of the first memory banks for storing parity data according to control of a first flag signal. The mode setting circuit sets the first flag signal and a second flag signal controlling based on whether a separate memory bank is used to store the parity data in the second memory banks. The parity data generation unit receives normal write data during a write operation, generates parity data with respect to the normal write data in response to the second flag signal, and outputs the normal data and the parity data.

Abstract: A information processing system comprises a memory module having a plurality of unit memory regions, a memory controller, connected to the memory module via memory interface, configured to control access to the memory module, an error detector, which is in the memory controller, configured to perform an error detection on data read from the memory module, a failure inspection controller configured to switch a mode of the memory controller from a normal mode to a failure inspection mode, read data from an address, where data was written, to be inspected for each of the plurality of unit memory regions, causes the error detector to detect an error in the read data and perform a failure inspection and a determining unit configured to determine a memory failure or a transmission path failure on the basis of the state of the error detected from the unit memory regions.

Abstract: An error detection control system for a nonvolatile memory comprises: a nonvolatile memory having data areas for a plurality of addresses each including a main data area and a redundant data area for one address; memory control means for controlling on the nonvolatile memory a batch erasing process on a data area group basis, a reading process on the data area basis, a programming process on the data area basis, and an overwriting process on a bit basis; error detecting means for executing the error detecting process based upon the corresponding redundant data; error detecting control means for controlling availability of execution of the error detecting process based upon data types to be classified depending on whether or not the data is subjected to the overwriting process or a storage state indicating whether or not the overwriting process has been executed.

Abstract: Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed.

Abstract: An information processing apparatus including a plurality of nodes, each node connecting at least a memory and a processor to a system bus; an interconnection bus that interconnects the nodes; a device that is connected to a system bus on any of the plurality of nodes and performs data processing; and a memory selecting unit that selects a memory connected to the system bus to which the device is connected as a memory to be accessed by the device.

Abstract: A process for quiescing a master and a plurality of subordinate computer systems in a cluster. An original or a pending state may be entered that is a quiesce or an online state. The master instructs the subordinates the quiesce or online state be made the pending state. The subordinates prepare to change accordingly, determine whether successful, and vote to commit or abort. Based on whether all voted to commit, the master instructs the subordinates to either commit or abort. If to commit and the pending state is the quiesce state, an operation is performed in the subordinates. If to commit and the pending state is the online state, the subordinates prepare to resume the original state. The subordinates change from the original to the pending state. Otherwise, if to abort, the subordinates prepare to remain in the original state and reset the pending to the original state.

Abstract: A method is used in managing loop interface instability. It is determined that a loop has excessive intermittent failures. It is determined, based on whether the intermittent failures are detectable on another loop, whether the cause of the excessive intermittent failures is within a specific category of components. A search procedure is executed that is directed to the specific category of components, to isolate the cause of the excessive intermittent failures.

Abstract: Provided is a storage system, including: one or more disk drives storing data; a disk controller for controlling data access to the disk drive; a power supply controller for autonomously turning off a power source of the disk drive according to the data access status to the disk drive, and autonomously turning on the power source of the disk drive, which was turned off, after the lapse of a prescribed period from the time the power source was turned off irrespective of the data access status to the disk drive; and a media inspection unit for inspecting a failure in the disk drive in which the power source thereof was autonomously turned on irrespective of the data access status to the disk drive.

Abstract: An apparatus and method are disclosed to configure, format, and test, a data storage subsystem product. The method supplies a data storage subsystem product comprising one or more host computer ports, a processor, one or more data storage device ports, and one or more data storage devices interconnected to the one or more data storage device ports. The method further supplies a configuration appliance comprising a storage configuration. The method connects the configuration appliance to one of the one or more storage device ports, boots up the data storage subsystem product, discovers the configuration appliance by the data storage subsystem product, imports storage configuration data into the data storage subsystem product, formats the one or more data storage device, and tests the input and output data transfer rates for the data storage subsystem product, wherein the formatting and testing are initiated concurrently.

Abstract: A storage management apparatus manages a plurality of storage apparatuses connected to each other over a network in a storage system that distributes data among the storage apparatuses and stores the data therein. The storage management apparatus has a patrol process executing unit configured to execute a patrol process to confirm whether a storage area of each storage apparatus operates normally and a patrol flow controlling unit configured to control a patrol flow indicating the speed of the patrol process executed by the patrol process executing unit.

Abstract: To provide a memory system which determines a memory state such as an exhaustion level and allows a memory to be efficiently used. The memory system includes a NAND type flash memory 1 in which data can be electrically written/erased, a nonvolatile memory 2 which counts the number of erase operations of the NAND type flash memory 1 and retains the number of erase operations and a maximum number of erase operations, and a controller 3 which has a connection interface 31 to be given a self-diagnosis command from a computer 4, and retrieves the number of erase operations and the maximum number of erase operations from the nonvolatile memory 2 based on the self-diagnosis command and outputs the number of erase operations and the maximum number of erase operations to the computer 4 through the connection interface 31.

Abstract: A system and method are provided for counting storage-related error events using a sliding window. This is accomplished by counting error events that occur within a sliding window of time and triggering a reaction based on such count. By this feature, the error events are counted with additional accuracy so that a reaction will be appropriately triggered. To this end, in various embodiments, more accurate error counting is afforded to avoid a situation, such as in fixed sampling window frameworks, where an appropriate reaction is not triggered due to a failure to count an appropriate number error events in close proximity.

Abstract: A method for managing a redundant memory architecture for an information handling system (IHS) may include providing redundant memory for a portion of system memory wherein the redundant memory is configured to mirror data stored in the portion of system memory. The method may further include reporting a parameter associated with the portion of system memory to an operating system of the IHS and executing a program from the portion of system memory.

Abstract: The invention provides a method for managing writing errors for a nonvolatile memory. In one embodiment, the nonvolatile memory is coupled to a controller. First, data received from the controller is stored in a data register of the nonvolatile memory. The data stored in the data register is then written to a first memory space with a first write address according to instructions from the controller. The data stored in the data register is kept from being changed after the data is written to the first write address. When an error occurs in writing of the data to the first memory space, a rewrite command is sent from the controller to the nonvolatile memory. After the nonvolatile memory receives the rewrite command, the data stored in the data register is written to a second memory space with a second write address according to the rewrite command.

Abstract: A test system includes a computer and an interface device for accessing a scan chain on an application specific integrated circuit (ASIC) under test. The computer includes a memory that contains application software that when executed by the computer quantifies soft errors and soft error rates (SER) in storage elements on the ASIC. The interface device receives commands and data from the computer, translates the commands and data from a first protocol to a second protocol and communicates the commands and data in the second protocol to the ASIC. A method for measuring SER in the ASIC includes baseline, comparison, and latch up accesses of data in a scan chain in the ASIC. Between accesses, the ASIC is exposed to a neutron flux that accelerates the occurrence of soft errors due to ionizing radiation upon the ASIC.

Abstract: A control device includes: memory diagnosis means for setting a power-on status when an electric power is turned on and diagnosing an ECC memory; restarting means for restarting the control device when the memory diagnosis means detects a correctable error of the ECC memory during the power-on status of the ECC memory; and operation processing means for resetting the power-on status and performing a normal operation when the memory diagnosis means does not detect a correctable error of the ECC memory, while performing the normal operation when a correctable error of the ECC memory is detected because of the restart of the control device by soft reset after the reset of the power-on status but when the control device is not in the power-on status.

Abstract: Systems and methods are provided for performing diagnostics on a removable media drive. An example system includes a monitoring unit configured to collect information about a media access to the media drive and a media access to a removable media contained in the media drive. The example system also includes a storage unit having a threshold table with at least one threshold value for the media access to the media drive. A processing unit is configured to compare the collected information of the monitoring unit to the at least one threshold value contained in the threshold table. The processing unit is also configured to determine diagnostic data relating to the removable media drive in accordance with the comparison.

Abstract: A system and method for a software override capability for enforcing a predetermined state for an otherwise hardware-programmable device. Software that may think it knows what it is doing may try to control a hardware device, but may not know about a hardware issue, such as another feature or defect requiring that the device stay in a certain state. The technique programmatically maintains a persistent hardware state independent of any other control software. To other software, the software layer of the invention is indistinguishable and inseparable from hardware. Nothing can slip in between. Any insertion attempt will be detected and disallowed. Features of the processor or system chips actually weld the software to the hardware, which feature disallows any software intervention between the welded software layer and the hardware.

Abstract: A process executing on a computing system may encounter an exception. Pointers or other references created by the exception may identify portions of the computing system's memory containing the binary code that was executing at the time of the exception. The exception-causing code from the system memory may be compared to an original version of the code from a non-volatile source. If the comparison identifies a hardware corruption pattern, the computing system may communicate information about the process and the exception to an error analysis server. Using historical exception data, the error analysis server may determine if the identified corruption pattern is most likely the result of corrupt hardware at the computing system. If corrupt hardware was the most likely result of the exception, then the server may communicate with the computing system to recommend or initiate a hardware diagnostic routine at the computing system to identify the faulty hardware.

Abstract: A write error detection mechanism for a computer data disk drive or storage controller writes and then verifies data to detect disk write errors. It allows the heads to be moved to other tracks to do other jobs in the time it takes the disk to rotate from the point the data was written and to return there again so it can be read to verify the write. The data written is temporarily stored in feature table memory outside the disk, so it can be used as in the comparison later when the written data can be read for the verify. In the interim, other write-and-verify and read operations can be pipelined, or multitasked using the same head, even on different tracks.

Abstract: A method, apparatus and system for improving failover within a high-availability computer system are provided. The method includes obtaining one or more parameters associated with at least one resource of any of the first cluster, second cluster and high-availability computer system. The method also includes detecting, as a function of the parameters, one or more anomalies of any of the first cluster, second cluster and high-availability computer system, wherein the at least one anomaly is a type that impacts the failover. These anomalies may include anomalies within the first and/or second clusters (“intra-cluster anomalies”) and/or anomalies among the first and second clusters (“inter-cluster anomalies”). The method further includes generating an alert in response to detecting one or more of the anomalies.

Abstract: A method for identifying non stuck-at faults in a read-only memory (ROM) includes generating a golden value of a victim cell, providing a fault-specific pattern through an aggressor cell, generating a test reading of the victim cell in response to the provided fault-specific pattern, and determining whether the ROM has at least one non stuck-at fault. The determination is based on a comparison of the golden value and the test reading of the victim cell.

Abstract: A semiconductor memory device includes a memory cell array and an error correction code (ECC) engine. The memory cell array stores bits of normal data and parity data therein. The ECC engine performs a masking operation in a masking mode, the ECC engine calculating the parity data using the normal data. The normal data includes a first section that is to be updated and a second section that is to be saved by the masking operation.