Abstract: A method begins by a processing module generating a payload section of a dispersed storage network (DSN) frame regarding a check request operation by generating one or more slice name fields of the payload section to include one or more slice names corresponding to one or more encoded data slices and generating a transaction number field of the payload section to include a transaction number corresponding to the check request operation. The method continues with the processing module generating a protocol header of the DSN frame by generating a payload length field of the protocol header to include a payload length that represents a length of the payload section and generating remaining fields of the protocol header.

Abstract: A redundant array of independent disks (RAID) system comprises N storage arrays, wherein each of the N storage arrays comprise a target processing module and 1 to M hard disk drives, where M and N are integers greater than 1. A data processing module selectively assigns error checking and correcting (ECC) processing for data blocks to selected ones of the target processing modules in a non-overlapping manner. A switch module provides communication paths between the data processing module and the N storage arrays and between each one of the N storage arrays and others of the N storage arrays.

Abstract: A controller updates a partition arrangement table and a backup-disk management table. The controller also creates, in a first disk, a logical memory area for storing a backup directory that has been stored in the first disk and that corresponds to a primary directory stored in a second disk of a processing element in which a failure has occurred.

Abstract: A system comprising a first memory, a second memory, and a controller. The first memory may be configured to store a first firmware. The second memory may be configured to store a second firmware similar to the first firmware stored on the first memory. The controller may be configured to (i) operate the first firmware stored on the first memory, (ii) discontinue operating the first firmware in response to a failure of the first firmware, and (iii) begin operating the second firmware after discontinuing operation of the first firmware.

Abstract: In response to a hypervisor page fault for memory that is not resident in a shared memory pool, an I/O paging request is sent to an external storage paging space. In response to a paging service partition encountering an I/O paging error, a paging failure indication is sent to the hypervisor. A simulated machine check interrupt instruction is sent from the hypervisor to the shared memory partition and a machine check handler obtains control. The machine check handler performs data analysis utilizing an error log in an attempt to isolate the I/O paging error to a process or a set of processes in the shared memory partition. The process or set of processes associated with the I/O paging error, or the shared memory partition itself, may be terminated. Finally, the shared memory partition may clear or initialize the page associated with the I/O paging error.

Abstract: A test apparatus includes: a test executing section executing a test on the device under test; a fail memory storing a test result outputted by the test executing section, the fail memory implementing an interleave technology for interleaving accesses to a plurality of banks; a buffer memory storing the test result transferred from the fail memory and transfers at least part of the test result to a cache memory, the buffer memory being either a memory not implementing the interleave technology or a memory implementing the interleave technology but having a smaller number of banks than the fail memory; the cache memory storing the at least part of the test result transferred from the buffer memory, the cache memory allowing random access in shorter time than the buffer memory does; and an analysis section analyzing the test result stored in the cache memory.

Abstract: An information handling system includes a host mapped general purpose input output (GPIO), a shared memory, a board management controller, and a cryptography engine. The host mapped GPIO includes a plurality of registers. The board management controller is in communication with the host mapped GPIO and with the shared memory, and is configured to control accessibility to the plurality of registers in the GPIO, and to control write accessibility of the shared memory based on a private key received from a basic input output system requesting accessibility to the plurality of registers and write accessibility of the shared memory. The cryptography engine is in communication with the board memory controller, and is configured to authenticate the private key received from the board management controller.

Abstract: Disclosed are methods, systems and devices, such as a device including a data location, a quantizing circuit coupled to the data location, and a test module coupled to the quantizing circuit. The quantizing circuit may include an analog-to-digital converter, a switch coupled to the memory element and a feedback signal path coupled to the output of the analog-to-digital converter and to the switch.

Abstract: A system and method for providing a high fault tolerant memory system. The system includes a memory system having a memory controller, a plurality of memory modules and a mechanism. The plurality of memory modules are in communication with the memory controller and with a plurality of memory devices. The plurality of memory devices include at least one spare memory device for providing memory device sparing capability. The mechanism is for detecting that one of the memory modules has failed possibly coincident with a memory device failure on an other of the memory modules. The mechanism allows the memory system to continue to run unimpaired in the presence of the memory module failure and the possible memory device failure.

Abstract: A system and method of input/output (I/O) workload analysis of the components in a storage area network (SAN) are disclosed. In one embodiment, I/O workloads of components in the SAN are analyzed by determining host bus adapter (HBA) port to storage port oversubscription ratios as well as HBA port to inter-switch link (ISL) oversubscription ratios. A subset of the components for monitoring based on the HBA port to storage port oversubscription ratios and the HBA port to ISL oversubscription ratios is selected. The subset of the components is continuously monitored and the I/O statistics of the subset of the components are stored. Expected I/O workloads of the subset of the components are forecast based on current I/O workloads associated with the I/O statistics of the subset of the components and respective I/O workload threshold values of the subset of the components.

Abstract: A system and method for error correction and detection in a memory system. The system includes a memory controller, a plurality of memory modules and a mechanism. The memory modules are in communication with the memory controller and with a plurality of memory devices. The mechanism detects that one of the memory modules has failed possibly coincident with a memory device failure on an other of the memory modules. The mechanism allows the memory system to continue to run unimpaired in the presence of the memory module failure and the memory device failure.

Abstract: An apparatus for generating and managing logical units (LUNs) in a storage network environment is disclosed herein. In one embodiment, such an apparatus includes an identification module to identify a type of LUN, one or more servers that will access the LUN, and a storage system that will host the LUN. A mapping module maps the type, the one or more servers, and the storage system to one more abbreviations. A naming module then generates a LUN name that encapsulates the abbreviations. An assignment module may then assign the LUN name to the LUN. A corresponding method and computer program product are also disclosed herein.

Abstract: A method, device, and system are disclosed. In one embodiment method includes determining a left edge and right edge of a valid data eye for a memory. The method continues by periodically checking the left and right edges for movement during operation of the memory. If movement is detected, the method retrains the valid data eye with an updated left edge and right edge.

Abstract: One or more switches are interposed between a controller portion and a storage device. When transmission of a command to a certain storage device fails, a command is transmitted starting from an upstream side to a downstream side of a path between the controller portion and the switch to which the certain storage device is connected, and when command transmission fails while transmitting a command from a kth switch (k is an integer of 0 or more) which is connected to a (k+1)th switch and is one level upstream of the (k+1)th switch or from any port of the controller portion, it is determined that a failure has occurred in a power source that supplies power to the (k+1)th switch.

Abstract: The service life of memory cards is to be substantially elongated against the occurrence of faulty blocks. A control logic searches blocks in a nonvolatile memory cell array for any acquired fault on the basis of a fault-inviting code in a management information section. If any faulty block is detected, the faulty block will be subjected to write/read comparison of data to judge whether or not the data in the block are normal. Any block determined to be normal will undergo rewriting of its fault-inviting code and registered as a normal block. Further, the registered block is stored into a write management table in the management area as a writable block. This enables an essentially normal block judged faulty on account of an erratic error or some other reason to be restored.

Abstract: An error processing method processes an error generated on a bus of a CPU, by inputting a bus error that is generated on at least one of an instruction bus and a data bus of the CPU to the CPU by a bus error input part, counting the bus error by a bus error counter part of the CPU, and specifying a region of a memory part that is coupled to the CPU based on a value of the bus error counter part.

Abstract: Embodiments of methods and systems for controlling access to information stored on memory or data storage devices are disclosed. In various embodiments, methods of retrieving information from a data storage device previously deactivated by modification or degradation of at least a portion of the data storage device are disclosed.

Abstract: In a method of controlling an information processing system in which an information processing device is connected to each of a plurality of input/output ports provided in a routing device and having a first property or a second property, for conducting data transmission among the information processing devices via the routing device, a step of causing all of the information processing devices to halt data transmission, a step of resetting properties and identification information of the input/output ports with the second properties other than the input/output port with the first property which cannot be used, in the routing device, and a step of causing the information processing devices to restart the data transmission after the reset of the identification information are executed.

Abstract: A method, system, and program product for a VTS subsystem's logging server to optimize applications' logging data entries where applications use the logging service. More specifically, in certain embodiments, the system comprises logic executed within a VTS subsystem to which a tape library subsystem is attached. The logic controls VTS subsystem applications' logging data entry strategy through applications' configured logging level, log entry category, and a cache buffer. The logic not only dynamically balances applications' logging request but also maximizes the availability of system information.

Abstract: A network device including a receiver, a counter, and a trigger. The receiver is configured to receive idle code groups or false carriers from a remote device. The idle code groups indicate that there is no data to be sent from the remote device, and the false carriers indicate a fault. The counter is configured to count the at least one of the idle code groups or the false carriers detected during a predetermined period. The trigger is configured to (i) assert a first signal if the counter exceeds a predetermined threshold during the predetermined period to resynchronize the network device to the remote device and (ii) count a number of times the first signal is asserted without bringing down a link between the network device and the remote device.

Abstract: Methods, apparatuses and systems are disclosed for a memory device. In one embodiment, a memory device is disclosed that may include a command error module operably coupled to a mode register, a command input, and an address input. The command error module may be configured to detect an invalid command sequence and report an error indication to an output signal. Additionally, the memory device may include a temperature sensor operably coupled to a mode register and a reference voltage. The temperature sensor may be configured to sense a device temperature and report a temperature status. Furthermore, the memory device may be incorporated into a memory module, which may be included in an electronic system.

Abstract: A semiconductor memory device including a plurality of banks, each including a plurality of memory cells, a pattern signal generator configured to generate pattern signals having combinations in response to an input signal applied through an arbitrary pad in a compression test mode. Input paths are configured to transfer the plurality of pattern signals to the corresponding banks.

Abstract: A set of disks in a plurality of disk arrays are configured to have one or more spare partitions. Upon detecting a faulty disk in a faulty array, the method involves the steps of: (a) migrating data in the faulty array containing the faulty disk to one or more spare partitions; (b) reconfiguring the faulty array to form a new array without the faulty disk; (c) migrating data from one or more spare partitions in the set of disks to the reconfigured new array; (d) monitoring to identify when overall spare capacity falls below a predetermined threshold; and when the predetermined threshold is exceeded, scheduling a service visit for replacement of the failed disks.

Abstract: A computer system having a plurality of devices including a data storage part which includes a plurality of cells to store data, and a controller to inspect whether there is a defective cell in the data storage part if a condition to execute a cell inspection function is met, and sets the defective cell to be assigned to one of the devices if a defective cell is found.

Abstract: A storage controller including a first controller. The first controller includes a memory module, a test access port controller, the test access port controller configured to control a built in self-test operation on the memory module, and a register configured to store a first instruction. In response to the storage controller detecting a test access port interface being accessible to the storage controller, the test access port controller is configured to control the built in self-test operation on the memory module of the first controller by having either (i) a second instruction sent from the test access port controller to the first controller or (ii) the first instruction sent from the register to the first controller. The first controller is configured to perform the built in self-test operation on the memory module in response to having received the first instruction or having received the second instruction.

Abstract: A method for data protection includes, in a first operational mode, sending data items for storage in a primary storage device and in a secondary storage device, while temporarily caching the data items in a disaster-proof storage unit and subsequently deleting the data items from the disaster-proof storage unit, wherein each data item is deleted from the disaster-proof storage unit upon successful storage of the data item in the secondary storage device. An indication of a fault related to storage of the data in the secondary storage device is received. Responsively to the indication, operation is switched to a second operational mode in which the data items are sent for storage at least in the primary storage device and are cached and retained in the disaster-proof storage unit irrespective of the successful storage of the data items in the secondary storage device.

Abstract: A disk drive is described which executes distributed computing tasks including a CPU and associated memory. The communication interface with the host computer is modified to allow the host computer to send executable code for a task to the drive and to allow the drive to communicate the results and status information about the task to the host computer. In a preferred embodiment the disk drive has a task control program, task program code, task data and status information for the distributed task. In alternative embodiments, the disk drive can communicate with other similar disk drives in the bus to provide the results of computation to the other processors. The RAM memory, and mass storage are intimately connected through the associated hard disk controller such that the exact location of the required data and program instructions are known.

Abstract: The invention provides a memory circuit comprising a plurality of storage cells for storing data and redundant spare storage cells for replacing defective storage cells, and a memory access logic for accessing said storage cells connected to a replacement setting register which is writeable during operation of said memory circuit to store replacement settings.

Abstract: Provided are an apparatus and method for processing data of flash memory. The apparatus includes a user requesting unit to request a data operation using a predetermined logical address, a transformation unit to transform the logical address into a physical address, and a control unit to record count data counting the number of predetermined bits of data, in an index region to indicate whether the data is valid when conducting the data operation.

Abstract: A memory chip having a memory with a plurality of non-redundant memory lines and a plurality of redundant memory lines, and a controller configured to allocate dynamically a redundant memory line to a failed memory line during runtime.

Abstract: Detecting brown-out in a system having a non-volatile memory (NVM) includes loading data in the NVM, wherein a next step in loading is performed on a location in the NVM that is logically sequential to an immediately preceding loading. A pair of adjacent locations include one with possible data and another that is empty. Determining which of the two, if at all, have experienced brownout includes using two different sense references. One has a higher standard for detecting a logic high and the other higher standard for detecting a logic low. Results from using the two different references are compared. If the results are the same for both references, then there is no brownout. If the results are different for either there has been a brownout. The location with the different results is set to an invalid state as the location that has experienced the brownout.

Abstract: Management server 16 may obtain application programs from content server 20 in response to requests of mobile terminal 11. Management server 16 may transmit the obtained application programs to mobile terminal 11 with information concerning reliabilities of the application programs. After mobile terminal 11 receives the application programs from management server 16, mobile terminal 11 manages operations of the application programs. Operations of the application programs are coordinated with operations of other programs using the information concerning the reliabilities corresponding to the application programs. Management of the coordinated operations of the application programs avoids problems concerning information security, where valuable information may be distributed unexpectedly because of operations of low reliable application programs. As a result, convenience of users of mobile terminals 11 can be improved without deteriorating the information security of mobile terminals 11.

Abstract: A degeneration control device that controls degeneration of a cache having a plurality of ways based on an error that occurs in response to an access request, includes a cache line degeneration information memory unit, which stores cache line degeneration information that indicates whether a cache line constituting each of the plurality of ways is degenerated, and a degeneration control unit, which writes, when an error that occurs in response to the access request causes a predetermined condition to be met, cache line degeneration information that indicates a predetermined cache line where the error occurs is degenerated in the cache line degeneration information memory unit.

Abstract: An apparatus and method for a processor-memory unit for use in system-in-package (SiP) and system-in-package (SiP) integrated circuit devices. The apparatus includes a processing module, a memory module and a programmable system module. The programmable system module is configured to function as an interface between the memory module and the processing module, or as an interface between the memory module and a testing device. The invention facilitates integration and testing of processor-memory units including functional components having different communication protocols.

Abstract: A control apparatus controls a device to which the control apparatus is connected. The control apparatus includes a storing unit and a linking unit. The storing unit stores an error message that contains information on a failed component in a storage device upon receiving the error message from the device. The linking unit stores the error message and information on a replacement component, which has been installed in the device in place of the failed component, in the storage device in association with each other upon receiving the information on the replacement component.

Abstract: A storage subsystem has a plurality of storage devices. An indication of failure of at least one of the plurality of storage devices is detected. In response to detecting the indication of failure, monitoring is performed for a further condition. According to the monitored further condition, it is determined whether the at least one storage device has failed or whether communication has been lost to the storage subsystem. In response to determining that communication has been lost, state information of the storage subsystem is preserved to enable restoration of the storage subsystem after communication to the storage subsystem is recovered.

Abstract: A method for controlling an execution of a first DMA task, the method includes comprises monitoring an execution of the first DMA task, the method characterized by including defining a first DMA task execution interval and a first DMA task execution sub-interval; and performing a first possible timing violation responsive operation if the first DMA task was not completed during the first DMA task execution sub-interval. A device having a first DMA task controlling capabilities, the device includes a memory unit; characterized by including a DMA controller that is adapted to monitor an execution of the first DMA task that involves an access to the memory unit, and to perform a first possible timing violation responsive operation if the first DMA task was not completed during a first DMA task execution sub-interval.

Abstract: An evaluation method is proposed to evaluate reliability of a nonvolatile memory in a semiconductor storage device with respect to data writing and data reading. While power is being supplied to the semiconductor storage device, a test program and the control program are written in a storage unit of the semiconductor storage device. The test program being written to control execution of an evaluation test performed for evaluating the reliability of the nonvolatile memory and generate a simulated access command identical to an access command input externally for accessing the nonvolatile memory. Access to the nonvolatile memory is controlled according to the test program and control program in the storage unit.

Abstract: Methods and devices operate to apply and provide differing levels of error correction within a multi-level, non-volatile memory. In an example, the differing level of error correction is provided within one page of a row of multi-level cells relative to other pages stored within the same row of multi-level cells.

Abstract: A system and method for logging and storing failure analysis information on disk drive so that the information is readily and reliably available to vendor customer service and other interested parties is provided. The information, in an illustrative embodiment, is stored on a nonvolatile (flash) random access memory (RAM), found generally in most types of disk drives for storage of updateable disk drive firmware. A known location of limited size is defined in the flash RAM, to form a scratchpad. This scratchpad is a blank area of known addresses, formed during the original firmware download onto the memory, and which is itself free of firmware code. This scratchpad is sufficient in size to write a series of failure codes in a non-erasable list as failures/errors (and user/administrator attempts to unfail the disk) are logged.

Abstract: A method for monitoring the status of a memory device is disclosed. The method includes, during operation of the memory device, exercising a first portion of the memory device more than at least one other portion of the memory device in order to induce an accelerated rate of aging of the first portion. The first portion is monitored to detect at least a potential for a failure in the first portion. According to the method, in response to monitoring the first portion, at least one corrective action is performed. Apparatus and computer readable media are also disclosed.

Abstract: Provided is a computer system including at least one host computer; and at least one storage system, characterized in that: the storage system has a disk drive and a disk controller, and provides a storage area of the disk drive as at least one logical unit; upon detecting a failure in a logical path serving as an access route from the host computer to the logical unit, the host computer specifies logical paths for accessing the same logical unit that is connected to the logical path where the failure is detected; the host computer executes failure detecting processing for the specified logical paths to judge whether the specified logical paths are normal or not; the host computer selects normal logical paths out of the specified logical paths; and the host computer accesses the logical unit via the normal logical paths selected.

Abstract: A response of a disk device during rebuild can be sped up. A disk array control device determines whether or not there is a normal read request during rebuild. If there is a read request during rebuild, data is read by sequentially switching a plurality of disk devices in a certain block size unit lower than a block size in which each disk device reads data during normal read.

Abstract: Leaked memory in a computer system is detected and recovered by first detecting memory leakage within the computer system based on nonlinear and non-parametric time-series regression analysis of software telemetry data generated by one or more software process running on the computer system. If existence of memory leakage is detected, then memory that has leaked is specifically identified and recovered. This is done by halting one or more of the software processes, generating a core image file or files of the halted software process(es), and re-starting the halted process or processes without waiting for analysis of the core image file(s). Then, the core image file is evaluated to specifically identify leaked memory in the computer system based on the core image file. Finally, the identified leaked memory is recovered.

Abstract: A method for updating firmware in a communication device storing an original firmware in a first data area of a non-volatile memory includes receiving and storing a new firmware in a second data area of the non-volatile memory. The method comprises assigning a firmware other than the new firmware as a boot firmware for the communication device before verification of the new firmware. The new firmware is loaded and executed in response to a boot procedure of the communication device. If the new firmware is executable and causes the communication device to satisfy a predetermined boot up condition, the new firmware passes the bootability check, and the new firmware is assigned as the boot firmware. The new firmware is not assigned as the boot firmware if the new firmware does not pass the bootability check.

Abstract: An electrical field device has a microprocessor-controlled control device, a data memory which is inside the device and is connected to the control device via a first memory controller, and a data interface which is connected to the control device and is intended to connect external devices to the electrical field device. In order to ensure access to the data memory inside such a field device even when the control device or internal power supply device is not in working order, the data interface is connected to the data memory inside the device via a second memory controller. There is also disclosed a method for establishing a data link between a data interface of an electrical field device and a data memory inside the device.

Abstract: In some embodiments a request is received to perform an error injection or a memory migration, a mode is entered that blocks requests from agents other than a current processor core or thread, the error is injected or the memory is migrated, and the mode that blocks requests from the agents other than the current processor core or thread is exited. Other embodiments are described and claimed.

Abstract: In a storage system, a first loop and a second loop are connected to a controller, and at least one of the first loop and the second loop is connected to existing storage devices (which are physical storage devices other than additional storage devices, which are physical storage devices which are additionally provided). In processing for additional provision, after having disconnected all of the existing storage devices from the first loop, the controller connects an additional storage device to the first loop. And the controller acquires, via said first loop, an address acquired by this additional storage device, and makes a first suitability decision as to whether or not this address is appropriate. And, if the result of this first suitability decision is negative, then the controller blocks up this additional storage device whose address has been acquired.

Abstract: Embodiments relate to systems and methods for managing stalled storage devices of a storage system. In one embodiment, a method for managing access to storage devices includes determining that a first storage device, which stores a first resource, is stalled and transitioning the first storage device to a stalled state. The method also includes receiving an access request for at least a portion of the first resource while the first storage device is in the stalled state and attempting to provide access to a representation of the portion of the first resource from at least a second storage device that is not in a stalled state. In another embodiment, a method of managing access requests by a thread for a resource stored on a storage device includes initializing a thread access level for an access request by a thread for the resource.

Abstract: A solid-state mass storage device and method of operating the storage device to anticipate the failure of at least one memory device thereof before a write endurance limitation is reached. The method includes assigning at least a first memory block of the memory device as a wear indicator that is excluded from use as data storage, using pages of at least a set of memory blocks of the memory device for data storage, writing data to and erasing data from each memory block of the set in program/erase (P/E) cycles, performing wear leveling on the set of memory blocks, subjecting the wear indicator to more P/E cycles than the set of memory blocks, performing integrity checks of the wear indicator and monitoring its bit error rate, and taking corrective action if the bit error rate increases.