Memory Or Storage Device Component Fault Patents (Class 714/42)
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Patent number: 8132045Abstract: In a nonvolatile memory system, data received from a host by a memory controller is transferred to an on-chip cache, and new data from the host displaces the previous data before it is written to the nonvolatile memory array. A safe copy is maintained in on-chip cache so that if a program failure occurs, the data can be recovered and written to an alternative location in the nonvolatile memory array.Type: GrantFiled: June 16, 2009Date of Patent: March 6, 2012Assignee: SanDisk Technologies, Inc.Inventors: Chris Nga Yee Avila, Jonathan Hsu, Alexander Kwok-Tung Mak, Jian Chen, Grishma Shailesh Shah
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Publication number: 20120054556Abstract: A method begins by a processing module monitoring a reprovisioned memory device that has been reprovisioned from a legacy storage protocol to an error coding dispersed storage protocol. The method continues with the processing module determining a data migration scheme for migrating a plurality of encoded data slices stored on the reprovisioned memory device and migrating the plurality of encoded data slices from the reprovisioned memory device to one or more other memory devices in accordance with the data migration scheme when a usable memory life of the reprovisioned memory device in the error coding dispersed storage protocol has expired.Type: ApplicationFiled: August 5, 2011Publication date: March 1, 2012Applicant: CLEVERSAFE, INC.Inventors: GARY W. GRUBE, TIMOTHY W. MARKISON, JASON K. RESCH, ILYA VOLVOVSKI, MANISH MOTWANI
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Patent number: 8127202Abstract: A system and method, including computer software, allows reading data from a flash memory cell. Voltages from a group of memory cells are detected. The group of memory cells have associated metadata for error detection, and each memory cell stores a voltage representing a data value selected from multiple possible data values. Each possible data value corresponds to one range of multiple non-overlapping ranges of analog voltages. Memory cells having uncertain data values are identified based on the detected voltages. Alternative data values for the memory cells having the uncertain data values are determined, and a combination of alternative data values is selected. An error detection test is performed using the metadata associated with the multiple memory cells and the selected combination of alternative data values.Type: GrantFiled: June 23, 2009Date of Patent: February 28, 2012Assignee: Apple Inc.Inventors: Michael J. Cornwell, Christopher P. Dudte
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Patent number: 8122320Abstract: An integrated circuit includes a memory array and an error correction code (ECC) circuit configured to provide a first signal indicating whether data read from the memory array has been corrected by the ECC circuit. The integrated circuit includes a mimic circuit configured to provide a second signal indicating whether the first signal is valid and a counter configured to increment in response to the second signal indicating the first signal is valid and the first signal indicating an error.Type: GrantFiled: January 22, 2008Date of Patent: February 21, 2012Assignee: Qimonda AGInventors: Khaled Fekih-Romdhane, Peter Chlumecky
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Patent number: 8122295Abstract: A circuit is operated to detect unstable memory cells from among a plurality of memory cells in at least one page. A determination is made from an initial status of data stored in a memory cell whether no read error occurs when the data is read at a standard read voltage level, whether a read error occurs and the read error is correctable, and whether a read error occurs and the read error is uncorrectable. Responsive to determining that a read error occurs that is correctable, a further determination is made as to whether the memory cell is correctable by reading the data stored in the memory cell at a correction read voltage level, which has a different voltage level from the standard read voltage level, and by determining whether a read error occurring in the data read at the correction read voltage level is correctable or uncorrectable.Type: GrantFiled: May 5, 2010Date of Patent: February 21, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Seon-taek Kim, Yoon-young Kyung
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Patent number: 8122294Abstract: An apparatus, system, and method are disclosed for rapidly grading the operating condition of computer storage. A storage log module 312 logs error information regarding any error in a storage subsystem 302 that occurs during normal operation. A storage test module 314 performs a cursory check 318 of the storage subsystem 302 as requested by a user. A storage diagnostic module 316 grades the storage subsystem 302 on an operating condition scale based at least in part upon the error information logged and upon results of the cursory check 318. In one embodiment, the storage subsystem 302 is graded as pristine if no error has been logged and no error was detected by the cursory check 318, as potentially failing if any error has been logged but no error was detected by the cursory check 318, and as failing if any error was detected by the cursory check 318.Type: GrantFiled: November 3, 2008Date of Patent: February 21, 2012Assignee: Lenovo (Singapore) Pte. Ltd.Inventors: Philip Lee Childs, Jeffrey R. Hobbet, Michael Terrell Vanover
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Patent number: 8122298Abstract: Methods and systems for capturing error information regarding a Serial Advanced Technology Attachment (SATA). An initiator device is enhanced in accordance with features and aspects hereof to detect an error condition in operation of the system and to transmit error information to the SATA target device during a soft reset condition applied to the SATA target device. The SATA target device discards all such frames received during the soft reset condition until the initiator device clears the soft reset condition. The error information may be captured for further analysis and debug of the error condition by suitable error analyzer equipment such as a SATA bus analyzer. The initiator device may be a SATA initiator or a Serial Attached SCSI (SAS) initiator using the SATA Tunneling Protocol (STP). Features and aspects hereof may also include a SAS/SATA bridge device coupling a SAS initiator to the SATA target device.Type: GrantFiled: June 12, 2008Date of Patent: February 21, 2012Assignee: LSI CorporationInventor: Ross J. Stenfort
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Publication number: 20120042211Abstract: A mechanism is provided for controlling a solid state disk. A failure detector detects a failure in the solid state disk. Responsive to failure detector detecting a failure, a status degrader sets a degraded status indicator for the solid state disk. Responsive to the degraded status indicator, a degraded status controller maintains the solid state disk in operation in a degraded operation mode.Type: ApplicationFiled: April 7, 2010Publication date: February 16, 2012Applicant: International Business Machines CorporationInventors: Joanna K. Brown, Ronald J. Venturi
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Patent number: 8117501Abstract: A virtual library apparatus includes an exclusive control section that exclusively secures a logical drive and a physical drive according to an instruction from a host at a time of an occurrence of an error in the physical drive and a diagnostic section that performs a diagnostic process on the exclusively secured physical drive through the exclusively secured logical drive. The exclusive control section releases the exclusively secured logical and physical drives after the diagnostic section completes the diagnostic process for the physical drive.Type: GrantFiled: January 21, 2010Date of Patent: February 14, 2012Assignee: Fujitsu LimitedInventors: Yukio Taniyama, Yasuhiko Hanaoka
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Patent number: 8116079Abstract: A storage device transporter includes a transporter body having first and second body portions. The first body portion is configured to be engaged by automated machinery for manipulation of the storage device transporter. The second body portion is configured to receive and support a storage device. The first body portion is configured to receive and direct an air flow over one or more surfaces of a storage device supported in the second body portion.Type: GrantFiled: June 14, 2010Date of Patent: February 14, 2012Assignee: Teradyne, Inc.Inventor: Brian S. Merrow
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Patent number: 8117526Abstract: A method for extracting an original message from a received signal including data bits representing the original message or an inverted version thereof, an indicator indicating whether the data bits represent the original message or the inverted version thereof, and a check information which depends on the data bits and the indicator, the method including determining a check information based on the received data bits and the received indicator, comparing the determined check information with the received check information and extracting the original message based on the result of the comparison.Type: GrantFiled: November 29, 2007Date of Patent: February 14, 2012Assignee: Qimonda AGInventor: Maurizio Skerlj
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Patent number: 8111412Abstract: According to a printer of the present invention, the displaying unit creates a print image of the image received by the receiving unit and displays a preview of the print image when the loss detecting unit detects the lost part of the image, and the displaying unit creates a print image of an image obtained as a result of the trimming and displays a preview of the print image when the trimming unit trims the image, and the printing unit prints an image obtained as a result of the trimming by the trimming unit. Consequently, if a user failed in communicating an image as the user did not set an external communication terminal to an appropriate place and the image has been lost, the user can display a preview of the image by removing the lost part by trimming and display the lost part by a preview, check the trimmed image and print it.Type: GrantFiled: January 30, 2007Date of Patent: February 7, 2012Assignee: Fujifilm CorporationInventors: Shinya Yamada, Satoshi Ueda
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Patent number: 8112664Abstract: Restore software executing in a computer system may invoke a snapshot of a target volume before restoring a plurality of files from a backup image to the target volume. If the restore operation fails before all the files are restored to the target volume then the restore software may use the snapshot to return one or more of the files to their original states as they existed before the restore operation was initiated.Type: GrantFiled: March 26, 2008Date of Patent: February 7, 2012Assignee: Symantec Operating CorporationInventors: Suren Sethumadhavan, Ynn-Pyng “Anker” Tsaur
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Patent number: 8112661Abstract: Embodiments of the present invention provide a method and system for providing, in a network storage system, a topology set to a storage administrator for selection of a topology to implement a new protection policy for a dataset. A topology includes a mapping between storage objects participating to effectuate an existing protection policy and storage objects participating to effectuate the new protection policy. When a storage administrator selects a new protection policy, a storage manager automatically generates a number of topology options including a storage object participating in the existing protection policy. According to a priority rule, the storage manager determines the priority of the topologies by computing a priority indicator for each of the topologies. In certain embodiments, the topology set is displayed to a storage administrator including the priority indicator for each topology for informing the storage administrator the relative preference of each topology.Type: GrantFiled: February 2, 2009Date of Patent: February 7, 2012Assignee: NetApp, Inc.Inventors: David Eric La France, Colin Johnson, Shraddha Sorte
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Patent number: 8107398Abstract: Methods, devices and systems for improved zone merge operations are disclosed. Two connected switches are arbitrated as an initiator and a receiver. The merge operation is initiated only by the initiator on an initiator/receiver inter-switch link. The initiator may initiate a merge request and the receiver may perform the computation of the difference between the old and the new zone. Either the whole configuration or only the differences are communicated between the switches. The merges may be done on a connected switch basis, not on a connected port basis. Only the principle ports in the principle inter-switch-link perform the merge operation. All the remaining ports, i.e. the non-principle ports, adopt the merge result of the principle ports. The zone information may also be cached on each switch such that merge calculations need not be performed again when a merge operation with the same configuration occurs in the future.Type: GrantFiled: August 21, 2009Date of Patent: January 31, 2012Assignee: Brocade Communications Systems, Inc.Inventors: Yi Lin, Eric Andre Warmenhoven, James Hu, Sundar Poudyal
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Patent number: 8108647Abstract: A communications architecture utilizes modules arranged in a daisy-chain, each module supporting multiple input and output ports. Point-to-point links are arranged so that a first output link of each of multiple modules connects to the next module in the chain, and a second output link connects to a module after it, and inputs arranged similarly, so that any single module can be by-passed in the event of malfunction. Multiple chains may be cross-linked and/or serviced by hubs or chains of hubs. Preferably, the redundant links are used in a non-degraded operating mode to provide higher bandwidth and/or reduced latency of communication. The exemplary embodiment is a memory subsystem in which the modules are buffered memory chips.Type: GrantFiled: January 29, 2009Date of Patent: January 31, 2012Assignee: International Business Machines CorporationInventors: Gerald Keith Bartley, Darryl John Becker, John Michael Borkenhagen, Philip Raymond Germann, William Paul Hovis, Mark Owen Maxson
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Patent number: 8108737Abstract: A system, method, and computer program product are provided for sending failure information from a solid state drive (SSD) to a host device. In operation, an error is detected during an operation associated with a Serial ATA (SATA) solid state drive. Additionally, a command is received for failure information from a host device. Further, the failure information is sent from the solid state drive to the host device, the failure information including failure information associated with the solid state drive.Type: GrantFiled: October 5, 2009Date of Patent: January 31, 2012Assignee: SandForce, Inc.Inventor: Ross John Stenfort
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Publication number: 20120023374Abstract: The embodiments provide a failure diagnosis method for a main memory in an information processing device equipped with a write-back cache. According to the method, an application program stored in the main memory is divided by the storage size of write-back cache, and the regions are stored in advance. Then, a read signal from the main memory to the write-back cache is detected. It is determined whether the region corresponding to the read signal has yet to be diagnosed. If the region has yet to be diagnosed, a command to diagnose failure of the region is issued. If a write signal (write back) to a particular region is detected during the diagnosis of the particular region, the diagnosis of the particular region is stopped. Thus, the failure diagnosis of the main memory is executed in parallel with the execution of the application program.Type: ApplicationFiled: February 11, 2011Publication date: January 26, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Naoya OHNISHI, Hiroshi Nakatani, Yoshito Sameda
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Patent number: 8103900Abstract: A method and circuit for implementing enhanced memory reliability using memory scrub operations to determine a frequency of intermittent correctable errors, and a design structure on which the subject circuit resides are provided. A memory scrub for intermittent performs at least two reads before moving to a next memory scrub address. A number of intermittent errors is tracked where an intermittent error is identified, responsive to identifying one failing read and one passing read of the at least two reads.Type: GrantFiled: July 28, 2009Date of Patent: January 24, 2012Assignee: International Business Machines CorporationInventors: Richard E. Fry, Marc A. Gollub, Eric E. Retter, Kenneth L. Wright
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Patent number: 8099632Abstract: The variable latency associated with flash memory due to background data integrity operations is managed in order to allow the flash memory to be used in isochronous systems. A system processor is notified regularly of the nature and urgency of requests for time to ensure data integrity. Minimal interruptions of system processing are achieved and operation is ensured in the event of a power interruption.Type: GrantFiled: September 28, 2007Date of Patent: January 17, 2012Assignee: SanDisk Technologies Inc.Inventors: J. James Tringali, Sergey A. Gorobets, Shai Traister, Yosief Ataklti
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Patent number: 8095827Abstract: A method for replicating a volume of data including selecting a target storage box to receive a physical copy of the actual volume of data stored on the source storage box for replication of the actual volume of data, selecting a point in time storage box to receive a physical copy of actual data stored on the target storage box, physically copying actual data stored on the target storage box to the point in time storage box, performing the replication of the actual volume of data by initiating the physical copying on the target storage box of the actual volume of data, and selectively undoing the physical copying on the target storage box of the actual volume of data by replacing the current actual data stored on the target storage box with the physical copy of actual target storage box data stored on the point in time storage box.Type: GrantFiled: November 16, 2007Date of Patent: January 10, 2012Assignee: International Business Machines CorporationInventors: David R. Blea, Errol J. Calder, Steven M. Kern, William D. Olsen, Jeffrey R. Placer, Benjamin J. Randall, Todd B. Schlomer, Jacob A. Stevens, John J. Wolfgang
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Patent number: 8090992Abstract: A method, apparatus, and system of improved handling of clustered media errors in raid environment are disclosed. In one embodiment, a method includes starting a command timer when a firmware accepts a command from a host, tracking an amount of time the command spends on handling of a clustered media error through the command timer, and stopping the command timer when at least one of the command is completed and a time limit expires. The method may complete a read as a success when a host IO is a read command. The method may complete a write as a success, after writing parity, and data when the host IO may be a write command.Type: GrantFiled: July 25, 2008Date of Patent: January 3, 2012Assignee: LSI CorporationInventors: Kapil Sundrani, Anant Baderdinni
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Patent number: 8090991Abstract: A logical central processing unit (logical CPU) selects a target device. When the target device is shared by another logical CPU, the logical CPU determines whether the logical CPU is in charge of exclusively making diagnosis of the target device. When the target device is not shared by another logical central processing unit or when the logical CPU is exclusively in charge of making diagnosis of the target device, the logical CPU makes diagnosis of the target device and stores a result of diagnosis in a storage unit.Type: GrantFiled: August 6, 2008Date of Patent: January 3, 2012Assignee: Fujitsu LimitedInventor: Hidenori Higashi
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Patent number: 8090988Abstract: An embodiment is a method and apparatus to save data during power failure. A power supply generator generates operating voltages to a circuit from a generator supply source. A power monitor monitors a normal supply voltage and a backup supply voltage to provide a normal supply voltage to the generator supply source in a normal mode and to provide a backup supply voltage to the generator supply source in a power failure mode. A data transfer circuit transfers data from a volatile memory in the circuit to a non-volatile memory during the power failure mode.Type: GrantFiled: November 24, 2009Date of Patent: January 3, 2012Assignee: Virtium Technology, Inc.Inventor: Phan Hoang
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Publication number: 20110320862Abstract: Embedded dynamic random access memory (EDRAM) macro disablement in a cache memory includes isolating an EDRAM macro of a cache memory bank, the cache memory bank being divided into at least three rows of a plurality of EDRAM macros, the EDRAM macro being associated with one of the at least three rows, iteratively testing each line of the EDRAM macro, the testing including attempting at least one write operation at each line of the EDRAM macro, determining if an error occurred during the testing, and disabling write operations for an entire row of EDRAM macros associated with the EDRAM macro based on the determining.Type: ApplicationFiled: June 24, 2010Publication date: December 29, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael Blake, Timothy C. Bronson, Hieu T. Huynh, Pak-kin Mak
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Publication number: 20110314338Abstract: Described are techniques for detecting data collisions between a first portion and a second portion of an application executing on a computer, the first portion and the second portions executing concurrently with respect to each other. While the first portion and second portion are executing, before the first portion accesses a memory location shared by the first portion and the second portion, a value stored in the memory location is captured and the first portion is delayed. While the second portion continues to execute the first portion is delayed. After a period of the first portion having been paused or slowed, the current content of the memory location is compared with the captured content to determine if there is a data collision. The first and second portions may be threads, and the capturing, delaying, and determining may be performed by code inserted to the application after it has been compiled.Type: ApplicationFiled: June 18, 2010Publication date: December 22, 2011Applicant: MICROSOFT CORPORATIONInventors: John Erickson, Madan Musuvathi
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Patent number: 8082464Abstract: Systems, methods and articles of manufacture are disclosed for managing availability of a component executing in a distributed system. The component may have an address space closed to the distributed system. In one embodiment, the component may be initiated. A state of the component may be analyzed to determine the availability of the component. The determined availability may be transmitted to the distributed system. The component may also be restarted responsive to a request from the distributed system to restart the component.Type: GrantFiled: October 13, 2009Date of Patent: December 20, 2011Assignee: International Business Machines CorporationInventors: Harish Deshmukh, Sridhar Rajagopalan, Roger C. Raphael, Chitrang Shah, Paul S. Taylor
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Patent number: 8078918Abstract: A storage subsystem is disclosed that maintains (a) statistics regarding errors detected via an ECC (error correction code) module of the storage subsystem; and/or (b) historical data regarding operating conditions experienced by the storage subsystem, such as temperature, altitude, humidity, shock, and/or input voltage level. The storage subsystem, and/or a host system to which the storage subsystem attaches, may analyze the stored data to assess a risk of a failure event such as an uncorrectable data error. The results of this analysis may be displayed via a user interface of the host system, and/or may be used to automatically take a precautionary action such as transmitting an alert message or changing a mode of operation of the storage subsystem.Type: GrantFiled: February 7, 2008Date of Patent: December 13, 2011Assignee: SiliconSystems, Inc.Inventors: Mark S. Diggs, David E. Merry, Jr.
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Patent number: 8078922Abstract: The present disclosure involves systems, software, and computer implemented methods for internal server error analysis. One process includes operations for identifying an internal server error associated with a particular type of error and returned by a web container. A counter of the number of internal server errors returned by the web container is incremented. The internal server error is also associated with an internal categorization of the particular type of internal server error, and the occurrence of the internal server error is added to a categorization entry generated based on the internal categorization of the error.Type: GrantFiled: September 30, 2009Date of Patent: December 13, 2011Assignee: SAP AGInventors: Diyan Yordanov, Violeta Georgieva, Polina Genova, Maria Jurova
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Patent number: 8074106Abstract: The present invention provides a storage system having a controller that can extend an old RAID group to a new RAID group without decreasing a processing speed. A conversion part reads the data from an unconverted area A1, converts it into the data based on a new RAID organization, and write it into a storage area A3 of the new RAID group. An address management part updates an initial address Ps and a last address Pe saved in a flash memory if the initial address Ps saved in the flash memory and the newest last address Pe of a converted area A2 are matched. When a power failure occurs, it is checked to see whether or not the data within the converted area A2 is correct. The conversion part reads the initial address Ps and the last address Pe from the flash memory to resume a conversion process.Type: GrantFiled: November 14, 2008Date of Patent: December 6, 2011Assignee: Hitachi, Ltd.Inventor: Yuko Matsui
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Publication number: 20110296249Abstract: There is provided a computer-implemented method for selecting from a plurality of full configurations of a storage system an operational configuration for executing an application. An exemplary method comprises obtaining application performance data for the application on each of a plurality of test configurations. The exemplary method also comprises obtaining benchmark performance data with respect to execution of a benchmark on the plurality of full configurations, one or more degraded configurations of the full configurations and the plurality of test configurations. The exemplary method additionally comprises estimating a metric for executing the application on each of the plurality of full configurations based on the application performance data and the benchmark performance data. The operational configuration may be selected from among the plurality full configurations based on the metric.Type: ApplicationFiled: May 26, 2010Publication date: December 1, 2011Inventors: Arif A. Merchant, Ludmila Cherkasova
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Patent number: 8069396Abstract: A storage device for refreshing pages of a flash memory comprises a flash memory, an ECC detector and a controller. The flash memory has a plurality of pages, and each page comprises a data area for storing data and a spare area for storing error correction code (ECC) corresponding to the data. The ECC detector is used to get the number of error bits of each page. The controller coupled to the ECC detector is used for storing data and ECC in a first page to a second page when a number of used bytes of the ECC stored in a spare area of the first page exceeds a first predetermined value. A number of used bytes of the ECC stored in a spare area of the second page is less than the first predetermined value. The second page is a blank page.Type: GrantFiled: August 25, 2008Date of Patent: November 29, 2011Assignee: Genesys Logic, Inc.Inventors: Ju-peng Chen, Chih-jung Lin
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Patent number: 8069384Abstract: An aspect of the present disclosure relates to scanning reassigned data storage locations. In one example, a reassignment table is accessed to identify a deallocated data storage location and scan the deallocated data storage location for media defects.Type: GrantFiled: June 8, 2009Date of Patent: November 29, 2011Assignee: Seagate Technology LLCInventors: Bo Wei, Patrick Tai Heng Wong, MingZhong Ding
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Publication number: 20110289349Abstract: Monitoring and repairing memory includes selecting a first memory bank comprising a plurality of memory cells to analyze. The plurality of memory cells are copied from the first memory bank to a second memory bank, wherein a request to access the first memory bank is redirected to the second memory bank. A determination is made whether the first memory bank comprises an error of the memory cell.Type: ApplicationFiled: May 24, 2010Publication date: November 24, 2011Applicant: Cisco Technology, Inc.Inventors: Matthias J. Loeser, Daniel V. Singletary, Sanjeev A. Joshi, Shadab Nazar
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Publication number: 20110289358Abstract: A method begins by a processing module identifying a plurality of dispersed storage networks (DSNs) for storing copies of dispersed storage encoded data based on global data retrieval accesses of the copies of the dispersed storage encoded data. The method continues with the processing module determining a set of error coding dispersal storage parameters for at least one of the plurality of DSNs based on local data retrieval accesses allocated to the at least one of the plurality of DSNs. The method continues with the processing module encoding data in accordance with the set of error coding dispersal storage parameters to produce a copy of the copies of the dispersed storage encoded data and outputting the copy of the copies of the dispersed storage encoded data to the at least one of the plurality of DSNs.Type: ApplicationFiled: May 11, 2011Publication date: November 24, 2011Applicant: CLEVERSAFE, INC.Inventors: Gary W. Grube, Timothy W. Markison
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Publication number: 20110289359Abstract: A method begins by a processing module determining access performance to copies of dispersed storage encoded data, wherein the copies of the dispersed storage encoded data are stored in a set of a plurality of dispersed storage networks (DSNs). The method continues with the processing module modifying the set of the plurality of DSNs based on the access performance and the desired access performance level to produce a modified set of the plurality of DSNs when the access performance is not at a desired access performance level. The method continues with the processing module, for a new DSN of the modified set of the plurality of DSNs, determining error coding dispersal storage parameters based on local data retrieval accesses allocated to the new DSN and facilitating the new DSN storing another copy of the dispersed storage encoded data.Type: ApplicationFiled: May 11, 2011Publication date: November 24, 2011Applicant: CLEVERSAFE, INC.Inventors: Jason K. Resch, Gary W. Grube, Timothy W. Markison
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Publication number: 20110283150Abstract: An objective is to allow a storage apparatus to accurately locate a failure site upon occurrence of a failure. Provided is a storage apparatus 10 including: a controller 11 that performs data input and data output into and from a storage drive 171 in response to a data input/output request sent from an external device 2; and expanders 112, 121 each having a switch circuit 1122 provided with a physical port (Phy 1121). In this storage apparatus 10, the controller 11 performs a loopback diagnosis on the expanders 112, 121, and performs a connection-based diagnosis on a target device by sending a connection frame thereto, the target device being a device detected as having a failure. When a response to the connection frame includes information indicating a failure, the controller 11 disables the physical port to which the target device is coupled, or the physical port of the switch circuit 1121 existing on a path from the controller 11 to the target device.Type: ApplicationFiled: May 12, 2010Publication date: November 17, 2011Applicant: HITACHI, LTD.Inventors: Yusuke Konishi, Hiroshi Izuta, Hiroyoshi Suzuki
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Patent number: 8060650Abstract: Described herein are exemplary storage network architectures and methods for diagnosing a path in a storage network. Devices and nodes in the storage network have ports. Port metrics for the ports may be ascertained and used to detect link problems in paths. In an exemplary described implementation, the following actions are effectuated in a storage network: ascertaining one or more port metrics for at least one device at a first time; ascertaining the one or more port metrics for the at least one device at a second time; analyzing the one or more port metrics from the first and second times; and determining if the analysis indicates a link problem in a path of the storage network.Type: GrantFiled: October 27, 2004Date of Patent: November 15, 2011Assignee: Hewlett-Packard Development Company, L.P.Inventors: Peter Jansz, Rajiv Kumar Grover, Krishna Babu Puttagunta
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Publication number: 20110276742Abstract: An approach is provided that uses a hypervisor to allocate a shared memory pool amongst a set of partitions (e.g., guest operating systems) being managed by the hypervisor. The hypervisor retrieves memory related metrics from shared data structures stored in a memory, with each of the shared data structures corresponding to a different one of the partitions. The memory related metrics correspond to a usage of the shared memory pool allocated to the corresponding partition. The hypervisor identifies a memory stress associated with each of the partitions with this identification based in part on the memory related metrics retrieved from the shared data structures. The hypervisor then reallocates the shared memory pool amongst the plurality of partitions based on the identified memory stress of the plurality of partitions.Type: ApplicationFiled: May 5, 2010Publication date: November 10, 2011Applicant: International Business Machines CorporationInventors: Vaijayanthimala K. Anand, Richard Louis Arndt, David Alan Hepkin, Sergio Reyes, Kenneth Charles Vossen
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Publication number: 20110276837Abstract: A method and system for verifying memory device integrity includes identifying at least one memory block corresponding to at least one memory location within a memory device. The memory block is associated with a portion of a file and a checksum representing data within the memory block at a first time. Based at least in part on determining that the memory block is mapped to the same portion of the same file at a second time, it is indicated that the checksum represents expected data within the memory block. A system for verifying memory device integrity is also disclosed.Type: ApplicationFiled: May 6, 2010Publication date: November 10, 2011Inventors: Timothy Steven Potter, Donald Becker, Bruce Montgomery, JR., Dave Dopson
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Patent number: 8055492Abstract: A design verification system that verifies the operation of multi-processor architecture by generating test programs in which the behavior of the processor, when executing the test program, is evaluated against the behavior required by the design specification. The test program generator produces scenarios for a multi-processor design in which non-unique results may occur. The system is provided with facilities to report expected outcomes, and to evaluate the validity of non-unique results in multiple resources under conditions of non-unique result propagation and dependencies among adjacent and non-adjacent resources.Type: GrantFiled: January 10, 2002Date of Patent: November 8, 2011Assignee: International Business Machines CorporationInventor: Allon Adir
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Patent number: 8055954Abstract: Storage systems and methods for distributed support ticket processing are disclosed. An exemplary method may include accessing at least one storage device in a storage system by an interface manager to retrieve raw support ticket data from the at least one storage device. The method may also include analyzing the raw support ticket data at the interface manager to generate a support ticket for the storage system. The method may also include decoding the support ticket to an intermediate format at a management station. The method may also include presenting the converted support ticket to a user at the management station.Type: GrantFiled: October 1, 2008Date of Patent: November 8, 2011Assignee: Hewlett-Packard Development Company, L.P.Inventors: Alexandre Lenart, Steven Maddocks, Richard Bickers
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Publication number: 20110271138Abstract: A system and a method for handling a system failure are disclosed. The method is adapted for an information handling system having a basic input and output system and a micro-controller. The method includes the following steps: sending, via the micro-controller, a signal; checking, via the micro-controller, whether an acknowledgement is received from the basic input and output system responsive to the signal; and scanning, via the micro-controller, a type of a system failure in response to the acknowledgement being not received.Type: ApplicationFiled: April 27, 2011Publication date: November 3, 2011Applicant: International Business Machines CorporationInventors: Ameha Aklilu, Hank CH Chung, Jeff HC Yu
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Patent number: 8051343Abstract: Example embodiments relate to a method and system of testing a memory module having the process of receiving single ended input signals via differential input terminals through which differential pairs of packet signals may be received from a testing equipment, wherein a number of terminals of the testing equipment may be different from a number of terminals of the memory module, and testing memory chips of the memory module based on the single ended input signals.Type: GrantFiled: October 22, 2010Date of Patent: November 1, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Seung-Man Shin, Byung-Se So, Seung-Jin Seo, You-Keun Han
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Patent number: 8051333Abstract: Upon occurrence of a memory error which is difficult to correct, CPU interrupts a process under execution in response to interrupt signal output from error detection device, and transfers the control to the OS. The OS references attributes of a page stored in a page frame which has suffered the memory error. When read-only is indicated, physical memory management table is updated to set the page frame, which has suffered the error, into a disabled state. Then, page table is updated such that a virtual page stored in the page frame which has suffered the error is not assigned to any page frame, followed by resumption of the execution of the process. After execution of the process is resumed, a page fault process is invoked to store the virtual page which has encountered the memory error in another normal page frame.Type: GrantFiled: February 8, 2008Date of Patent: November 1, 2011Assignee: NEC CorporationInventor: Akihito Kohiga
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Patent number: 8051337Abstract: A system and method for fast detection of cache memory hits in memory systems with error correction/detection capability is provided. A circuit for determining an in-cache status of a memory address comprises an error detect unit coupled to a cache memory, a comparison unit coupled to the cache memory, a results unit coupled to the comparison unit, and a selection unit coupled to the results unit and to the error detect unit. The error detect unit computes an indicator of errors present in data stored in the cache memory, wherein the data is related to the memory address. The comparison unit compares the data with a portion of the memory address, the results unit computes a set of possible in-cache statuses based on the comparison, and the selection unit selects the in-cache status from the set of possible in-cache statuses based on the indicator.Type: GrantFiled: November 13, 2009Date of Patent: November 1, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Yi-Tzu Chen
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Patent number: 8051220Abstract: A process control system is provided having a plurality of I/O devices in communication using a bus. A primary redundant I/O device and a secondary redundant I/O device are coupled to the bus, where the secondary redundant I/O device is programmed to detect a primary redundant I/O device fault. The secondary redundant I/O device, upon detecting the primary redundant I/O device fault, publishes a primary redundant I/O device fault message on the bus. The controller may deactivate the primary redundant I/O device and activate the secondary redundant I/O device responsive to the primary redundant I/O device fault message.Type: GrantFiled: December 23, 2009Date of Patent: November 1, 2011Assignee: Fisher-Rosemount Systems, Inc.Inventors: Michael D. Apel, Steven L. Dienstbier
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Patent number: 8051260Abstract: A method for safeguarding data stored in a memory of a data storage system includes monitoring values of a subset of environmental variables associated with the data-storage system and updating a portion of a table containing values of environmental variables associated with the data-storage system. The table includes values for environmental variables that are not in the subset of environmental variables monitored. The values of the environmental variables are then inspected. On the basis of the inspection, a condition in which there exists a high-risk of data loss is determined.Type: GrantFiled: June 30, 2004Date of Patent: November 1, 2011Assignee: EMC CorporationInventors: Steven T. McClure, Scott B. Gordon, Robert Decrescenzo, Timothy M. Johnson, Zhi-Gang Liu
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Publication number: 20110264963Abstract: A system for checking a program memory) of a processing unit includes a check module, and the processing unit is made up of an instruction counter connected to the check module. The check module has a register connected to a first changeover switch that sets the register content. In a system that allows for the instruction addresses of the entire program memory to be checked, the instruction counter contains an ancillary counter, which runs through the instruction address space of the program memory independently of the program code during normal operation and which is connected to the register.Type: ApplicationFiled: November 27, 2008Publication date: October 27, 2011Inventors: Jo Pletinckx, Hongyn Wang, Axel Wenzler, Markus Brockmann
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Publication number: 20110264950Abstract: A method begins by a processing module generating a payload section of a dispersed storage network (DSN) frame regarding a check request operation by generating one or more slice name fields of the payload section to include one or more slice names corresponding to one or more encoded data slices and generating a transaction number field of the payload section to include a transaction number corresponding to the check request operation. The method continues with the processing module generating a protocol header of the DSN frame by generating a payload length field of the protocol header to include a payload length that represents a length of the payload section and generating remaining fields of the protocol header.Type: ApplicationFiled: April 5, 2011Publication date: October 27, 2011Applicant: CLEVERSAFE, INC.Inventors: Andrew Baptist, Wesley Leggette, Jason K. Resch, Zachary J. Mark, Ilya Volvovski, Greg Dhuse