Abstract: Techniques are provided to trace packet descriptors. A received packet may be identified. A packet descriptor associated with the received packet may be created. A trace indicator in the packet descriptor may be set. The presence of a packet descriptor with the trace indicator set may be logged by a detector.

Abstract: In one aspect, a method includes receiving a request to access a virtual volume snapshot, preparing to bind the virtual volume snapshot, intercepting a command to prepare bind of the virtual volume snapshot, rolling back to a point in time corresponding to the requested virtual volume snapshot and generating a virtual volume snapshot in a storage array.

Abstract: System and method are disclosed for managing storage space of a magnetic storage device. The system may read data from a sector of the storage space and determine whether the data are successfully read from the sector. If it is determined that the data are not successfully read from the sector, the system may retrieve an address of the sector. The system may further determine whether the sector is subject to media fatigue based on the address. If it is determined that the sector is subject to media fatigue, the system may reallocate the sector subject to media fatigue to a spare sector.

Abstract: System and methods for selectively or automatically migrating resources between storage operation cells are provided. In accordance with one aspect of the invention, a management component within the storage operation system may monitor system operation and migrate components from storage operation cell to another to facilitate failover recovery, promote load balancing within the system and improve overall system performance as further described herein. Another aspect of the invention may involve performing certain predictive analyzes on system operation to reveal trends and tendencies within the system. Such information may be used as the basis for potentially migrating components from one storage operation cell to another to improve system performance and reduce or eliminate resource exhaustion or congestion conditions.

Abstract: In one embodiment, an encoder reads a set of data from memory cells to obtain retrieved data influenced by one or more distortion mechanisms as a result of having been stored. A quality metric is generated responsive to the retrieved data that changes in value responsive to differences between the user data and the associated retrieved data. A quality monitor establishes a relationship between a current value of the quality metric and a threshold value and monitors the relationship as being indicative of a degradation of the quality of the retrieved data, and selectively initiates an error response. In another embodiment, a correction value is iterated through a set of values as a quality metric is monitored such that the value of the quality metric which most closely approaches the value of the quality metric immediately subsequent to an initial writing of the data can be selected.

Abstract: Embodiments of systems and methods for archive verification are disclosed. More specifically, embodiments of this archive verification can comprise loading media into a drive and reading data from the media to verify that the media and data on the media can be read. In one embodiment, media can be loaded into a drive and read according to a verification policy. As part of verifying that media and data on media can be read, read errors or other verification data associated with media can be obtained. Using this verification data a result for the media may be determined.

Abstract: Embodiments are directed towards managing data storage that may experience a data failure. If a repair event is associated with a data storage failure, a new repair task may be generated and added to a task list. A priority value for each repair task in the task list may be determined based in part on the mean-time-to-data-loss (MTTDL) value associated with each repair task in the task list such that a lower MTTDL may indicate a higher priority value over a lower MTTDL. One or more repair tasks may be promoted to become active repair tasks based on the priority value the repair tasks such that the promoted repair tasks have a higher priority that than other repair tasks in the task list, if any. Each active repair task may be executed to repair one or more associated the storage failures.

Abstract: A method of determining vulnerability of a cache memory includes associating a first counter with a cache element and periodically incrementing the first counter. When a read or other access that consumes the data in the cache element occurs, a current value of the first counter is accumulated. When a write or other cache access that modifies data in the cache element occurs, the first counter is reset. At the end of an evaluation period, the value in a total counter approximates the number of clock cycles during which data that was consumed was vulnerable. Dividing this value by the number of clock cycles approximates the vulnerability of this cache element. The vulnerability for a subset of all cache elements may be measured and extrapolated to obtain an estimate for the vulnerability of the cache memory as a whole.

Abstract: An allocation method comprises: partitioning moderate memory into a plurality of physical memory pages having predetermined page size according to the predetermined page size; scanning the moderate memory using the predetermined page size and recording the physical address and damage degree of each physical memory page; obtaining the allocation information of the physical memory pages when a memory request is received and allocating physical memory to the request based on the recorded physical address and damage degree of each physical memory page and the obtained allocation information. A moderate memory is scanned and the physical address and damage degree of each physical memory page are recorded, then the physical memory is allocated based on the recorded physical address and damage degree of each physical memory page and the obtained allocation information.

Abstract: The method includes receiving a command at a first storage system of a block storage cluster. The command is transmitted by the initiator system to the first storage system via a network and includes a request for data. The method further includes transferring the stored data from the first storage system to the initiator system via the network when data requested in the data request is stored by the first storage system. The method further includes transmitting a referral response from the first storage system to the initiator system when a portion of the data requested in the data request is not stored by the first storage system, but is stored by a second storage. system of the block storage cluster.

Abstract: The relative health of data storage drives may be determined based, at least in some aspects, on data access information and/or other drive operation information. In some examples, upon receiving the operation information from a computing device, a health level of a drive may be determined. The health level determination may be based at least in part on operating information received from a client entity. Additionally, a storage space allocation instruction or operation may be determined for execution. The allocation instruction or operation determined to be performed may be based at least in part on the determined health level.

Abstract: Systems, methods, and computer storage mediums are provided for mitigating damage to data caused by a computer process having a corrupted pointer. An exemplary method includes receiving a pointer to a memory address. The pointer is received in conjunction with a command of the computer process to access data stored at the memory address, where the data is intended to be stored in a memory segment that allows for read-only access. The memory segment that includes the memory address is analyzed to determine a modification state for the memory segment, where the modification state indicates the type of access that the memory segment allows. The computer process is halted when the modification state indicates that the memory segment allows for other than read-only access.

Abstract: A computer program product is provided for performing input/output (I/O) processing. The computer program product is configured to perform: generating and storing in local channel memory at least one address control word (ACW) specifying one or more host memory locations for data transfer and including a data discard field; generating an address control structure specifying a local channel memory location of a corresponding ACW; receiving one or more data transfer requests from a network interface that each corresponding address control structure information; accessing an ACW and routing the data transfer request to a host memory location specified in the ACW; and responsive to encountering an error during at least one of the accessing and the routing, discarding the one or more data transfer requests and setting the data discard field to a value configured to instruct a channel to discard any subsequent data transfer requests associated with the ACW.

Abstract: A maintenance operation instance collection apparatus includes: a storage unit that includes a maintenance operation instance database in which operation information obtained from a device via a sensor and maintenance information on a measure to deal with the operation information corresponding thereto are stored in association with each other; and a control unit that receives an input of new operation information, receives an input of new maintenance information, searches the maintenance operation instance database using the newly-received maintenance information as a search key, acquires searched operation information, compares the newly-received operation information to the acquired operation information, determines whether or not the newly-received operation information is close to the acquired operation information in such a degree of satisfying a prescribed criterion, and, if the newly-received operation information is not determined to be close to the acquired operation information, prompts a re-input

Abstract: An integrated circuit including a first interface, a decoder, and a controller. The first interface is configured to (i) write encoded data in a portion of a flash memory, and (ii) read the encoded data back from the flash memory. The decoder is configured to (i) according to an error correction code, decode the encoded data read back from the flash memory, and (ii) based on the decoded data, determine a number of decoding errors corresponding to the decoded data. The controller is configured to, in response to the number of decoding errors being greater than or equal to a first threshold, cease accessing the portion of the flash memory. The first threshold is less than a number of errors correctable by the error correction code for the portion of the flash memory.

Abstract: An apparatus can include a circuit board; a processor mounted to the circuit board; a storage subsystem accessible by the processor; random access memory accessible by the processor; a network interface; and a controller mounted to the circuit board and operatively coupled to the network interface where the controller includes circuitry to capture values stored in the random access memory, the values being associated with a state of the apparatus, and circuitry to transmit the values via the network interface. Various other apparatuses, systems, methods, etc., are also disclosed.

Abstract: A memory subsystem includes a test signal generator of a memory controller that generates a test data signal in response to the memory controller receiving a test transaction. The test transaction indicates one or more I/O operations to perform on an associated memory device. The test signal generator can generate data signals from various different pattern generators. The memory controller scheduler schedules the test data signal pattern, and sends it to the memory device. The memory device can then execute I/O operation(s) to implement the test transaction. The memory controller can read back data written to a specific address of the memory device and compare the read back data with expected data. When the read back data and the expected data do not match, the memory controller can record an error. The error can include the specific address of the error, the specific data, and/or encoded data.

Abstract: Disclosed is a non-mounted storage test device based on FPGA, which comprises a processor unit for performing enumeration and configuration for device, creating a scenario for test and performing test; a device driver unit for managing storage device; a data engine unit for generating pattern data for test and performing test; a system memory interface unit for receiving data for test and storing test result; a monitoring unit for monitoring packet; a DMA driver/address translation unit for performing DMA operation and transmitting Memory Read Request to Root Complex; a message input/output unit for transmitting to the data engine unit and the device driver unit; a switch unit for constituting DUT unit; a storage-in DUT unit as device under test which is storage for direct interface to PCIe including HBA; and a memory unit for storing data for test and record generated between tasks.

Abstract: Approaches for a packet format for error reporting in a content addressable memory (CAM) device are disclosed. The CAM device may comprise a CAM array that includes a plurality of rows, each row including a plurality of CAM cells coupled to a match line, and an error notification circuit capable of forming a packet that indicates whether the CAM device is experiencing an error condition. If an error condition was experienced by the CAM device, the response packet may also indicate the type(s) of error that was encountered. Advantageously, information about any error condition experienced by the CAM device may be quickly ascertained by a host device in which the CAM device is incorporated.

Abstract: A data storage device includes a memory and a controller coupled to the non-volatile memory. The controller is coupled to a communication interface that is configured to enable communication with a host device. The controller is configured to send a signal via a first connection of the communication interface and to send a corresponding clock signal via a second connection of the communication interface. The signal is compliant with a communication protocol that specifies that the first connection of the communication interface carries the signal while the second connection of the communication interface carries the clock signal. The first connection is testable to measure the signal to generate data indicating transitions of the signal. The data excludes measurements of the clock signal. The data is analyzable to detect an indication defined by the communication protocol and to determine an estimated bit sequence of the signal.

Abstract: According to one embodiment, a memory system includes a first memory, a second memory, and a control unit. The first memory includes a volatile first register retaining a first operation parameter. The control unit performs a first operation of retaining the first operation parameter in the second memory. Then, the control unit turns OFF the first memory while retaining the first operation parameter in the second memory when an operation mode is switched from a first mode to a power saving second mode. Then, the control unit performs a second operation of turning on the first memory, and transferring the first operation parameter retained in the second memory to the first register when the operation mode is switched from the second mode to the first mode.

Abstract: A disk control apparatus includes a processor, and a memory coupled to the processor in which executes a process as follows. The process includes diagnosing whether or not a failure has occurred on each of a plurality of disk apparatuses, determining, when the failure has occurred, whether or not the failure is a pre-defined failure, and excluding from diagnosis targets, when the failure is the pre-defined failure, a disk apparatus group included in a RAID together with a failed disk apparatus that is determined to have the pre-defined failure in the plurality of disk apparatuses.

Abstract: In a method for testing a storage system, each disk of a storage system is numbered, and a disk of a number is selected as a root node of a binary tree. A probability that the nodes of each level of the binary tree is completely added into the binary tree is computed according to a predefined algorithm, and the nodes of each level of the binary tree are added into the binary tree according to the computed probability. And each disk is tested when the disk is added into the binary tree as the node of the binary tree.

Abstract: A computing core includes a processing module, main memory, and a memory controller. The memory controller receives a request to fetch an instruction from the processing module and determines whether the instruction is currently stored in the main memory. When the instruction is not currently stored in the main memory, the memory controller determines whether the instruction is stored in a distributed storage network (DSN) memory as one or more sets of encoded instruction slices; and, when it is, the memory controller addresses the DSN memory to retrieve the one or more sets of encoded instruction slices. When at least a threshold number of encoded instruction slices are retrieved for each of the one or more sets of encoded instruction slices, the one or more sets of encoded instruction slices are decoded using a dispersed storage error coding function to reconstruct the instruction, which is provided to the processing module.

Abstract: In a testing device, a method for implementing distributed pin mapping. The method includes receiving a request from a plurality of CPUs to access a pin map memory at each of a plurality of bridges, implementing accesses to the pin map memories locally at each of the plurality of bridges, and using pin map data from the accesses to the plurality of CPUs to enable access to testing device resources.

Abstract: A method and system for testing a memory is provided in the present invention. The method includes the following steps. Each of at least one address bit to be tested of the memory is set to a fixed value. Current test data is written into memory unit(s) of the memory which the set address bit(s) correspond(s) to. Current read back data is read from the memory unit(s) which the set address bit(s) correspond(s) to. The current test data is compared with the current read back data. It is judged whether there is any signal integrity problem in unset address bit(s) of the memory according to the comparison result of the current test data and the current read back data, in order to determine fault address bit(s). The method and system for testing a memory provided by the present invention may determine fault address bit(s) of the memory simply and quickly.

Abstract: A CPU changes the operating mode to a test mode in which the CPU does not terminate a program being executed even if an MMU outputs a CPU exception notification, outputs an address signal for causing the MMU to output a CPU exception notification to the MMU in the test mode, and detects whether or not a CPU exception notification is input after the address signal is output to the MMU. This allows inspection as to whether or not a fault that prevents detection of an illegal access has occurred in the MMU while executing another program.

Abstract: This document generally describes systems, devices, methods, and techniques for obtaining debug information from a memory device. Debug information can include a variety of information associated with a memory device that can be used for debugging the device, such as a sequence of operations performed by the memory device and information regarding errors that have occurred (e.g., type of error, component of memory device associated with error). A memory device can be instructed by a host to obtain and provide debug information to the host. A memory device can be configured to obtain particular debug information using a variety of features, such as triggers. For instance, a memory device can use a trigger to collect debug information related to failed erase operations.

Abstract: A method or apparatus detects a memory corruption of at least one portion of memory during run-time and corrects the memory corruption of the at least one portion of memory by replacing the at least one portion of memory with a backup of the at least one portion of memory. In this way, memory corruption can be corrected in a timely fashion while minimizing security risks.

Abstract: A method includes a DSN access token module retrieving one or more sets of at least a threshold number of dispersed storage (DS) error coding function slices from the DSN memory via the computing device. The method continues with the computing device and/or the DSN access token module decoding the one or more sets of the at least a threshold number of DS error coding function slices using a default DS error coding function to recapture a DS error coding function. The method continues with the computing device and/or the DSN access token module generating a plurality of sets of data access requests in accordance with the DS error coding function. The method continues with the computing device sending the plurality of sets of data access requests to the DSN memory.

Abstract: A buffer integrated circuit device. The device comprising an output driver formed on the substrate member, the output driver having at least a command bus and an address bus. The device has a protocol and parity checking block (“Block”). The device has a table configured in the block. The table is programmable with a plurality of timing parameters. The device has a memory state block coupled to the table and a command history table coupled to the table to process protocol information for all commands that pass through the Block. The buffer integrated circuit device utilizes the protocol checking functionality to prevent failure propagation and enables data protection even in the case of host memory controller failure or system-level failure of any signal or signals on the command, control and address bus from the host memory controller to the buffer integrated device.

Abstract: A method that determines the system impact of single event upset (SEU) and a single event upset (SEU) wrapper that controls a SEU controller is disclosed. The method injects faults into a component (e.g. FPGA, ASIC) of an operational system that is carrying live traffic and monitors the system's response to the faults to determine the impact of SEU on the system. The SEU wrapper sends the SEU controller a pattern scheme that includes information indicating when, where, how often, and/or how long to inject bursts of one or more faults into memory of the component of the system. A burst of faults contains faults that are consecutively injected into the array of memory blocks. After each fault in a burst is injected, one or more errors in one or more memory elements are detected and/or corrected. Information regarding the detection and/or the correction of an error is updated using registers that store counters. After injecting a burst of faults, the SEU controller waits for a predetermined amount of time.

Abstract: A computer booting method is provided for a computer system. The method comprises performing a power-on-self test. When the test result shows no error on the BIOS, a booting procedure is executed. When the test result shows the BIOS is damaged, whether the computer system stores a backup file of the BIOS is determined. When the computer system stores the backup file, the central processing unit reads the data of backup file and write it into a BIOS system memory and a reboot process is performed. When there is no backup file in the computer system, the computer system is connected to an internet server and downloads a BIOS backup file to the system main memory from the internet server. The central processing unit reads the BIOS backup file and write it into the BIOS system memory and a reboot process is formed.

Abstract: A maintenance free storage container includes a plurality of storage servers, wherein the maintenance free storage container allows for multiple storage servers of the plurality of storage servers to be in a failure mode without replacement. The maintenance free storage container further includes a container controller operable to manage failure mode information of the plurality of storage servers, manage mapping of a plurality of virtual storage servers to at least some of the plurality of storage servers based on the failure mode information, communicate storage server access requests with a device external to the maintenance free storage container using addressing of the plurality of virtual storage servers, and communicate the storage server access requests within the maintenance free storage container using addressing of the plurality of storage servers.

Abstract: Determining port failover information is described. First information is determined by a first storage processor executing first code for performing port matching. The first information identifies a first set of port pairs. Each port pair includes a first port of the first or second storage processor and a second port of the first or second storage processor. Each port pair denotes the first port as protecting the second port. Upon failure or unavailability of the second port, the first port virtualizes the second port and requests directed to the second port are redirected to the first port. Similarly, second information is determined by the second storage processor executing second code for performing the port matching. Port failover processing is performed upon failure or unavailability of port(s) of the first storage processor and/or the second storage processor. Port failover processing uses the first information and/or the second information.

Abstract: A memory dump method includes performing information processing using a first partition including a first device board and a second device, detecting an error in the first device, after detecting the error, performing information processing using a second partition including a third device, after detecting the error, performing a memory dump on each of the first device and the second device to obtain dump data, and after the memory dump is performed, adding the second device to the second partition.

Abstract: A method begins by a processing module detecting a potential dispersed storage network (DSN) protocol issue that effects access of dispersed storage error encoded data within a DSN. The method continues with the processing module identifying a DSN entity based on the DSN protocol issue and generating a DSN protocol inquiry frame. The method continues with the processing module transmitting the DSN protocol inquiry frame to the DSN entity. The method continues with the processing module receiving a DSN protocol response frame from the DSN entity and resolving the DSN protocol issue based on the DSN protocol response frame.

Abstract: A method of sampling sensor data from a computing system is presented. The computing system includes a plurality of components and a sensor network for monitoring the computing system. The sensor network includes primary sensor nodes operable to obtain primary parameter data from a measurement of a primary parameter of the components, and secondary sensor nodes operable to obtain secondary parameter data from a measurement of secondary parameters of the components. The method includes: a) obtaining secondary parameter data from secondary sensor nodes relating to components; b) processing, in a computing device, the secondary parameter data; c) determining, based upon determined or pre-determined relationships between the secondary parameters and the primary parameter, a sample rate for the primary parameter data for the components; and d) obtaining primary parameter data from the primary sensor nodes relating to components at the determined sample rate.

Abstract: A plug-in card storage device includes a plug-in card including a memory to store received input data and an error correction circuit to be equipped electrically connectable to the memory and to correct an error in the input data outputted from the memory; a device main body to have the plug-in card implemented therein; and a processor to determine whether or not to activate the error correction circuit, by calculating a reliability index value of the plug-in card based on an error rate of the memory provided in the plug-in card implemented in the device main body, so as to approximate the reliability index value to a reference value.

Abstract: Embodiments are directed towards a controller that provides individual network accessibility to a storage drive. The controller may include a first connector operative to couple with a storage-drive connector, a second connector operative to couple with a backplane connector of a multi-storage-drive chassis, memory, and processor. The controller may convert communication received through the first connector into an Ethernet protocol for output through the second connector, and convert communication received through the second connector into a storage-drive protocol for output through the first connector. A physical shape of the controller may fit adjacent to the storage-drive connector and occupy less space than is bounded by peripheral edges of an end of a separate housing of a storage drive coupled to the storage-drive connector. The controller may manage power provided to the storage drive and may coordinate with other controllers to manage power-up sequences of multiple storage drives.

Abstract: A semiconductor device includes a first memory region including a plurality of memory cells; a test unit configured to test the first memory region, and detect a weak bit from among the plurality of memory cells; and a second memory region configured to store a weak bit address (WBA) of the first memory region, and data intended to be stored in the weak bit, wherein the first memory region and the second memory region include different types of memory cells.

Abstract: A cache coherency controller, a system comprising such, and a method of its operation are disclosed. The coherency controller ensures that target-side security checking rules are not violated by the performance-improving processes commonly used in coherency controllers such as dropping, merging, invalidating, forwarding, and snooping. This is done by ensuring that requests marked for target-side security checking and any other requests to overlapping addresses are forwarded directly to the target-side security filter without modification or side effects.

Abstract: Apparatus and methods, such as those that read data from non-volatile integrated circuit memory devices, such as NAND flash. For example, disclosed techniques can be embodied in a device driver of an operating system. Errors are tracked during read operations. If sufficient errors are observed during read operations, the block is then retired when it is requested to be erased or a page of the block is to be written. One embodiment is a technique to recover data from uncorrectable errors. For example, a read mode can be changed to a more reliable read mode to attempt to recover data. One embodiment further returns data from the memory device regardless of whether the data was correctable by decoding of error correction code data or not.

Abstract: The present invention is related to systems and methods for harmonizing testing and using a storage media. As an example, a data system is set forth that includes: a data decoder circuit, a data processing circuit, and a write circuit. The data decoder circuit is configured to decode a test data set to yield a result. The data processing circuit is configured to encode a user data set guided by the result to yield a codeword. The write circuit is configured to store an information set corresponding to the codeword to a storage medium.

Abstract: Embodiments of an invention for protecting information processing system secrets from debug attacks are disclosed. In one embodiment, a processor includes storage, a debug unit, and a test access port. The debug unit is to receive a policy from a debug aggregator. The policy is based on a value of a first fuse and has a production mode corresponding to a production value of the first fuse and a debug mode corresponding to a debug value of the fuse. The test access port is to provide access to the storage using a debug command in the debug mode and to prevent access to the storage using the debug command in the production mode.

Abstract: A data storage device comprises storage media and a controller. The storage media may comprise a plurality of media defects, at least some of the media defects being listed in a grown defect list and a primary defect list comprising a plurality of entries sorted in an order according to physical address locations. The controller may be configured to generate a push down list from the primary defect list and the grown defect list by populating the push down list with entries from the primary defect list such that the push down list entries maintain the order; translating each entry in the grown defect list to a physical address location; and inserting each translated physical address location with updated push down count into the push down list.

Abstract: The subject disclosure relates to analyzing memory allocations for one or more computer-implemented processes. In particular, in conjunction with employing tags for tracking memory allocation commands, currently allocated memory can be examined for various characteristics of inefficient memory use. For example, as memory is initially allocated, a predetermined bit pattern can be written to the newly allocated memory. Thus, detection of the predetermined bit pattern can be indicative of wasted memory use. Moreover, additional features can be provided to both analyze data and present views associated with that analysis relating to identification of memory fragmentation, over-allocation, sparse memory use, duplication of allocations, multiple module loads, and so forth.

Abstract: A tape drive for exchanging data with a tape cartridge, which has tape media and auxiliary memory that is not tape media, is operable, in response to a boot request from a computer apparatus that is bootable from a kind of initial program load device that is not a tape drive, to read boot data stored on the auxiliary memory and to output the boot data for booting the computer apparatus.

Abstract: A method begins by a dispersed storage (DS) processing module of a DS unit selecting a data slice for corruption analysis and requesting integrity information for the data slice from one or more other DS units of a dispersed storage network. When the one or more requested integrity information is received, the method continues with the DS processing module analyzing the one or more received integrity information and local integrity information of the data slice stored in the DS unit. When the analysis of the one or more received integrity information and the local integrity information of the data slice is unfavorable, the method continues with the DS processing module identifying the data slice as being corrupted.

Abstract: The method includes receiving a command at a first storage system of a block storage cluster. The command is transmitted by the initiator system to the first storage system via a network and includes a request for data. The method further includes transferring the stored data from the first storage system to the initiator system via the network when data requested in the data request is stored by the first storage system. The method further includes transmitting a referral response from the first storage system to the initiator system when a portion of the data requested in the data request is not stored by the first storage system, but is stored by a second storage. system of the block storage cluster.