Abstract: Embodiments of the present invention provide a method for monitoring components in a library by tracking the movement of library components. By tracking the movement of library components, the degradation of library components can be monitored and the reliability of library components determined, allowing unreliable components to be bypassed or replaced, enhancing the reliability of the library and preventing data loss.

Abstract: Systems and methods which provide mount catalogs to facilitate rapid volume mount are shown. A mount catalog of embodiments may be provided for each aggregate containing volumes to be mounted by a takeover node of a storage system. The mount catalog may comprise a direct storage level, such as a DBN level, based mount catalog. Such mount catalogs may be maintained in a reserved portion of the storage devices containing a corresponding aggregate and volumes, wherein the storage device reserved portion is known to a takeover node. In operation according to embodiments, a HA pair takeover node uses a mount catalog to access the blocks used to mount volumes of a HA pair partner node prior to a final determination that the partner node is in fact a failed node and prior to onlining the aggregate containing the volumes.

Abstract: The present invention systems and methods enable configuration of functional components in integrated circuits. A present invention system and method can flexibly change the operational characteristics of functional components in an integrated circuit die based upon a variety of factors, including if the die has a defective component. An indication of the defective functional component identification is received. A determination is made if the defective functional component is one of a plurality of similar functional components that can provide the same functionality. The other similar components can be examined to determine if they are parallel components to the defective functional component. The defective functional component is disabled if it is one of the plurality of similar functional components and another component can handle the workflow that would otherwise be assigned to the defective component. Workflow is diverted from the disabled component to other similar functional components.

Abstract: A non-volatile solid state memory device and method for balancing write/erase cycles among blocks to level block usage. The non-volatile solid state memory device includes a memory unit having data stored therein and a controller with logic for programming the memory unit according to a monitored occurrence of an error during a read operation. The method includes monitoring an occurrence of an error during a read operation in a memory unit of the device and programming the memory unit according to the monitored occurrence of the error.

Abstract: In a storage system, when a recovered error occurred upon access to a storage apparatus, a data redundancy determination unit determines whether data to be accessed has redundancy. When the data is determined to have no redundancy, an anomaly-occurring portion determination unit determines that the storage apparatus is not an anomaly-occurring portion and at the same time, an error history determination unit determines whether a recovered error occurred at the time of the past access to the storage apparatus other than that of the access destination. The anomaly-occurring portion determination unit determines whether a common transmission path is the anomaly-occurring portion based on the determination result of the error history determination unit.

Abstract: Methods and structure for enabling re-training of a DDR memory controller in a storage device without loss of data in the DDR memory devices of the cache memory in response to detecting failure of the memory subsystem during operation of the storage device. In response to detecting a failure of the memory subsystem, the memory controller is reset without resetting the memory devices. The memory controller is then re-trained for operation with the memory device. During the re-training, self-refresh mode of the memory devices is disabled and manual refresh is performed by a processor of the storage device to thereby retain any user data in the memory device.

Abstract: A mechanism of monitoring activity on a computer which may be applied to measuring the performance of the computer. The computer is configured to track a first set of information relating to at least a first occurrence of at least one scenario on the computer. At least some of the first set of information is evaluated to make a determination about the first occurrence of the scenario. Based on that determination, the computer may be configured to track a second set of information relating to at least a second occurrence of the scenario on the computer, in which the second set of information includes at least some types of information not tracked in the first set of information. The second set of information can then be evaluated.

Abstract: A semiconductor memory apparatus including a test circuit configured for generating compressed data by comparing and compressing data stored in a plurality of memory cells inside a memory bank during a first test mode, and configured for outputting the compressed data as test data to an input/output pad through one selected global line during the first test mode, and the test circuit is configured for transmitting the compressed data to a plurality of global lines during a second test mode, combining the compressed data loaded in the respective global lines during the second test mode, and outputting the combination result as the test data to the input/output pad during the second test mode.

Abstract: In one embodiment, an encoder reads a set of data from memory cells to obtain retrieved data influenced by one or more distortion mechanisms as a result of having been stored. A quality metric is generated responsive to the retrieved data that changes in value responsive to differences between the user data and the associated retrieved data. A quality monitor establishes a relationship between a current value of the quality metric and a threshold value and monitors the relationship as being indicative of a degradation of the quality of the retrieved data, and selectively initiates an error response. In another embodiment, a correction value is iterated through a set of values as a quality metric is monitored such that the value of the quality metric which most closely approaches the value of the quality metric immediately subsequent to an initial writing of the data can be selected.

Abstract: A computing system stores actual memory usage data in a user memory space. The actual memory usage data represents memory usage of a plurality of device drivers that are loaded by a first kernel. The computing system generates an estimate of memory space to be reserved for a second kernel based on the actual memory usage data for the plurality of device drivers that are loaded by the first kernel and reserves memory space for the second kernel using the estimate.

Abstract: To produce a memory which resists ion or photon attack, a memory structure is chosen whose memory point behaves asymmetrically with regard to these attacks. It is shown that in this case, it is sufficient to have a reference cell for an identical and periodic storage structure in order to be able to correct all the memory cells assailed by an attack. An error correction efficiency of ½ is thus obtained, with a simple redundancy, whereas the conventional methods make provision, for the same result, to triple the storage, to obtain a less beneficial efficiency of ?.

Abstract: An information processing device includes a plurality of memories, and a processor coupled to the plurality of memories and configured to carry out a first test to determine whether a first error is detected when first and second memories of the plurality of memories are concurrently operated, and when the first error is detected from the first test, carry out a second test to determine whether a second error is detected when the first and second memories are separately operated.

Abstract: Embodiments of the invention relate to calculation of error rate for data storage which includes determining a completion status of a read operation of data stored in a storage device, the completion status being one of at least partially complete or not complete. The fault monitoring count is incremented based on the completion status being not complete. The fault monitoring count is decreased based on the completion status being at least partially complete. The fault monitoring count being decreased according to a value based on the number of bytes successfully read. The error rate indicator value is being calculated based on an exponential decay rate related to the number of bytes read. The fault monitoring count threshold is monitored every time the fault monitoring count is incremented and the storage device is identified as faulty once the threshold limit is exceeded.

Abstract: An apparatus for monitoring changes to a block of data is disclosed. A first hardware watchpoint is set to monitor changes to the block of data at a current location of the block of data in memory and a second hardware watchpoint is set to monitor changes at a selected location in the memory where a reference to the block of data is located. Responsive to the second hardware watchpoint being triggered by a change at the selected location where the reference to the block of data is located, a new location of the block of data in the memory is identified based on the change that triggered the second hardware watchpoint. Subsequent to identifying the new location of the block of data, the first hardware watchpoint is reset to monitor changes to the block of data at the new location of the block of data.

Abstract: According to one embodiment, a semiconductor storage device includes a memory cell array, a plurality of first latch circuits, a first register and a comparator. The memory cell array has a plurality of memory cells associated with columns. The first latch circuits are provided corresponding to the respective columns, and each of the first latch circuits holds data on whether or not the corresponding column has a failure. The first register holds the number of columns for redundancy. The comparator compares the number of the first latch circuits holding the data that the corresponding columns have failures with a criterion based on the data held by the first register. The semiconductor storage device determines whether or not there is a failure in the first latch circuit, based on the result of the comparison by the comparator.

Abstract: A method and system is used in managing drive error information. An error is detected in connection with a drive. Error data associated with the drive error is collected in response to detecting the error. The error data is stored on the drive. The error data being sufficiently complete to allow a comprehensive evaluation of the error.

Abstract: A method and apparatus for monitoring changes to a block of data is disclosed. A computer sets a first hardware watchpoint to monitor changes to the block of data at a current location of the block of data in memory and a second hardware watchpoint to monitor changes at a selected location in the memory where a reference to the block of data is located. Responsive to the second hardware watchpoint being triggered by a change at the selected location where the reference to the block of data is located, the computer identifies a new location of the block of data in the memory based on the change that triggered the second hardware watchpoint. Subsequent to identifying the new location of the block of data, the computer then resets the first hardware watchpoint to monitor changes to the block of data at the new location of the block of data.

Abstract: Embodiments of systems and methods for archive verification are disclosed. More specifically, embodiments of this archive verification can comprise loading media into a drive and reading data from the media to verify that the media and data on the media can be read. In one embodiment, media can be loaded into a drive and read according to a verification policy. As part of verifying that media and data on media can be read, read errors or other verification data associated with media can be obtained. Using this verification data a result for the media may be determined.

Abstract: Some embodiments include apparatuses and methods having a first interface to communicate with a processing unit, a second interface to communicate with a memory device, and a module coupled to the first and second interfaces. In at least one of the embodiments, the module can be configured to obtain information stored in the memory device and perform at least one of testing and repairing of a memory structure of the memory device based at least in part on the information.

Abstract: In a self-diagnosing method of a volatile memory device, a processor outputs a self-refresh entrance command and enters a power save mode, and a volatile memory device performs a self-diagnosing operation for a plurality of memory cells in response to the self-refresh entrance command while the processor is in the power save mode.

Abstract: A method for memory space management in a multitasking capable data processing system including a data processing device and software running thereon. The data processing device includes at least one central processing unit (CPU) and at least one user memory, and the software running on the CPU includes a first computer program application and at least a second computer program application which respectively jointly access the user memory used by both computer program applications during execution. Information of the first computer program application is stored in at least a portion of the memory space of the user memory in a temporary manner, and the integrity of the contents memory space is checked after interrupting the execution of the first computer program application. The first computer program application is only executed further when the memory integrity is confirmed through the checking or when the memory integrity has been reestablished.

Abstract: Methods, apparatuses and systems are disclosed involving a memory device. In one embodiment, a memory device is disclosed that includes a command error module of the memory device operably coupled to at least one of a command signal and an address signal and configured to detect and report a parity error on the command signal, the address signal, or combinations thereof. In some embodiments, a memory device may include a temperature sensor operably coupled to a mode register. The temperature sensor may be configured to sense a device temperature and report a temperature status. Furthermore, the memory device may be incorporated into a memory module, which may be included in an electronic system.

Abstract: Embodiments of the present invention provide a method for monitoring components in a library by tracking the movement of library components. By tracking the movement of library components, the degradation of library components can be monitored and the reliability of library components determined, allowing unreliable components to be bypassed or replaced, enhancing the reliability of the library and preventing data loss.

Abstract: In one embodiment, a method for managing DDM failures includes analyzing, using a hardware processor, information stored in a data repository and relating to DDM failures to identify problems in an installed base of DDM, the analysis comprising analyzing comparative DDM failure data.

Abstract: A storage integrity system in a dispersed storage network scans an address range of data slices to identify errors in one of a plurality of encoded data slices, wherein the plurality of encoded data slices are generated from a data segment using an error encoding dispersal function. When the storage integrity system detects an error, it identifies one of the encoded data slices for rebuilding. The identified data slice is rebuilt in response to the type of error. For example, when the type of the error includes a temporary error, the storage integrity system waits a predetermined time period to determine whether the error still exists prior to rebuilding the identified data slice.

Abstract: Methods, systems, and computer readable media for early detection of potential flash failures using an adaptive system level algorithm based on NAND program verify are disclosed. According to one aspect, a method for early detection of potential flash failures using an adaptive system level algorithm based on NAND program verify includes performing a program verify operation after a write to a non-volatile memory, where the program verify mechanism reports a pass or fail based on an existing measurement threshold value, and dynamically adjusting the measurement threshold value used by subsequent program verify operations based on the results of previous program verify operations.

Abstract: Various embodiments are described herein. Some embodiments include an Operating System and a platform. The platform includes a processor having an error register. The Operating System can write to the error register only via the platform in a secure manner (for example, using platform firmware). Other embodiments are described and claimed.

Abstract: A memory system includes a nonvolatile memory device and a memory controller configured to control the nonvolatile memory device and configured to provide the nonvolatile memory device with error flag information including error location information of an error of data read from the nonvolatile memory device.

Abstract: Embodiments include a method and system of dynamically allocatable memory error mitigation. In one embodiment, a system applies an error mitigation mechanism to one of multiple groups of memory units, wherein the one group is in active use during an error test of a second group of memory units. The system deactivates and tests the second group of memory units for errors. In response to detecting an error in a memory unit of the second group, the system applies, to the memory unit of the second group having the error, the error mitigation mechanism for active use. The system then activates the second group of memory units with the error mitigation mechanism applied to the memory unit of the second group having the error.

Abstract: The method includes receiving a command at a first storage system of a block storage cluster. The command is transmitted by the initiator system to the first storage system via a network and includes a request for data. The method further includes transferring the stored data from the first storage system to the initiator system via the network when data requested in the data request is stored by the first storage system. The method further includes transmitting a referral response from the first storage system to the initiator system when a portion of the data requested in the data request is not stored by the first storage system, but is stored by a second storage. system of the block storage cluster.

Abstract: A memory error management system connected to memory channels for managing errors detected in corresponding memory devices includes a reporting table including a list of historically reported errors, a binary value representing the current error status of the memory channels, a uniqueness check module for checking whether a historically reported error is reappearing as a current error, an error mask register for generating a masked binary value representing unique current errors in the memory channels, and a channel arbitration module for decoding the channel identifiers of corrupted memory channels from the masked binary value and storing the decoded channel identifiers into the reporting table.

Abstract: Subject matter disclosed herein relates to on-the-fly remapping a memory device by hardware-switching data paths to locations of the memory device.

Abstract: A method of controlling data transfers between a volatile memory and a non-volatile storage, the volatile memory being on a memory device operatively coupled to a computer system, the data transfers comprising: storing data from the volatile memory to the non-volatile storage when a power source of the computer system fails, the method comprising following re-establishment of the previously failed power source, the step of: selectively restoring data from the non-volatile storage to the volatile memory by a controller software after restart operations.

Abstract: In a method for detecting memory errors occurring in a computing device, a channel number of an error memory module is obtained from a first register of a memory controller of the computing device. The method analyzes an error type to obtain a rank number of the memory module from one or more specified registers of the memory controller, and finds a serial number of a memory slot into which the memory module has been inserted. According to the serial number of the memory slot and a distribution list, the method can detect the memory slot which is carrying the memory module.

Abstract: Provided is a test apparatus including: an address generator that generates an address of a memory under test; a selector that selects whether to perform bit inversion on the address generated by the address generator before supplying the address to the memory under test; an inversion processing section that outputs the address generated by the address generator after performing bit inversion on the address if the selector has selected in the affirmative, and outputs the address generated by the address generator without performing any bit inversion on the address if the selector has selected in the negative; and a supply section that supplies, to the memory under test, the address having undergone inversion control outputted from the inversion processing section and an inversion cycle signal that indicates whether the address outputted from the inversion processing section is bit inverted or not.

Abstract: A system and method for recovering from a configuration error are disclosed. A Basic Input Output System (BIOS) configures a memory associated with a node of an information handling system and enables a progress monitoring process during configuration of the memory. The memory is disabled if the BIOS determines that a configuration error occurred and a memory reference code associated with the memory is modified in order to prevent a reset of the information handling system.

Abstract: A system and method for testing multi-protocol network access using a synthetic multi-protocol client is provided. The synthetic multi-protocol client implements one or more predefined and/or user defined tests that interleave data access operations directed to a storage system using a plurality of data access protocols.

Abstract: A system, method, and computer program product are provided for sending failure information from a solid state drive (SSD) to a host device. In operation, an error is detected during an operation associated with a solid state drive. Additionally, a command is received for failure information from a host device. Further, the failure information is sent from the solid state drive to the host device, the failure information including failure information associated with the solid state drive.

Abstract: An MUT unit for testing memory modules includes a first circuit board; a second circuit board coupled to the first circuit board in a vertical orientation; a socket on a top surface of the first circuit board; and a resilient member electrically connecting the first and second circuit boards at an joint there between, wherein the resilient member comprises a horizontal segment that is welded to a bottom surface of the first circuit board, a vertical segment that is welded to a surface of the second circuit board, and a curved buffer segment connecting the horizontal segment and the vertical segment.

Abstract: A memory subsystem can test a memory device in situ, testing the performance of parameters of operation the device in the system it is built into during production. Thus, the system can detect the specific values that will work for one or more operating parameters for the memory device in actual runtime. A test component embedded in the memory subsystem can perform a stress test and identify specific bits or lines of memory that experience failure under one or more stresses. The system can then map out the failed bits or lines to prevent the bits/lines from being used in runtime of the system.

Abstract: Fault isolation capabilities made available by user space can be provided for a embedded network storage system without sacrificing efficiency. By giving user space processes direct access to specific devices (e.g., network interface cards and storage adapters), processes in a user space can initiate Input/Output requests without issuing system calls (and entering kernel mode). The multiple user spaces processes can initiate requests serviced by a user space device driver by sharing a read-only address space that maps the entire physical memory one-to-one. In addition, a user space process can initiate communication with another user space process by use of transmit and receive queues similar to transmit and receiver queues used by hardware devices. And, a mechanism of ensuring that virtual addresses that work in one address space reference the same physical page in another address space is used.

Abstract: An electronic device capable of communicating with a plurality of servers includes a storage unit, a vibration unit, a control unit, and a communication unit. The storage unit stores a vibration threshold value. The vibration sensor senses a vibration magnitude of the electronic device. The control unit generates control signals and transmits the control signals to the servers via the communication unit to direct the servers to take certain actions to protect data when the vibration magnitude sensed by the vibration sensor is equal to or greater than the vibration threshold value.

Abstract: Described embodiments provide a media controller for processing a diagnostic request received from a diagnostic source. The received diagnostic request is parsed by a corresponding request handling module of the media controller, where each diagnostic source type has a corresponding request handling module. If the received diagnostic request requires allocation of buffer space, a common diagnostic handling module of the media controller allocates buffer space in a buffer for the received diagnostic request. The common diagnostic handling module is common for all diagnostic source types. The common diagnostic handling module provides the received diagnostic request to a corresponding one of a plurality of end diagnostic handling modules. The end diagnostic handling module performs the diagnostic tasks. If the received diagnostic request requires a transfer of data to the diagnostic source, the common diagnostic handling module performs the data transfer between the media controller and the diagnostic source.

Abstract: A system includes a first device, a first storage element, a comparator and a second device. The first device is configured to test memory cells in an array of memory cells to detect defective memory cells. The defective memory cells include a first memory cell and a second memory cell. The first storage element is configured to store a first address of the first memory cell. The comparator is configured to compare a second address of the second memory cell to the first address.

Abstract: A first component, executing in a first data processing system, receives, over a data communication network using a first adapter, a first diagnostic heartbeat packet from a second adapter in a second data processing system. The first heartbeat packet comprises a header, a set of heartbeat parameters, and a set of diagnostic attributes. The first component determines, based on a set of values corresponding to the set of diagnostic attributes, that a soft network error condition exists in the data communication network. The soft network error condition is a network error condition that adversely affects the transmission of packets having certain properties in the data communication network. The first component stores the set of values in a state information record associated with the first component and re-routes data traffic from one link to a different link between the first and the second data processing systems.

Abstract: A solid state drive includes a first solid state disc controller (SSDC), a second SSDC and a flash array. The flash array includes a first flash port and a second flash port. The first SSDC is configured to connect to the flash array through the first flash port and the second flash array is configured to connect to the flash array through the second flash port.

Abstract: A programmable Built In Self Test (pBIST) system used to test embedded memories where the memories under test are incorporated in a plurality of sub chips not integrated with the pBIST module. A distributed Data Logger is incorporated into each sub chip, communicating with the pBIST over serial and a compressed parallel data paths.

Abstract: Systems and methods are disclosed for monitoring the time it takes to perform a write operation, and based on the time it takes, a determination is made whether to retire a block that is a recipient of the write operation. The time duration of the write operation for a page or a combination of pages may indicate whether any block or blocks containing the page or combination of pages is experiencing a physical failure. That is, if the time duration of the write operation for a particular page exceeds time threshold, this may indicate that this page requires a larger number of program cycles than other pages. The longer programming cycle can be an indication of cell leakage or a failing block.

Abstract: A data processing device according to the present invention includes a memory, an arithmetic circuit that accesses the memory by outputting an access control signal CTRL that controls access to the memory, a first data storage unit that stores first data used when a self-diagnosis is performed, a read-modify-write circuit that generates second data by replacing a part of the first data stored in the first data storage unit with modify data outputted from the arithmetic circuit, and a determination unit that diagnoses a failure of the read-modify-write circuit by comparing the second data with an expected value.

Abstract: A storage system comprises a storage device for storing data, a control apparatus which controls the storage device and comprises multiple communication ports, and a switch apparatus which expands the number of storage device couplings and comprises multiple communication ports. Respective multiple communication ports of the control apparatus are coupled to respective multiple communication ports of the switch apparatus, and the switch apparatus is coupled to the storage device. The control apparatus configures at least one communication port of the multiple communication ports of the control apparatus, to a dedicated communication port for outputting only a prescribed command issued when a failure is detected.