Abstract: A server motherboard diagnosis method, system, and related circuit system. A management module of the server motherboard and peripheral devices managed by the management module are capable of being powered by a server power source and a USB port. In response to the management module and the peripheral devices being powered by the USB port, a power supply line of the server power source is isolated, as by: identifying the peripheral devices, in response to the management module and the peripheral devices being powered by the USB port; for each of the identified peripheral devices, initializing the peripheral device, and then shutting down the power supply of the peripheral device; establishing a communication between the management module and a diagnosis host through the USB port; and executing a command in response to the command being received from the diagnosis host.

Abstract: A server motherboard diagnosis method, system, and related circuit system. A management module of the server motherboard and peripheral devices managed by the management module are capable of being powered by a server power source and a USB port. In response to the management module and the peripheral devices being powered by the USB port, a power supply line of the server power source is isolated, as by: identifying the peripheral devices, in response to the management module and the peripheral devices being powered by the USB port; for each of the identified peripheral devices, initializing the peripheral device, and then shutting down the power supply of the peripheral device; establishing a communication between the management module and a diagnosis host through the USB port; and executing a command in response to the command being received from the diagnosis host.

Abstract: Disclosed are a cipher control method which supports to maintain a cipher mode between a network system and a terminal. The method of controlling an encryption includes: attempting a connection for operating a communication channel between a terminal and a network system; providing cipher information about a cipher algorithm operation of the terminal to the network system; determining whether the terminal is a problematic terminal operating an abnormal cipher algorithm by the networking system; and when the terminal is determined to be operating abnormal, instructing the terminal to perform a communication channel operation based on a normally operable cipher algorithm by the network system.

Abstract: A configurable 2-wire/3-wire serial communications interface (C23SCI), which includes start-of-sequence (SOS) detection circuitry and sequence processing circuitry, is disclosed. When the SOS detection circuitry is coupled to a 2-wire serial communications bus, the SOS detection circuitry detects an SOS of a received sequence based on a serial data signal and a serial clock signal. When the SOS detection circuitry is coupled to a 3-wire serial communications bus, the SOS detection circuitry detects the SOS of the received sequence based on a chip select (CS) signal. In response to detecting the SOS, the SOS detection circuitry provides an SOS detection signal to the sequence processing circuitry, which initiates processing of the received sequence using the serial data signal and the serial clock signal. The received sequence is associated with one of multiple serial communications protocols.

Abstract: An automatically configurable 2-wire/3-wire serial communications interface (AC23SCI), which includes start-of-sequence (SOS) detection circuitry and sequence processing circuitry, is disclosed. When the SOS detection circuitry is coupled to a 2-wire serial communications bus, the SOS detection circuitry detects an SOS of a received sequence based on a serial data signal and a serial clock signal. When the SOS detection circuitry is coupled to a 3-wire serial communications bus, the SOS detection circuitry detects the SOS of the received sequence based on a chip select (CS) signal. The SOS detection circuitry provides an indication of detection of the SOS to the sequence processing circuitry, which initiates processing of the received sequence using the serial data signal and the serial clock signal upon the detection of the SOS. As such, the AC23SCI automatically configures itself for operation with some 2-wire and some 3-wire serial communications buses without external intervention.

Abstract: Various examples of techniques for identifying a corrupt data lane and using a spare data lane are described herein. Some examples include a method of coordinating spare lane usage between link partners. One such example comprises analyzing data from a link partner to identify a corrupt lane, and communicating the corrupt lane to the link partner, wherein the communication does not require sideband communication channel. In some embodiments, communicating the corrupt lane to the link partner comprises identifying a transmit lane corresponding to the corrupt lane, transmitting a set of data intended for a corresponding transmit lane using a spare data lane, and transmitting bad data to the link partner using the corresponding transmit lane.

Abstract: A test configuration resource manager and a method of managing test configuration resources in a network test system. A computer readable storage medium may store instructions that, when executed, cause a computing device to receive a user input identifying a portion of a first test configuration, store the identified portion of the first test configuration as a test configuration resource in a library of test configuration resources, receive a user input identifying a stored test configuration resource, retrieve the identified stored test configuration resource, and incorporate the retrieved test configuration resource into a second test configuration. The library of test configuration resources may include one or more of port resources, protocol resources, and traffic resources.

Abstract: System and method for automated testing of hot swap scenarios of field replaceable units (FRUs) in a storage system comprises an external automation server that distributes control signals to actuation systems within a number of FRUs. Power for the actuation systems may be provided by the external automation server or by self-contained power supplies with each actuation system. The actuation systems are responsive to the control signals to move the storage devices back-and-forth thereby electrically and physically disconnecting the storage device's mating connector from the backplane connector. This approach provides a high degree of automation while closely emulating customer hot swap scenarios.

Abstract: The disclosed embodiments provide a system that operates a processor in a computer system. During operation, the system uses the processor to maintain a count of outstanding input/output (I/O) requests for a component in the computer system. Next, the system facilitates efficient execution of the processor by overriding a latency tolerance reporting (LTR) value for the component based on the count.

Abstract: A network, in particular an Ethernet network, contains as network elements at least two network components that are interconnected by a network transmission line. Accordingly, at least one expansion unit having two external ports is disposed in the network line for extending the scope thereof, wherein the expansion unit forwards a failure of the network transmission line at one of the ports thereof to a port of the next subsequent network element.

Abstract: A method, system, and medium are disclosed for performing transparent failover in a cluster server system. The cluster includes a plurality of servers. In servicing a client request, a primary server replicates session data for the client into memory space of one or more backup servers. The primary server sends a response to the client, wherein the response includes an indication of the one or more backup servers. When the client sends a subsequent request, it includes an indication of the backup servers. If the primary server is unavailable, the cluster determines a recovery server from among the backup servers indicated by the request. The chosen recovery server would then service the request.

Abstract: A computer-implemented method for performing input/output path failovers may include identifying a computing system with a plurality of input/output paths to a storage array. The computer-implemented method may additionally include detecting a failure of a first input/output path within the plurality of input/output paths. The computer-implemented method may also include receiving a communication from the storage array indicating that a storage processor within the first input/output path is unavailable. The computer-implemented method may further include selecting at least one alternate input/output path within the plurality of input/output paths that does not include the storage processor. The computer-implemented method may additionally include reconfiguring the computing system to access the storage array via the alternate input/output path. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A system and method for direct memory access (DMA) operation provides for receiving DMA requestors, assigning the received DMA requestors to one or more of a plurality of DMA engines for processing the received DMA requestors, and if one of the received DMA requestors is a safety requestor, assigning the safety requestor to at least two DMA engines of the plurality of DMA engines for processing the safety requestor, disabling a bus interface for coupling at least one DMA engine of the at least two DMA engines to memories, comparing the outputs of the at least two DMA engines, and generating an error message if the comparison of the outputs of the at least two DMA engines are different from each other.

Abstract: A storage device failure in a computer storage system can be analyzed by the storage system by examining relevant information about the storage device and its environment. Information about the storage device is collected in real-time and stored; this is an on-going process such that some information is continuously available. The information can include information relating to the storage device, such as input/output related information, and information relating to a storage shelf where the storage device is located, such as a status of adjacent storage devices on the shelf. All of the relevant information is analyzed to determine a reason for the storage device failure. Optionally, additional information may be collected and analyzed by the storage system to help determine the reason for the storage device failure. The analysis and supporting information can be stored in a log and/or presented to a storage system administrator to view.

Abstract: A method, an apparatus and an article of manufacture for detecting an event storm in a networked environment. The method includes receiving a plurality of events via a plurality of probes in a networked environment, each of the plurality of probes monitoring a monitored information technology (IT) element, aggregating the plurality of events received into an event set, and correlating the plurality of events in the event set to determine whether the plurality of events are part of an event storm by determining if the plurality of events in the event set meet one or more event storm criteria.

Abstract: Determining port failover information is described. First information is determined by a first storage processor executing first code for performing port matching. The first information identifies a first set of port pairs. Each port pair includes a first port of the first or second storage processor and a second port of the first or second storage processor. Each port pair denotes the first port as protecting the second port. Upon failure or unavailability of the second port, the first port virtualizes the second port and requests directed to the second port are redirected to the first port. Similarly, second information is determined by the second storage processor executing second code for performing the port matching. Port failover processing is performed upon failure or unavailability of port(s) of the first storage processor and/or the second storage processor. Port failover processing uses the first information and/or the second information.

Abstract: A computer program product for handling communication link problems between a first communication means and a second communication means. Data signals, control signals and/or error information are transferred between the first communication means and the second communication means using the communication link. The method includes activating a static identification pattern in the first communication means representing an error information, and stopping a clock signal (Clk) inside the first communication means to freeze a present error condition, in response to a communication link problem being detected, and transferring the activated static identification pattern permanently and/or repeatedly to the second communication means using the communication link.

Abstract: One aspect of the present disclosure relates to a backplane initiator for testing enclosure management controller. The backplane initiator includes: an initiator board and an initiator control application. The initiator board includes initiator controller, at least one SGPIO interface, at least one SMBus interface, and a first communication interface. The initiator controller is configured to transmit control commands and data according to enclosure management protocol through the SGPIO interface and the SMBus interface to an EMC.

Abstract: An apparatus and method are disclosed to optimize the latency and the power of a link operating inside a processor-based system. The apparatus and method include a latency meter built into a queue that does not rely on a queue-depth threshold. The apparatus and method also include feedback logic that optimizes power reduction around an increasing latency target to react to sluggish re-provisioning behavior imposed by the physical properties of the link.

Abstract: A method is provided for cabling a plurality of hardware components. A chassis controller establishes a wireless connection to a wireless device. The chassis controller, via a wireless interface, transmits a chassis map to the wireless device over the wireless connection. The chassis controller, via the wireless interface, transmits to the wireless device, an indication of a first port to be cabled over the wireless connection, the first port. The first port is of a first hardware component of the plurality of hardware components. The chassis controller tests the first port to determine whether cabling of the first port has been performed correctly.

Abstract: An electronic device includes an earphone port, an audio amplifier, a digital processor, a multi-way selection switch, and an earphone detection response circuit. The earphone port includes left and right channel pins. The audio amplifier includes an earphone left channel output pin and an earphone right channel output pin. The digital processor includes a data transmission pin and a data receive pin. The multi-way selection switch includes four switches electrically connected between the data transmitting pin and the left channel pin, the data receive pin and the right channel pin, the earphone left channel output pin and the left channel pin, and the earphone right channel output pin and the right channel pin, respectively. The earphone detection response circuit turns on a first switch and a second switch, and turns off a third switch and a fourth switch when the earphone port does not receive an earphone.

Abstract: A method of operating a test equipment system that is coupled to network circuitry is described. The method displays only selected information. Furthermore, the method may display the selected information in a manner as to allow a user of the test equipment to easily identify errors in the network circuitry. The method may select the information to be displayed by processing received signals according to a stacked protocol hierarchical structure.

Abstract: A method and system for repairing high speed serial links is provided. The system includes a first electronic components, connected to at least a second electronic component via at least one link. At least one of the first or second electronic components has a link controller. The link controller is configured to repair serial links by detecting a link error and mapping out individual lanes of a link where the link error is detected. The link controller resumes operation, i.e., transmission of data and continues to monitor the lanes for errors. If and when additional link errors occur, the link controller identifies the lanes in which the link error occurs and deactivates those lanes. The deactivated lane(s) can not be used in further transmissions which, in turn, reduces the occurrence of intermittent link errors.

Abstract: Techniques and configurations are disclosed herein for communication between devices. In some embodiments, a bus for communication between first and second devices may include a transmit buffer and one or more processing devices. The one or more processing devices may be configured to receive first asynchronous data from an operating system, running on a central processing unit of the first device, on an operating system signal path; transmit the first asynchronous data from the first device to the second device on a command signal path; transmit first data from the transmit buffer to the second device at a first fixed packet frequency on a transmit signal path; and receive data from the second device at a second fixed packet frequency on a receive signal path different from the transmit signal path. Other embodiments may be disclosed and/or claimed.

Abstract: A system for implementing interconnection fault tolerance between CPUs, a first CPU and a second CPU implements interconnection through a first CPU interconnect device and a second CPU interconnect device. The system adds a data channel between a first SerDes interface of the first CPU interconnect device and a second SerDes interface of the second CPU interconnect device, and transmits link connection state information and a link control signal through the added data channel. The system monitors a link state of any one link in a CPU interconnection system, transmits the link state through the added data channel, recovers any one of the connection links when determining whether any one of the first connection link, the second connection link and the third connection link is faulty.

Abstract: Systems for helping identify faults on a bus, as well as to determine the topology of a bus network, are disclosed. A system according to one embodiment includes a bus interface for connecting to a bus and a switch coupled to the bus interface, the switch configured to alternate between an open state and a closed state. The system is connected to the bus via the bus interface when the switch is in the closed state, and the system is disconnected from the bus via the bus interface when the switch is in the open state.

Abstract: Methods and apparatus for testing Input/Output (I/O) boundary scan chains for Systems on a Chip (SoCs) having I/Os that are powered off by default. Some methods and apparatus include implementation of boundary scan chain bypass routing schemes that selectively route a boundary scan chain path around I/O interfaces and/or ports that are powered off by default. Other techniques include selectively power-on I/Os that are powered off by default in a manner that is independent of SoC facilities for controlling the power state of the I/Os during SoC runtime operations. Various schemes facilitate boundary scan testing in accordance with IEEE Std.-1149.1 methodology.

Abstract: A PCIE switch-based server system, switching method and device are disclosed. The system includes: an active PCIE switch device, where the active PCIE switch device includes a communication interface and a first PCIE switch module, and the first PCIE switch module includes at least two first PCIE ports; a standby PCIE switch device, where the standby PCIE switch device includes a communication interface and a first PCIE switch module, and the first PCIE switch module includes at least two first PCIE ports; where the communication interface of the active PCIE switch device and the communication interface of the standby PCIE switch device are interconnected, so that the standby PCIE switch device obtains switch network configuration information of the active PCIE switch device through the communication interface of the active PCIE switch device and the communication interface of the standby PCIE switch device.

Abstract: A network testing method implemented in a software-defined network (SDN) is disclosed. The network testing method comprising providing a test scenario including one or more network events, injecting said one or more network events to the SDN using an SDN controller, and gathering network traffic statistics. A network testing apparatus used in a software-defined network (SDN) also is disclosed. The network testing apparatus comprising a testing system to provide a test scenario including one or more network events, to inject said one or more network events to the SDN using an SDN controller, and to gather network traffic statistics. Other methods, apparatuses, and systems also are disclosed.

Abstract: A safety device of the invention includes at least one of an input unit having one or more input terminals and an output unit having one or more output terminals, a testing unit having one or more test terminals, a rewritable nonvolatile memory configured to store setting information of a terminal specification which can be set from outside via the tool, and wherein the terminal specification of the one or more test terminals included in the testing unit is determined in accordance with the setting information of the terminal specification.

Abstract: Processing, such as debug and/or recovery processing, within a communications environment is facilitated. Responsive to detecting an event, a stop signal is propagated through a communications network of the communications environment, and each network element that receives the stop signal, transmits the signal to its neighbors (if any), and then performs an action depending on its specific programming. The action can be to take no action, perform a debugging action or perform a recovery action. The elements that receive the signal and perform the same action as other elements form a coordinated network providing a coordinated result.

Abstract: Processing, such as debug and/or recovery processing, within a communications environment is facilitated. Responsive to detecting an event, a stop signal is propagated through a communications network of the communications environment, and each network element that receives the stop signal, transmits the signal to its neighbors (if any), and then performs an action depending on its specific programming. The action can be to take no action, perform a debugging action or perform a recovery action. The elements that receive the signal and perform the same action as other elements form a coordinated network providing a coordinated result.

Abstract: Serial Attached SCSI (SAS) expander includes an exposed SAS interface connector, a microcontroller unit (MCU), a smart port, and an SAS expander chip. The SAS interface connector is coupled to a host personal computer (PC) to receive commands sent from the host PC. When a fault occurs in the SAS expander or a connected storage device, the MCU enables the smart port in response to a first control command sent from the host PC, reads status information from the SAS expander chip through the smart port in response to a status reading command sent from the host PC, and sends read status information back to the host PC for analyzing. MCU obtains detailed fault information from the SAS expander chip through the smart port in response to a detailed fault information obtaining command sent from the host PC and sends the obtained detailed fault information back to the host PC.

Abstract: A first component, executing using a processor and a memory in a first data processing system, receives a diagnostic heartbeat packet from a second component executing in a second data processing system, wherein the diagnostic heartbeat packet is a packet comprising a header, a set of heartbeat parameters, and a set of diagnostic attributes. The first component determines, using a value of a diagnostic attribute in the diagnostic heartbeat packet, that a first communication link between the first and the second data processing systems is usable but includes a soft network error, wherein a soft network error condition is a network error condition that adversely affects transmission of packets having certain properties in the data communication network. The first component re-routes a synchronization message from the first component to the second component using a second communication link between the first and the second data processing systems.

Abstract: In one embodiment, a protocol state associated with a port of a network device is determined to have expired. A port group of which the port is a member is determined, the port group including ports that share one or more common characteristics. A policy is applied to the ports of the port group to determine whether one or more other ports in the port group also have a corresponding protocol state protocol that has expired. In response to one or more other ports in the port group also having a corresponding protocol state that has expired, expiration of the protocol state is determined to be a false positive and no further action is taken based on expiration of the protocol state. When expiration of the protocol state is not determined to be a false positive, further action is taken based on expiration of the protocol state.

Abstract: Systems and methods for modeling test space for verifying system behavior, using one or more auxiliary variables, are provided. The method comprises implementing a functional coverage model including: one or more attributes, wherein respective values for the attributes are assigned according to a test plan, and one or more constraints defining restrictions on value combinations assigned to the attributes, wherein the restrictions are Boolean expressions defining whether said value combinations are valid; determining a set of valid value combinations for the attributes that satisfy the restrictions to define the test space for verifying the system behavior; and determining relevant auxiliary variables and a corresponding function for said auxiliary variables to reduce the complexity associated with modeling the test space.

Abstract: A monitoring circuit monitors for the occurrence of a failure event on a data bus. The monitoring circuit includes a failure detection circuit for detecting the occurrence of the failure event within a device coupled to the data bus. An isolation circuit isolates the device from the data bus in response to the occurrence of the failure event.

Abstract: A semiconductor memory apparatus including a test circuit configured for generating compressed data by comparing and compressing data stored in a plurality of memory cells inside a memory bank during a first test mode, and configured for outputting the compressed data as test data to an input/output pad through one selected global line during the first test mode, and the test circuit is configured for transmitting the compressed data to a plurality of global lines during a second test mode, combining the compressed data loaded in the respective global lines during the second test mode, and outputting the combination result as the test data to the input/output pad during the second test mode.

Abstract: Isolation of faulty links in a transmission medium including a method that includes receiving an atomic data unit via a multi-link transmission medium that has a plurality of transmission links. An error condition is detected and it is determined that the error condition is isolated to a single transmission link. It is determined if the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer. If the single transmission link has been isolated previously as a failing transmission link a specified number of times within an interval specified by a timer then: identifying the single transmission link as a faulty transmission link; resetting the timer; and outputting an identifier of the single transmission link.

Abstract: A control circuit board includes a first storage unit configured to store therein predetermined data; a connecting unit configured to be connected to another control circuit board including a second storage unit; a switching unit configured to switch between a first state and a second state, the first state being a state in which data read from the first storage unit is enabled but data read from the second storage unit is disabled, the second state being a state in which data read from the first storage unit is disabled but data read from the second storage unit is enabled; and a storage control unit configured to write or read data to or from the first storage unit in the first state, and perform a copying operation that reads the data from the second storage unit and stores the read data in the first storage unit in the second state.

Abstract: Connectivity fault notification is provided by generating an alarm indication signal at a device that is logically adjacent to the fault, and forwarding the alarm indication signal upward through various levels to at least one client level entity. The alarm indication signal may be suppressed at any level for a service instance if service is restored at that level, or if a protection path prevents disruption of the service instance at that level, or auto-suppressed at an originating node based on number of times transmitted or elapsed time. The alarm indication signal may include a point of failure indicator such as the MAC address of the device that generates the alarm indication signal, or a failed resource identity such as an IEEE 802.1AB LLDP MAC Service Access Point (“MSAP”). Further, the alarm indication signal may be employed to trigger use of the protection path.

Abstract: A network system configured from a test device that executes a test including a continuity test and a performance test of a network configured from a plurality of transfer devices and a management server that requests an execution of the test for the test device, in this way, one or more backup session used for executing the test is selected from a plurality of sessions, the test is executed for a processing interval in a success, a next test is executed by the backup session when the processing time for the test exceeds over a specified time, thereby, a large number of tests can be executed and the test can be executed regularly even when the processing time becomes longer caused by a failure etc.

Abstract: A USB testing device is provided for an electronic device having a USB port. The USB testing device includes a first USB control unit, a second USB control unit, and a micro-processor. When the first USB control unit has received power, the first USB control unit processes a connection test via a first data port. When the second USB control unit has received the power, the second USB control unit processes a connection test via a second data port. When the USB testing device is connected to the USB port, the micro-processor provides power to the first USB control unit. When the first USB control unit receives power, the first USB control unit provides power to the second USB control unit after waiting for a predetermined period of time. The electronic device determines whether the first and second data ports are operating properly.

Abstract: Embodiments relate to providing communication over cross-coupled links between independently managed compute and storage networks. An aspect includes coupling an independently managed local subsystem with an independently managed remote subsystem over cross-coupled links, whereby each subsystem includes compute entities and storage entities. Unique identifiers are assigned to all the compute entities and the storage entities in the local network and the remote network. A determination is then made as to whether each entity is in the local subsystem or the remote subsystem. Accordingly, a global broadcast tree is built to bridge the compute entities in the local subsystem to the storage entities in both the local and remote subsystem. Responsive to an error in a layer of the local subsystem external to a cross-coupled link, the cross-coupled link in the local subsystem is disabled. Accordingly, the remote subsystem may detect that the link has failed.

Abstract: A system includes a packet generator and a packet checker. The packet generator is operable to operable to generate a packet for transmission to a destination device. The packet includes a plurality of fields, including a code field that is operable to store a code generated based on an expected modification to the packet during transmission. The packet checker is associated with the destination device and is operable to receive the packet.

Abstract: An information processing apparatus includes: a first communication section which communicates with an external device having a diagnosis function of a network using a first communication method; a second communication section which communicates with the external device using a second communication method; a first transmission section which transmits a diagnosis request to the external device through the first communication section; and a second transmission section which transmits a diagnosis signal to the external device through the second communication section, after transmission of the diagnosis request.

Abstract: A system firmware agent providing the capabilities of a Baseboard Management Controller (BMC) from within System Management Mode (SMM) is discussed. A virtual BMC provides dedicated communication channels for system firmware, other BMCs in the platform and remote management agents. The virtual BMC may monitor the status of the system, record system events, and control the system state.

Abstract: Systems and methods are provided for selecting a path for an I/O in a storage area network. In one embodiment, a method comprises receiving path configuration information for paths associated with a host device connected to the storage area network, a listing of components within the storage area network, and a notification of a component failure within the storage area network. The method may also comprise correlating the received path configuration information, the received listing of components, and the received notification of component failure to determine one determine one or more paths associated with the host device affected by the component failure. The method may further comprise transmitting to the host device an alert for the one or more affected paths.

Abstract: Systems for helping identify faults on a bus, as well as to determine the topology of a bus network, are disclosed. A system according to one embodiment includes a bus interface for connecting to a bus and a switch coupled to the bus interface, the switch configured to alternate between an open state and a closed state. The system is connected to the bus via the bus interface when the switch is in the closed state, and the system is disconnected from the bus via the bus interface when the switch is in the open state.

Abstract: Method and system for managing port failover in storage system comprising first storage processor and first port and second storage processor and second port. Storage system adapted to communicate with FC switch. Storage system providing first and second names characterizing first and second ports to switch for registration such that the first name associated with first port and second name associated with second port. Storage system detects the state of first and second processors. Failure state in first or second processor activates deregistration of port associated therewith. Storage system providing to switch for re-registration one of the names in response to detecting failure in processor associated with one of the ports. The one of the names provided to switch such that the one of the names characterizing the one of the ports is associated with the other of the ports.