Access Processor Affected (e.g., I/o Processor, Mmu, Or Dma Processor, Etc.) Patents (Class 714/5.11)
  • Patent number: 8312313
    Abstract: An information processing apparatus has a first storage unit and a second storage unit and operates in one of a normal power mode and a power saving mode. When the information processing apparatus is operating in the power saving mode, if an error occurs in a storage process, the power mode of the information processing apparatus is switched to the normal power mode and the storage process is executed again. The storage process is a process in which when the first storage unit is replaced with a new storage unit, information equivalent to that stored in the first storage unit is stored in the new storage unit.
    Type: Grant
    Filed: January 5, 2010
    Date of Patent: November 13, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventor: Masakazu Kitora
  • Patent number: 8286027
    Abstract: An I/O device includes a host interface that may receive and process transaction packets sent by a number of processing units, with each processing unit corresponding to a respective root complex. The host interface includes an error handling unit having error logic implemented in hardware that may determine, as each packet is received, whether each transaction packet has an error and to store information corresponding to any detected errors. The error handling unit may include an error processor that may be configured to execute error processing instructions to determine any error processing operations based upon the information. The error processor may also generate and send one or more instruction operations, each corresponding to a particular error processing operation. The error handling unit may also include an error processing unit that may execute the one or more instruction operations to perform the particular error processing operations.
    Type: Grant
    Filed: May 25, 2010
    Date of Patent: October 9, 2012
    Assignee: Oracle International Corporation
    Inventors: John E. Watkins, Elisa Rodrigues, Abbas Morshed
  • Patent number: 8281180
    Abstract: A main data center with first and second backup data centers also has a translator for assisting a failover module of a failed server at the main data center in implementing failover of the failed server to a corresponding server at the first backup data center. The translator intercepts a command from the failover module to a store of the main data center, where the command directs the store to disable writes to particular storage space in the store associated with the failed server, but does not identify with specificity which of a store of the first data center and a store of the second data center is enabled to write to such particular storage space. Thus, the translator determines an identification of the store of the first backup data center, and modifies the command from the failover module based on the determined identification.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: October 2, 2012
    Assignee: United Services Automobile Association (USAA)
    Inventor: Larry S. Roy
  • Patent number: 8250250
    Abstract: In an embodiment, an integrated circuit includes a direct memory access (DMA) controller configured to perform DMA operations between peripheral components of the integrated circuit and/or a memory to which the integrated circuit is configured to be coupled. Combinations of memory-to-memory, memory-to-peripheral, and peripheral-to-memory operations may be used. The DMA controller may be programmed to perform a number of DMA operations concurrently. The DMA operations may be programmed and performed as part of testing the integrated circuit during design and/or manufacture of the integrated circuit. The DMA operations may cause many of the components in the integrated circuit to be busy performing various operations. In some embodiments, programmed input/output (PIO) operations may also be performed while the DMA operations are in progress. In some embodiments, various parameters of the DMA operations and/or PIO operations may be randomized.
    Type: Grant
    Filed: October 28, 2009
    Date of Patent: August 21, 2012
    Assignee: Apple Inc.
    Inventors: Maziar H. Moallem, Richard F. Avra
  • Patent number: 8185775
    Abstract: When a failure occurs in an LPAR on a physical computer under an SAN environment, a destination LPAR is set in another physical computer to enable migrating of the LPAR and setting change of a security function on the RAID apparatus side is not necessary. When a failure occurs in an LPAR generated on a physical computer under an SAN environment, configuration information including a unique ID (WWN) of the LPAR where the failure occurs is read, a destination LPAR is generated on another physical computer, and the read configuration information of the LPAR is set to the destination LPAR, thereby enabling migrating of the LPAR when the failure occurs, under the control of a management server.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: May 22, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Yukari Hatta, Hitoshi Ueno
  • Publication number: 20120110374
    Abstract: Some embodiments of the invention relate to an embedded processing system. The system includes a memory unit to store a plurality of operating instructions and a processing unit coupled to the memory unit. The processing unit can execute logical operations corresponding to respective operating instructions. An input/output (I/O) interface receives a first time-varying waveform and provides an I/O signal that is based on the first time-varying waveform. A comparison unit coupled to the processing unit and adapted to selectively assert an error signal based on whether the I/O signal has a predetermined relationship with a reference signal, wherein the predetermined relationship holds true during normal operation but fails to hold true when an unexpected event occurs and causes an unexpected change at least one of the I/O signal and reference signal.
    Type: Application
    Filed: October 29, 2010
    Publication date: May 3, 2012
    Applicant: Infineon Technologies AG
    Inventors: Simon Brewerton, Patrick Leteinturier, Oreste Bernardi, Antonio Vilela, Klaus Scheibert, Jens Barrenscheen
  • Patent number: 8166338
    Abstract: A method provides exception handling for a computer system. As an error in the computer system's hardware is detected, an exception vector pertaining to the hardware error is determined, and execution flow is transferred to a dispatcher that corresponds/pertains to the exception vector. A specific instance of a plurality of instances of a main exception handler is selected, and the specific instance of the main exception handler is executed. The actual exception handler thus contains two distinct parts, a dispatcher, which is unique and preferably resides in a safe memory region, and a main exception handler, multiple copies of which reside in an unsafe memory region.
    Type: Grant
    Filed: May 25, 2010
    Date of Patent: April 24, 2012
    Assignee: International Business Machines Corporation
    Inventors: Thomas Huth, Jan Kunigk, Joerg-Stephan Vogt
  • Patent number: 8156367
    Abstract: An I/O device management table that manages the types of I/O devices connected to an I/O switch is provided, and one or plural unallocated I/O devices are defined and registered as standby I/O devices. When a failure occurs in any of I/O devices, the I/O device management table is used to select an I/O device of the same type as the failed I/O device from the standby I/O devices, and the selected I/O device is allocated to a computer to which the failed I/O device is connected. I/O device management can be eased at failure in a computer including an I/O switch device.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: April 10, 2012
    Assignee: Hitachi, Ltd.
    Inventor: Yoshifumi Takamoto
  • Publication number: 20110320861
    Abstract: A system and a method for failover control comprising: maintaining a primary device table entry (DTE) in a first table activated for a first adapter in communication with a first processor node having a first root complex via a first switch assembly and maintaining a secondary DTE in standby for a second adapter in communication with a second processor node having a second root complex via a second switch assembly; maintaining a primary DTE in a second table activated for the second adapter and maintaining a secondary DTE in standby for the first adapter; and upon a failover, updating the secondary DTE in the first table as an active entry for the second adapter and forming a path to enable traffic to route from the second adapter through the second switch assembly over to the first switch assembly and up to the first root complex of the first processor node.
    Type: Application
    Filed: June 23, 2010
    Publication date: December 29, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gerd K. Bayer, David F. Craddock, Thomas A. Gregg, Michael Jung, Andreas Kohler, Elke G. Nass, Oliver G. Schlag, Peter K. Szwed
  • Patent number: 8086896
    Abstract: In virtualized environments, storage may be managed dynamically due to the changing data storage requirements. In such environments, logical storage unit identifiers (LUN IDs) may be modified as a result of deleting an existing mapping between physical storage and a virtualization server and recreating the mapping. This can result in I/O request failure. Techniques for resolving errors resulting from LUN ID modifications can be time-intensive and labor-intensive and can disrupt a communication path between a host device and the physical storage. Functionality can be implemented to dynamically identify the LUN ID modifications, determine valid LUN IDs, and retransmit failed I/O requests. This can help minimize I/O request failures due to LUN ID modifications without disrupting the communication path between the host device and the physical storage.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: December 27, 2011
    Assignee: International Business Machines Corporation
    Inventors: James P. Allen, Kiran K. Anumalasetty, Sudhir Maddali, Bhyrav M. Mutnury, James A. Pafumi, Sanket Rathi, Stephen M. Tee
  • Patent number: 8074102
    Abstract: A method for reactivating at least one media transfer protocol-compatible (MTP-compatible) device when an unrecoverable error occurs includes: temporarily storing a transaction ID of a latest operation performed on the MTP-compatible device; and selectively communicating with the MTP-compatible device by utilizing the transaction ID when an unrecoverable error of the MTP-compatible device occurs. An associated host for reactivating at least one MTP-compatible device when an unrecoverable error occurs includes a storage unit and a processing circuit. The storage unit is arranged to temporarily store a transaction ID of a latest operation performed on the MTP-compatible device. In addition, the processing circuit is arranged to selectively communicate with the MTP-compatible device by utilizing the transaction ID when an unrecoverable error of the MTP-compatible device occurs.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: December 6, 2011
    Assignee: MediaTek Singapore Pte. Ltd.
    Inventor: Jian Zhang
  • Publication number: 20110296234
    Abstract: Disclosed are methods for exposing multiple interfaces of a communications fabric (Ethernet, FibreChannel, Serial-Attached-SCSI, Infiniband, etc.) of a virtual machine and automatically mapping those interfaces onto separate physical interfaces. Such an approach may preserve the simple management experience of a single connection point into the virtual machine while allowing the OS and application within the virtual machine to supply information necessary to efficiently use the multiply underlying physical links.
    Type: Application
    Filed: May 25, 2010
    Publication date: December 1, 2011
    Applicant: Microsoft Corporation
    Inventors: Jacob Oshins, Tejas Karandakar
  • Patent number: 8060775
    Abstract: A method and apparatus for providing dynamic multi-pathing for an asymmetrical logical unit access (ALUA) based storage system. The method comprises identifying a first processor within a storage system as providing an optimized path to a disk array, identifying a second processor within a storage system as providing an unoptimized path to the disk array and, in response to failure of the optimized path, immediately switching from the optimized path to the unoptimized path.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: November 15, 2011
    Assignee: Symantec Corporation
    Inventors: Mona Sharma, Siddhartha Nandi, Praveen Kumar Padia
  • Patent number: 8041987
    Abstract: Embodiments that dynamically manage physical and virtual multipath I/O are contemplated. Various embodiments comprise one or more computing devices, such as one or more servers, having at least two HBAs. At least one of the HBAs may be associated with a virtual I/O server that employs the HBA to transfer data between a plurality of virtual clients and one or more storage devices of a storage area network. The embodiments may monitor the availability of the HBAs, such as monitoring the HBAs for a failure of the HBA or a device coupled to the HBA. Upon detecting the unavailability of one of the HBAs, the embodiments may switch, dynamically, from the I/O path associated with the unavailable HBA to the alternate HBA.
    Type: Grant
    Filed: November 10, 2008
    Date of Patent: October 18, 2011
    Assignee: International Business Machines Corporation
    Inventors: James P. Allen, Robert G. Kovacs, James A. Pafumi, James B. Partridge, Jacob J. Rosales, Stephen M. Tee
  • Patent number: 8037368
    Abstract: A controller capable of self-monitoring, a redundant storage system having the same, and its method are proposed. Each controller is arranged with a self-monitoring operating circuit and a watchdog unit. The self-monitoring operating circuit can periodically issue a confirmation signal to the watchdog unit. The watchdog unit comprises a counter unit for counting a predetermined time interval, and if it does not receive the confirmation signal issued by the self-monitoring operating circuit over the predetermined time interval, it will send out an output signal to the self-monitoring operating circuit. The self-monitoring operating circuit will then generate a plurality of global reset signals to shut down the entire operation of the controller. Another controller will take over the functions of the shut-down controller.
    Type: Grant
    Filed: July 11, 2005
    Date of Patent: October 11, 2011
    Assignee: Infortrend Technology Inc.
    Inventor: Cheng-Yu Lee
  • Patent number: 8028190
    Abstract: The bus control device includes a reset control unit which resets the input and output bus in response to receipt of reset instruction; a reset inhibition unit which inhibits a reset of the input and output bus triggered by a fault occurrence in the input and output bus; a log collection unit which collects log information of an input and output device connected to a fault occurrence section in the input and output bus triggered by the fault occurrence in the input and output bus; and an input and output interface which transfers the log information collected by the log collection unit to the processor. The reset inhibition unit cancels inhibition of the reset after the collection of the log information by the log collection unit has been completed.
    Type: Grant
    Filed: March 12, 2009
    Date of Patent: September 27, 2011
    Assignee: NEC Corporation
    Inventor: Hiroaki Oshida
  • Patent number: 8024602
    Abstract: Disclosed is a storage system and method that provides multi-path bus and component interconnection and isolation in a data storage system. A plurality of data storage devices in a removable assembly are connected to a fabric that is configurable to connect some or all of the data storage devices (or “drives”) to a drive controller and configurable to isolate one or more data storage devices from the drive controller. Multiple controllers, fabrics, and interconnecting buses may be employed to provide redundancy in the event of a connector, bus, or controller failure. Computer program code operating in a host, interface controller, and/or drive controller configures the fabric to isolate failed devices and may be employed to optimize data transfer rates. Data storage devices may be multi-ported. The fabric may comprise any device or devices capable of configurably interconnecting data storage devices to one or more controllers and may comprise multiplexers, cross point switches, port bypass controllers.
    Type: Grant
    Filed: July 14, 2008
    Date of Patent: September 20, 2011
    Assignee: Seagate Technology LLC
    Inventors: David Peter DeCenzo, William A. Pagano, Stephen J. Sicola
  • Patent number: 8015433
    Abstract: A disk drive that includes nonvolatile memory monitors the drive's reliability-related parameters to detect real or potential failure events, and records failure-related data in nonvolatile memory, rather than in reserved areas of the disks. The monitoring may be by running a diagnostic routine or by regular or periodic monitoring of disk drive sensors, like temperature and shock sensors. The failure events to be monitored and recorded may include defective data sectors. When a new defective sector is detected after the disk drive has been put into operation, that defective sector is taken out of service and its logical block address (LBA) is mapped to a memory space in the nonvolatile memory rather to a reserved spare sector on the disk.
    Type: Grant
    Filed: September 13, 2006
    Date of Patent: September 6, 2011
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Frank R. Chu, George A. Dunn, Richard M. H. New, Spencer W. Ng
  • Patent number: 8010847
    Abstract: A memory chip having a memory with a plurality of non-redundant memory lines and a plurality of redundant memory lines, and a controller configured to allocate dynamically a redundant memory line to a failed memory line during runtime.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: August 30, 2011
    Assignee: Infineon Technologies AG
    Inventor: Klaus Oberlaender
  • Patent number: 8006123
    Abstract: Provided is an environment that storage device configuration management can be efficiently done in a data center having a virtualization device. A SAN manager acquires configuration information from a device constituting a SAN and prepares a correspondence relationship between a host computer and a virtual volume in the SAN, and a corresponding relationship between the host computer and a real volume, depending upon the acquired information. Based on the corresponding relationship, the SAN manager outputs a correspondence relationship of between virtual and real volumes. Meanwhile, by interpreting a failure-notification message received from the devices of the SAN, detected and outputted is an influence upon an access to a real or virtual volume as to the failure.
    Type: Grant
    Filed: January 26, 2010
    Date of Patent: August 23, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Masayuki Yamamoto, Takashi Oeda
  • Publication number: 20110173488
    Abstract: A system, method and computer program product for supporting system initiated checkpoints in high performance parallel computing systems and storing of checkpoint data to a non-volatile memory storage device. The system and method generates selective control signals to perform checkpointing of system related data in presence of messaging activity associated with a user application running at the node. The checkpointing is initiated by the system such that checkpoint data of a plurality of network nodes may be obtained even in the presence of user applications running on highly parallel computers that include ongoing user messaging activity. In one embodiment, the non-volatile memory is a pluggable flash memory card.
    Type: Application
    Filed: January 10, 2011
    Publication date: July 14, 2011
    Applicant: International Business Machines Corporation
    Inventors: Matthias A. Blumrich, Dong Chen, Thomas M. Cipolla, Paul W. Coteus, Alan Gara, Philip Heidelberger, Mark J. Jeanson, Gerard V. Kopcsay, Martin Ohmacht, Todd E. Takken
  • Patent number: 7975167
    Abstract: An information system includes a housing with a plurality of units mounted thereon, a communication path built in the housing to take charge of information communication between a plurality of the units mounted on the housing, an information unit mounted on the housing to provide and process the information, a plurality of communication units each mounted on the housing to independently relay the information communication between the information unit and a device external to the housing, and a management unit for accessing the whole or a part of the plurality of the units mounted on the housing and acquiring internal information of the units accessed, wherein in the case where all the plurality of the communication units accessed are incommunicable, the internal information acquired from the plurality of the communication units is reported to the device external to the housing without passing through the plurality of the communication units.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: July 5, 2011
    Assignee: Fujitsu Limited
    Inventor: Masanori Takaoka
  • Publication number: 20110161725
    Abstract: In virtualized environments, storage may be managed dynamically due to the changing data storage requirements. In such environments, logical storage unit identifiers (LUN IDs) may be modified as a result of deleting an existing mapping between physical storage and a virtualization server and recreating the mapping. This can result in I/O request failure. Techniques for resolving errors resulting from LUN ID modifications can be time-intensive and labor-intensive and can disrupt a communication path between a host device and the physical storage. Functionality can be implemented to dynamically identify the LUN ID modifications, determine valid LUN IDs, and retransmit failed I/O requests. This can help minimize I/O request failures due to LUN ID modifications without disrupting the communication path between the host device and the physical storage.
    Type: Application
    Filed: December 28, 2009
    Publication date: June 30, 2011
    Applicant: International Business Machines Corporation
    Inventors: James P. Allen, Kiran K. Anumalasetty, Sudhir Maddali, Bhyrav M. Mutnury, James A. Pafumi, Sanket Rathi, Stephen M. Tee
  • Publication number: 20110145632
    Abstract: A method is provided for recovering from an uncorrected memory error located at a memory address as identified by a memory device. A stored hash value for a memory page corresponding to the identified memory address is used to determine the correct data. Because the memory device specifies the location of the corrupted data, and the size of the window where the corruption occurred, the stored hash can be used to verify memory page reconstruction. With the known good part of the data in hand, the hashes of the pages using possible values in place of the corrupted data are calculated. It is expected that there will be a match between the previously stored hash and one of the computed hashes. As long as there is one and only one match, then that value, used in the place of the corrupted data, is the correct value. The corrupt data, once replaced, allows operation of the memory device to continue without needing to interrupt or otherwise affect a system's operation.
    Type: Application
    Filed: December 11, 2009
    Publication date: June 16, 2011
    Applicant: VMWARE, INC.
    Inventors: Carl A. WALDSPURGER, Dilpreet BINDRA, Gregory HARM, Patrick TULLMANN
  • Publication number: 20110131443
    Abstract: A mechanism for automatic adjustment of virtual machine (VM) storage is disclosed. A method of embodiments of the invention includes stopping, by a host computing device, a virtual machine (VM) hosted by the host computing device from running upon detecting a write error due to lack of storage on the VM, communicating, by the host computing device, an out-of-storage notification from a hypervisor of the host computing device to a host management agent, and sending, by the host computing device, data associated with the out-of storage notification and the VM to a host controller that manages the host computing device, wherein the host controller causes storage for the VM to be increased.
    Type: Application
    Filed: November 30, 2009
    Publication date: June 2, 2011
    Inventors: Dor Laor, Shahar Frank, Uri Lublin, Avi Kivity, Gleb Natapov
  • Publication number: 20110126042
    Abstract: A method begins with a processing module sending a plurality of dispersed storage write commands to plurality of dispersed storage (DS) units for storing a plurality of encoded data slices. The method continues with the processing module receiving, within a time period, acknowledgements from at least some of the plurality of DS units to produce received acknowledgements. The method continues with the processing module determining whether a number of received acknowledgements compares favorably to a write threshold. The method continues with the processing module changing at least one of the write threshold and at least one of the plurality of DS units when the number of received acknowledgements does not compare favorably to the write threshold.
    Type: Application
    Filed: August 25, 2010
    Publication date: May 26, 2011
    Applicant: CLEVERSAFE, INC.
    Inventor: GREG DHUSE
  • Publication number: 20110113279
    Abstract: A redundant and fault tolerant solid state disk (SSDC) includes a determination module configured to identify a first SSDC configured to connect to a flash array and a second SSDC configured to connect to the flash array. A capture module is configured to capture a copy of an I/O request received by the first SSDC from a port of a dual port connector, and/or capture a copy of an I/O request received by the second SSDC from a port of the dual port connector, and identify a write I/O request from the I/O request. A detection module is configured to detect a failure in the first SSDC. A management module is configured to manage access to a flash array by the first SSDC and the second SSDC. An error recovery and failover module is configured to automatically reassign work from the first SSDC to the second SSDC.
    Type: Application
    Filed: November 12, 2009
    Publication date: May 12, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian J. Cagno, John C. Elliott, Gregg S. Lucas, Andrew D. Walls
  • Publication number: 20110107139
    Abstract: Example apparatus, methods, and computers prevent a split brain scenario in a pair of high availability servers by maintaining single writer access to a resource by controlling the resource according to a timer bounded arbitration protocol that controls self-termination of a writer process. One example method includes monitoring control of an arbitration (ARB) block by an active file system manager (FSM) and selectively causing a selection of a standby metadata controller (MDC) when control of the ARB block does not satisfy the timer bounded ARB protocol. The example method also includes selectively forcing a hardware reset of an apparatus running the active FSM and selectively establishing an FSM on a selected redundant MDC as a replacement FSM.
    Type: Application
    Filed: June 23, 2010
    Publication date: May 5, 2011
    Applicant: QUANTUM CORPORATION
    Inventors: William J. MIDDLECAMP, Tim LaBERGE, John REINART
  • Publication number: 20110078492
    Abstract: Methods and apparatus relating to home agent data and memory management are described. In one embodiment, a scrubber logic corrects an error at a location in a memory corresponding to a target address by writing back the corrected version of data to the target location. In an embodiment, a map out logic maps out an index or way of a directory cache in response to a number of errors, corresponding to the directory cache, exceeding a threshold value. Other embodiments are also disclosed.
    Type: Application
    Filed: September 30, 2009
    Publication date: March 31, 2011
    Inventors: Ganesh Kumar, Dheemanth Nagaraj, Vincent R. Freytag, Eric Delano, Gregory S. Averill