Access Processor Affected (e.g., I/o Processor, Mmu, Or Dma Processor, Etc.) Patents (Class 714/5.11)
-
Patent number: 11070420Abstract: A system for distributed device event handler configuration includes an event handler configuration server, including: a processor, a non-transitory memory, an input/output component, a visual program editor, a logical event model, and a device communicator; event management devices, each including: a hardware layer/operating system, a logical event mapping, a target compiler, a program executor; such that a configuration user can edit an event handling program, comprising event handlers, which handle device events on the event management devices; such that an event management device executes an event handler, when the event management device detects a device event, which corresponds with the event handler. Also disclosed is a method for distributed device event handler configuration, including editing an event handling program, updating devices, detecting a device event, and executing an event handler.Type: GrantFiled: September 13, 2019Date of Patent: July 20, 2021Assignee: PACIFIC TRACK, LLCInventors: Bernard O. Debbasch, Daniel P. Rothman
-
Patent number: 11068366Abstract: A device that provides power fail handling using command suspension includes non-volatile memory circuits and a controller that is configured to determine that a power fail event has occurred. The controller is configured to determine, in response to the determination that the power fail event has occurred, which of the non-volatile memory circuits are executing a first type of memory commands. The controller is also configured to issue a stop command to the determined non-volatile memory circuits to stop execution of the first type of memory commands.Type: GrantFiled: July 26, 2019Date of Patent: July 20, 2021Assignee: Western Digital Technologies, Inc.Inventors: YungLi Ji, Yuriy Pavlenko, Kum-Jung Song
-
Patent number: 11048600Abstract: Techniques for managing a storage system involve: in response to a storage device in a group of storage devices failing, determining multiple stripes in the storage system which are associated with the failed storage device; selecting a first storage device and a second storage device from the group of storage devices respectively, the first storage device and the second storage device being a first candidate and a second candidate of storage devices for rebuilding a first stripe and a second stripe among the multiple stripes to form a first rebuilt stripe and a second rebuilt stripe respectively; obtaining a coupling degree between the first rebuilt stripe and the second rebuilt stripe, the coupling degree describing a conflict degree of rebuilding the first stripe and the second stripe in parallel; and identifying the first candidate and the second candidate on the basis of the obtained coupling degree.Type: GrantFiled: January 17, 2019Date of Patent: June 29, 2021Assignee: EMC IP Holding Company LLCInventors: Baote Zhuo, Geng Han, Weihua Li, Xinlei Xu, Changyu Feng, Haiying Tang
-
Patent number: 11036584Abstract: A method includes, for a current phase of a multiple phase write operation to write a set of encoded data slices to a set of storage units, determining whether to send a write performance threshold number of write requests to a subset of the set of storage units regarding a write performance threshold number of encoded data slices of the set of encoded data slices, where the set of encoded data slices includes a total number of encoded data slices, and wherein the write performance threshold number is less than the total number and greater than or equal to the write threshold number. When the write performance threshold number of write requests is to be sent to the subset of the set of storage units, the method continues by sending the write performance threshold number of write requests to the subset of the set of storage units.Type: GrantFiled: July 30, 2019Date of Patent: June 15, 2021Assignee: Pure Storage, Inc.Inventors: Greg Dhuse, Jason K. Resch, Thomas Franklin Shirley, Jr.
-
Patent number: 11038637Abstract: A device that comprises a plurality of distributed transceivers, a central processor and a network management engine may be configured to function as relay device, relaying an input data stream from a source device to at least one other device. The relaying may include configuring one or more of the plurality of distributed transceivers to particular mode of relay operation and receiving the input data stream from the source device via at least one of the configured one or more of the plurality of distributed transceivers. The relaying may also include transmitting at least one relay data stream corresponding to the input data stream to the at least one other device, via at least one of the configured one or more of the plurality of distributed transceivers.Type: GrantFiled: June 25, 2019Date of Patent: June 15, 2021Assignee: GOLBA LLCInventor: Mehran Moshfeghi
-
Patent number: 10996871Abstract: An apparatus in one embodiment comprises at least one processing device comprising a processor coupled to a memory. The processing device is configured to detect an error relating to storage of a given data page in a first storage system, and to send a message to at least one additional storage system, the message containing a hash handle of the given data page with the hash handle having a length that is shorter than that of a corresponding hash digest of the given data page. The processing device is further configured to receive from the additional storage system responsive to the message a recovery data page identified by the additional storage system as having the same hash handle as the given data page. Separate instances of the message containing the hash handle of the given data page may be sent to each of a plurality of additional storage systems.Type: GrantFiled: November 1, 2018Date of Patent: May 4, 2021Assignee: EMC IP Holding Company LLCInventors: David Meiri, Anton Kucherov
-
Patent number: 10998923Abstract: The present disclosure includes apparatuses and methods related to stopping criteria for layered iterative error correction. A number of methods can include receiving a codeword with an error correction circuit, iteratively error correcting the codeword with the error correction circuit including parity checking the codeword on a layer-by-layer basis and updating the codeword after each layer. Methods can include stopping the iterative error correction in response to a parity check being correct for a particular layer.Type: GrantFiled: January 10, 2019Date of Patent: May 4, 2021Assignee: Micron Technology, Inc.Inventors: Mustafa N. Kaynak, William H. Radke, Patrick R. Khayat, Sivagnanam Parthasarathy
-
Patent number: 10977217Abstract: A method for managing storage devices includes, in response to a first determination that a first cloud storage device is inaccessible to a local storage device, obtaining metadata objects from a second cloud storage device, identifying, based on a sync time analysis, at least one metadata object of the metadata objects to be deleted, initiating the deletion of the at least one metadata object on a second cloud storage device, wherein the second cloud storage device is accessible to the local storage device, and updating, after initiating the deletion of the at least one metadata object, a namespace on a local storage device.Type: GrantFiled: October 31, 2018Date of Patent: April 13, 2021Assignee: EMC IP Holding Company LLCInventors: Neeraj Bhutani, Kalyan Chakravarthy Gunda, Nitin Madan, Jayasekhar Konduru
-
Patent number: 10970147Abstract: An abnormality determination means performs detection of abnormality of one of the pairs of detection means at a normal speed, and performs detection of abnormality of the other of the pairs at a speed not higher than the normal speed, and, when a sign of abnormality of the detection means is detected at the normal speed, a CPU performs switching to the other normal pair and continues control, and the abnormality determination means performs detection of abnormality of the other normal pair at the normal speed, and meanwhile, continues to perform detection of abnormality of the abnormal pair at a speed not higher than the normal speed.Type: GrantFiled: May 24, 2016Date of Patent: April 6, 2021Assignee: Mitsubishi Electric CorporationInventors: Eiji Iwami, Munenori Yamamoto
-
Patent number: 10970148Abstract: Embodiments of the present disclosure provide a method, device and computer program product for managing an input/output (I/O) stack. The method comprises obtaining metadata related to an I/O request stored in the I/O stack, the metadata at least comprising a timestamp when the I/O request is placed in the I/O stack; determining, based on the timestamp, a length of time during which the I/O request waits for processing; and in response to the length of time exceeding a threshold time length, performing a predetermined operation on the I/O request to prevent the I/O stack from being congested.Type: GrantFiled: October 22, 2018Date of Patent: April 6, 2021Assignee: EMC IP HOLDING COMPANY LLCInventors: Bing Liu, Man Lv
-
Patent number: 10958594Abstract: A network control system includes a network controller, and an information processor connected to the network controller via a first communication path complying with a first standard. The network controller is connected to an external device via an another communication path complying with the first standard. In response to receiving a packet from a transmission source that is registered in advance, the network controller transfers the packet to the information processor via the first communication path. When the packet transferred from the network controller is a special packet that is registered in advance, the information processor notifies the network controller of a content of an instruction indicated by the special packet via a second communication path. The network controller generates a special packet including the content of the instruction notified from the information processor, and transmits the generated special packet to the external device via the another communication path.Type: GrantFiled: February 13, 2019Date of Patent: March 23, 2021Assignee: Ricoh Company, Ltd.Inventor: Yoshihiro Kawashima
-
Patent number: 10929257Abstract: A method for defining local failover within a storage system using storage group containers includes creating a plurality set of storage groups from physical storage resources of a storage array of the storage system, and creating a masking view identifying a first subset of the storage groups and specifying that Thin Logical Units (TLUs) in the first subset of storage groups are visible only to a primary Software Defined Network Attached Storage (SDNAS) process executing on the storage system and to a backup SDNAS process executing on the storage system. The first set of storage groups includes a Virtual Data Mover (VDM) configuration/root TLU and all user data TLUs used by the primary SDNAS process to thereby enable the set of storage groups used by the SDNAS to be used as a container for local failover.Type: GrantFiled: January 31, 2019Date of Patent: February 23, 2021Assignee: EMC IP Holding Company LLCInventors: Ajay Potnis, Amit Dharmadhikari, Vijay Srinivasan
-
Patent number: 10891366Abstract: This disclosure provides techniques for recovering a root key from measurement of a circuit function. In some embodiments, a checkpointing feature is used to periodically mark measurements of this function and thereby track drift in the value of the root key over the life of a digital device; the checkpointing feature permits rollback of any measurement of the function in a manner that negates incremental drift and permits recovery of the root key for the life of a device (e.g., an IC circuit or product in which the IC is embedded). This disclosure also provides novel PUF designs and applications.Type: GrantFiled: August 11, 2018Date of Patent: January 12, 2021Assignee: JONETIX CORPORATIONInventors: Paul Ying-Fung Wu, Richard J. Nathan, Harry Leslie Tredennick
-
Patent number: 10884957Abstract: Techniques and mechanisms for performing in-memory computations with circuitry having a pipeline architecture. In an embodiment, various stages of a pipeline each include a respective input interface and a respective output interface, distinct from said input interface, to couple to different respective circuitry. These stages each further include a respective array of memory cells and circuitry to perform operations based on data stored by said array. A result of one such in-memory computation may be communicated from one pipeline stage to a respective next pipeline stage for use in further in-memory computations. Control circuitry, interconnect circuitry, configuration circuitry or other logic of the pipeline precludes operation of the pipeline as a monolithic, general-purpose memory device. In other embodiments, stages of the pipeline each provide a different respective layer of a neural network.Type: GrantFiled: October 15, 2018Date of Patent: January 5, 2021Assignee: Intel CorporationInventors: Amrita Mathuriya, Sasikanth Manipatruni, Victor W. Lee, Abhishek Sharma, Huseyin E. Sumbul, Gregory Chen, Raghavan Kumar, Phil Knag, Ram Krishnamurthy, Ian Young
-
Patent number: 10884843Abstract: In a system having at least two data storage and processing sites, each capable of alternatively serving as a primary site and a backup or target site, disaster recovery migration is optimized by cognitively analyzing at least one system parameter. Using machine learning, at least one pattern of that system related parameter is predicted, and planned or unplanned migration procedures are performed based on the predicted parameter patterns. The analyzed parameter may be data traffic at the sites, and the predicted data traffic pattern is used to assign primary and backup site status to those sites. The analyzed parameter may be the occurrence of events or transactions at the sites, and the predicted event or transaction patterns may be used to determine times of disaster recovery procedure processing so as to not interrupt a critical event or transaction.Type: GrantFiled: January 12, 2018Date of Patent: January 5, 2021Assignee: International Business Machines CorporationInventors: Jes Kiran Chittigala, Santhosh Joshi, Srirama R. Kucherlapati
-
Patent number: 10884888Abstract: A method, system and computer program product for facilitating communication among storage controllers of a storage system. The method comprises detecting an event indicative of status change in a storage system having a plurality of storage controllers; determining that it is needed to communicate the event from a first storage controller to a second storage controller of the storage controllers; transmitting a message about the event from the first storage controller to a host in response to failure of a dedicated link between the first storage controller and the second storage controller; and forwarding the message from the host to the second storage controller.Type: GrantFiled: January 22, 2019Date of Patent: January 5, 2021Assignee: International Business Machines CorporationInventors: Bo Zou, Yi Ning Chu, Chuan Li
-
Patent number: 10846234Abstract: A storage control system reads a data set from a storage apparatus if necessary in response to an I/O request. A data set contains data and an address. The storage control system performs an all-type address check which is a check to determine whether one of a first address and second address which correspond to a read-target data set in address translation information, which is information indicating a mapping relationship between one or more first addresses and one or more second addresses, matches the address among the data and address contained in the data set. The one or more first addresses are each an address which belongs to the first address type. The one or more second addresses are each an address which belongs to the second address type. The storage control system performs processing according to the I/O request when the result of the all-type address check is true.Type: GrantFiled: March 15, 2019Date of Patent: November 24, 2020Assignee: HITACHI, LTD.Inventors: Yusuke Saito, Toshiya Seki, Eiju Katsuragi, Yutaka Ohshima, Katsuya Sato, Noboru Morishita, Yoshihiro Yoshii
-
Patent number: 10725879Abstract: A storage apparatus includes a plurality of resources including a plurality of types of surplus resources, determines a surplus resource introduction plan used for coping with abnormalities, and controls allocation of the surplus resources according to the determined introduction plan. The storage apparatus includes a processor. The processor detects an abnormality associated with the resource of the storage apparatus, calculates one or more surplus resource introduction plans capable of coping with the abnormality on the basis of management information of the resource of the storage apparatus when the abnormality is detected, and determines, when there are a plurality of introduction plans, an introduction plan used for coping with the abnormality on the basis of a state in which other abnormalities that are likely to occur concurrently with the abnormality can be coped with, by surplus resources remaining when the introduction plans are executed.Type: GrantFiled: August 31, 2018Date of Patent: July 28, 2020Assignee: Hitachi, Ltd.Inventors: Yuta Nishihara, Takashi Watanabe, Shiori Inoue
-
Patent number: 10691545Abstract: A method, computer program product, and system includes a processor(s) progressively recording data modifications to an object (e.g., a virtual resource or a container), in an in-memory resource of the shared computing environment. Based on receiving an indication of a system failure or a system reboot, the processor(s) writes the data modifications to a non-volatile storage resource, where the non-volatile storage resource is readable by an object manager communicatively coupled to the non-volatile storage resource, and where the object manager utilizes the data modifications to recover the object at reboot following the system failure.Type: GrantFiled: July 17, 2019Date of Patent: June 23, 2020Assignee: International Business Machines CorporationInventors: Shashidhar Bomma, Neeraj Kumar Kashyap, Ginni Gidwani, Pramod V. Gavali
-
Patent number: 10691544Abstract: A method, computer program product, and system includes a processor(s) progressively recording data modifications to an object (e.g., a virtual resource or a container), in an in-memory resource of the shared computing environment. Based on receiving an indication of a system failure or a system reboot, the processor(s) writes the data modifications to a non-volatile storage resource, where the non-volatile storage resource is readable by an object manager communicatively coupled to the non-volatile storage resource, and where the object manager utilizes the data modifications to recover the object at reboot following the system failure.Type: GrantFiled: November 21, 2017Date of Patent: June 23, 2020Assignee: International Business Machines CorporationInventors: Shashidhar Bomma, Neeraj Kumar Kashyap, Ginni Gidwani, Pramod V. Gavali
-
Patent number: 10678640Abstract: A computer readable storage medium includes memory sections that store operational instructions, the when executed by one or more computing devices of a dispersed storage network (DSN), cause the one or more computing devices to perform the following for a data access request. The computing device(s) access a plurality of estimated efficiency models of a plurality of dispersed storage (DS) processing units of the DSN. The computing device(s) select one of the DS processing units based on the plurality of estimated efficiency models, a type of request, and a randomizing factor. The computing device(s) send the data access request to the selected DS processing unit for execution. The computing device(s) determine an actual processing efficiency of the processing of the data access request by the selected DS processing unit and update the estimated efficiency model of the selected DS processing module based on the actual processing efficiency.Type: GrantFiled: January 24, 2019Date of Patent: June 9, 2020Assignee: PURE STORAGE, INC.Inventors: Ravi V. Khadiwala, Jason K. Resch
-
Patent number: 10679217Abstract: Examples of methods and devices for sending transaction information and performing consensus verification are described. In one example of the methods, a first consensus node receives transaction information and sends the transaction information to a second consensus node. The first consensus node receives a consensus verification failure notification from the second consensus node. The consensus verification failure notification includes an information identifier of the transaction information. In response to receiving the consensus verification failure notification, the first consensus node resends the transaction information to the second consensus node based at least on the consensus verification failure notification.Type: GrantFiled: July 26, 2019Date of Patent: June 9, 2020Assignee: Alibaba Group Holding LimitedInventor: Ning Li
-
Patent number: 10665319Abstract: Approaches for testing memory devices, such as DRAMs, are described that can quickly identify various potential storage issues. The memory space for a device can be divided into subspaces that can be tested concurrently. A starting address is determined for each memory sub-space, and addresses are identified that are within a Hamming distance of the starting address, where a single Hamming distance or multiple Hamming distances can be used. Once a list of addresses is generated, a test pattern can be written to, and read from, the corresponding addresses. Differences from the expected pattern can be indicative of problems with the memory device, whether before user deployment or while storing live data. If there are specific problems suspected, targeted testing can be utilized that does not test the entirety of the memory space.Type: GrantFiled: September 20, 2018Date of Patent: May 26, 2020Assignee: AMAZON TECHNOLOGIES, INC.Inventors: Alex Levin, Ron Diamant, Georgy Zorik Machulsky
-
Patent number: 10620856Abstract: Example methods are provided for a first host to perform Input Output (I/O) fencing in a shared virtual storage environment. One example method may comprise determining that is required to fence off a second node from a first virtual disk, and obtaining persistent reservation information associated with the first virtual disk. The persistent reservation information may include a first key associated with a first path between a first node and the first virtual disk, and a second key associated with a second path between the second node and the first virtual disk. The method may also comprise identifying the second key associated with the second path; and blocking I/O access by the second node to the first virtual disk using the second key associated with the second path, thereby fencing off the second node from the first virtual disk.Type: GrantFiled: April 18, 2018Date of Patent: April 14, 2020Assignee: VMWARE, INC.Inventors: Rahul Dev, Gautham Swamy
-
Patent number: 10599510Abstract: A computer system comprises a computer being coupled to a device via a device interface. The device interface has an error status register and a link status register. An error isolation unit periodically obtains values of the error status register and the link status register. The error isolation unit determine whether an error occurs in the device; determine whether the error is an error to be isolated; determine whether the error is an error to be isolated based on values of the error status register and the link status register re-obtained after elapse of a predetermined time in a case of determining the error is not to be isolated. The error isolation unit detects the error as an error of a protocol caused by stop of a power supply in a case of determining the error is to be isolated.Type: GrantFiled: July 8, 2015Date of Patent: March 24, 2020Assignee: HITACHI, LTD.Inventors: Ken Sugimoto, Yusuke Funaya
-
Patent number: 10592296Abstract: A method, apparatus and computer program product that allows for maintaining correct states of all sub-components in a state machine, even as sub-components leave the state machine and later rejoin in some previous state. Preferably, this is achieved without requiring the system to remember the states of all sub-components or a log of every event that was fed into the state machine. Thus, the technique does not require any knowledge of the previous state of the sub-components nor the need to preserve a complete log of events that were fed into the state machine. The state machine may be used to enhance the operation of a technological process, such as a workload management environment.Type: GrantFiled: March 7, 2017Date of Patent: March 17, 2020Assignee: International Business Machines CorporationInventors: Michael Gerard Fitzpatrick, Andrew Hilliard Arrowood, Gary Owen McAfee, Sue L. Huang
-
Patent number: 10592432Abstract: Provided are a computer program product, system, and method for adjusting active cache size based on cache usage. An active cache in at least one memory device caches tracks in a storage during computer system operations. An inactive cache in the at least one memory device is not available to cache tracks in the storage during the computer system operations. During caching operations in the active cache, information is gathered on cache hits to the active cache and cache hits that would occur if the inactive cache was available to cache data during the computer system operations. The gathered information is used to determine whether to configure a portion of the inactive cache as part of the active cache for use during the computer system operations.Type: GrantFiled: August 3, 2018Date of Patent: March 17, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin J. Ash, Matthew G. Borlick, Lokesh M. Gupta, Will A. Wright
-
Patent number: 10587687Abstract: Methods, apparatus, and computer-accessible storage media for providing redundant storage gateways. A client may create a storage gateway group and add storage gateways to the group. The client may assign one or more volumes on a remote data store to each the storage gateways in the group. Volume data for each storage gateway in the group may be replicated to at least one other storage gateway in the group. If one of the gateways in the group becomes unavailable, one or more other gateways in the group may take over volumes previously assigned to the unavailable gateway, using the replicated data in the group to seamlessly resume gateway operations for the respective volumes. Client processes that previously communicated with the unavailable gateway may be manually or automatically directed to the gateway(s) that are taking over the unavailable gateway's volumes.Type: GrantFiled: July 28, 2014Date of Patent: March 10, 2020Assignee: Amazon Technologies, Inc.Inventors: James Christopher Sorenson, III, Yun Lin
-
Patent number: 10585592Abstract: Embodiments of the present disclosure provide a disk area isolation method, where the method includes: receiving, by a file system, a request for access to a file, where the access includes file reading or file writing; determining a to-be-accessed data block according to the request; accessing a physical area corresponding to the data block on a disk; identifying, according to a time consumed for accessing the physical area, whether the data block is located in a low-speed area on the disk; and isolating the data block that is identified to be located in the low-speed area.Type: GrantFiled: February 28, 2017Date of Patent: March 10, 2020Assignee: Huawei Technologies Co., Ltd.Inventors: Jiangang Shen, Yaohui Li
-
Patent number: 10585767Abstract: Provided is a method for correcting pinned data in a primary storage. A primary storage controller may detect a pinned data set on a primary storage. In response to detecting the pinned data set, the primary storage controller may instruct a secondary storage controller to transmit a copy of the pinned data set to the primary storage controller. The copy of the pinned data set may be stored in a secondary storage that is communicatively coupled to the secondary storage controller. The secondary storage may include a synchronous copy of the primary storage. The primary storage controller may receive the copy of the pinned data set from the secondary storage controller. The primary storage controller may also write the copy of the pinned data set over the pinned data set on the primary storage.Type: GrantFiled: February 7, 2018Date of Patent: March 10, 2020Assignee: International Business Machines CorporationInventors: William J. Rooney, Tabor R. Powelson, David R. Blea, Gregory E. McBride, Dale F. Riedy, Carol S. Mellgren
-
Patent number: 10579558Abstract: A redundancy termination panel includes first and second interfaces configured to be coupled to first and second I/O modules, respectively. The redundancy termination panel also includes a third interface configured to be coupled to a field device. The redundancy termination panel further includes an I/O channel circuit associated with an I/O channel between the I/O modules and the field device. The I/O channel circuit is configured to allow an input current used for receiving data from the field device to be split such that different portions of the input current are sourced by different ones of the I/O modules. The I/O channel circuit is also configured to combine multiple currents driven by different ones of the I/O modules and provide an output current used for sending data to the field device.Type: GrantFiled: March 6, 2019Date of Patent: March 3, 2020Assignee: Honeywell International Inc.Inventors: Nagaraja Sundaresh, Vamsee Krishna Aradhyula, Ram Mohan Anugu, Shripad Kumar Pande
-
Patent number: 10581711Abstract: System and method for policing logical network traffic flows using a ternary content addressable memory (TCAM). An exemplary embodiment can provide a network port that is associated with a plurality of entries of a TCAM, where each TCAM entry contains a value. Further, each TCAM entry can be assigned a priority and associated with at least one allow/drop action. A predefined set of values can be retrieved from at least one header field of a data packet processed by the network port. Each value in the predefined set of values can be aggregated into a search value, and the search value can be compared to the value contained in each TCAM entry. When a match is found between the search value and the value contained in a TCAM entry, the allow/drop action associated with the matching TCAM entry can be performed.Type: GrantFiled: January 24, 2017Date of Patent: March 3, 2020Assignee: ORACLE INTERNATIONAL CORPORATIONInventors: Bjørn Dag Johnsen, Arvind Srinivasan
-
Patent number: 10545825Abstract: Various implementations disclosed herein provide fault-tolerant enterprise object storage system that can store small objects. In various implementations, the fault-tolerant enterprise object storage system writes a small object into an aggregate object that is distributed across a plurality of storage entities. In some implementations, the small object is at least an order of magnitude smaller than the aggregate object, and the small object is within the same order of magnitude of a block unit addressable within each of the storage entities. In some implementations, based on the small object, the storage system updates the parity data associated with the aggregate object in response to writing the small object into the aggregate object. In various implementations, the storage system updates a processed data end offset indicator that indicates that the parity data for the aggregate object includes valid data up to and including the small object.Type: GrantFiled: July 12, 2016Date of Patent: January 28, 2020Assignee: Synamedia LimitedInventors: Vandana Shyam Rungta, Dana Marlow Henriksen, Mel J. Oyler, Kevin Wayne Kingdon
-
Patent number: 10503595Abstract: A method begins by receiving a storage request to store one or more portions of a data object and determining whether the one or more portions are stored within a dispersed storage network memory. When stored, the method continues by determining a retrieval demand for a portion of the one or more portions. When below a first threshold, the method continues by indicating that an existing copy of the one or more portions will be used for retrieval requests for the one or more portions. When above the first threshold, the method continues by copying the existing copy to create a first one or more portion copies and indicating the one or more portions will be used for retrieval requests from a first group of user computing devices and indicating the first one or more portion copies will be used for retrieval requests from a second group.Type: GrantFiled: September 27, 2018Date of Patent: December 10, 2019Assignee: PURE STORAGE, INC.Inventors: Teague S. Algie, Praveen Viraraghavan
-
Patent number: 10496504Abstract: Data storage systems are provided that include network interfaces each configured to receive storage operations issued by one or more host systems for handling by the data storage system, and transfer the storage operations over a Peripheral Component Interconnect Express (PCIe) fabric. The data storage systems also include processors configured to receive the storage operations over the PCIe fabric, process properties of the storage operations against allocation information of a shared PCIe address space to determine target processors to handle the storage operations, and selectively transfer ones of the storage operations to the target processors for handling of the storage operations with associated storage drives coupled over the PCIe fabric. The data storage systems also identifie failed ones of the processors and responsively initiate backup ones of the processors to handle portions of the shared PCIe address space handled by the failed ones of the processors.Type: GrantFiled: June 16, 2017Date of Patent: December 3, 2019Assignee: Liqid Inc.Inventors: Jason Breakstone, Christopher R. Long, James Scott Cannata
-
Patent number: 10489321Abstract: An aspect of performance improvement for an active-active distributed non-ALUA (asymmetrical logical unit assignment) system with address ownerships includes receiving an input/output (IO) by a host computer; accessing, by the host computer, an address-to-compute module (a?c) table; and determining, from the table, a target location of the IO request. The target location specifies an address. An aspect further includes determining an address owner of a storage controller port of a storage controller that owns the address of the IO, selecting a path associated with the address owner, and transmitting the IO request to the storage controller port.Type: GrantFiled: July 31, 2018Date of Patent: November 26, 2019Assignee: EMC IP Holding Company LLCInventors: Amitai Alkalay, Zvi Schneider, Assaf Natanzon
-
Patent number: 10482056Abstract: Systems and methods to transfer master duties to a slave on a communication bus are disclosed. A master of a communication bus determines that one or more slaves are capable of serving as a sub-master, including providing a clock signal and owning control information bits. Once that determination is made, the master may determine that processing within the master is not required for a particular activity on the bus. The master then alerts one such capable slave to prepare to assume sub-master duties. Once the slave confirms that the slave is ready to assume the sub-master duties, the master may transmit a handover frame on the bus, and the slave begins acting as a sub-master. The master may then enter a low-power state, which may promote power savings, reduce heat generation, and provide other advantages.Type: GrantFiled: November 21, 2017Date of Patent: November 19, 2019Assignee: QUALCOMM IncorporatedInventors: Lior Amarilio, Yuval Corey Hershko, Nir Strauss
-
Patent number: 10482045Abstract: Improvements over existing data collection interfaces disclosed herein include, among other things, additional logic blocks (and associated timers, state machines, and registers) to off-load data collection and data processing prior to waking a microprocessor from a sleep mode. For example, an improved data collection interface collects a predetermined number of sensor values from a sensor while maintaining active a single communication session with the sensor over a pin of the interface. The microprocessor remains in the sleep mode for an entire duration of the single communication session. The data collection interface can reduce the likelihood of false starts of the microprocessor by using the logic blocks to verify that data meet preconditions prior to interrupting the microprocessor. The data collection interface can reduce the overall power consumption of a chip in which the microprocessor is integrated by a factor of at least about 2× (i.e., 50% reduction in power consumption).Type: GrantFiled: June 20, 2016Date of Patent: November 19, 2019Assignee: ANALOG DEVICES GLOBAL UNLIMITED COMPANYInventors: Mohamed Farook Basheer Ahamed, Michael Martin McCarthy, Aravind K. Navada
-
Patent number: 10474531Abstract: A processing device has a memory including a plurality of storage areas each storing a setting value and the correction frequency change unit. The correction frequency change unit is configured to decrease, when a frequency of correction by the error correction unit for a storage area that stores one of the setting values is changed to a high frequency, a frequency of correction by the error correction processing for one of the storage areas other than the storage area whose correction frequency is changed to a high frequency, and to increase, when a frequency of correction by the error correction unit for a storage area that stores one of the setting values is changed to a low frequency, a frequency of correction by the error correction processing for one of the storage areas other than the storage area whose correction frequency is changed to a low frequency.Type: GrantFiled: January 11, 2018Date of Patent: November 12, 2019Assignee: FUJITSU OPTICAL COMPONENTS LIMITEDInventor: Daisuke Matsukawa
-
Patent number: 10452468Abstract: The subject technology provides for managing a data storage system. A data operation error for a data operation initiated in a first non-volatile memory die of a plurality of non-volatile memory die in the data storage system is detected. An error count for an error type of the data operation error for the first non-volatile memory die is incremented. The incremented error count satisfies a first threshold value for the error type of the data operation error is determined. The first non-volatile memory die is marked for exclusion from subsequent data operations.Type: GrantFiled: December 30, 2016Date of Patent: October 22, 2019Assignee: Western Digital Technologies, Inc.Inventors: Sanghoon Chu, Scott Jinn, Yuriy Pavlenko, Kum-Jung Song
-
Patent number: 10452498Abstract: A computing system can include a processor and a persistent main memory including a fault tolerance capability. The computing system can also include a memory controller to store data in the persistent main memory and create redundant data. The memory controller can also store the redundant data remotely with respect to the persistent main memory. The memory controller can further access the redundant data during failure of the persistent main memory.Type: GrantFiled: June 28, 2013Date of Patent: October 22, 2019Assignee: Hewlett Packard Enterprise Development LPInventors: Gregg B. Lesartre, Dale C. Morris, Gary Gostin, Russ W. Herrell, Andrew R. Wheeler, Blaine D. Gaither
-
Patent number: 10437632Abstract: A method and an apparatus execute a non-maskable interrupt. The method includes: obtaining a secure interrupt request in a non-secure mode, and interrupting an operation of an operating system OS, where the secure interrupt request cannot be masked; entering a secure mode by using the secure interrupt request, and saving, in the secure mode, an interrupt context of an OS status when the operation of the OS is interrupted; returning to the non-secure mode to execute user-defined processing; after the user-defined processing is completed, entering the secure mode again, and resuming the OS status in the secure mode according to the interrupt context; and returning to the non-secure mode again, and continuing to execute an operation of the OS. The method and the apparatus for executing a non-maskable interrupt in embodiments of the present invention can easily implement an NMI mechanism without depending on hardware.Type: GrantFiled: April 6, 2018Date of Patent: October 8, 2019Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Jun Ma, Tianhong Ding, Zhaozhe Tong
-
Patent number: 10430261Abstract: The subject matter described herein is generally directed towards detection and remediation of virtual computing instance (VCI) failure on host devices. Monitoring is performed to detect suspected failures of different guest operating systems, identify failure information, and perform remediation to provide high availability for the VCI.Type: GrantFiled: August 15, 2017Date of Patent: October 1, 2019Assignee: VMware, Inc.Inventors: Keith Farkas, Kevin Scott Christopher, Aalap Desai, Manoj Krishnan, Jesse Andrew Mendonca, Rohan Patil
-
Patent number: 10419527Abstract: The described herein relates to repairing a file system. Repairing the file system includes identifying a corrupted node of a tree corresponding to the file system and determining a status of a parent node of the corrupted node based on a status bit of the parent node. Repairing the file system also includes disabling the parent node to an off-line mode when the status bit indicates that the parent node is in an on-line mode; fixing the corrupted node while the parent node is in the off-line mode; and enabling the parent node to the on-line mode in response to fixing the at least one corrupted node.Type: GrantFiled: June 8, 2016Date of Patent: September 17, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Asmahan A. Ali, Ali Y. Duale, Mustafa Y. Mah
-
Patent number: 10412152Abstract: The described herein relates to repairing a file system. Repairing the file system includes identifying a corrupted node of a tree corresponding to the file system and determining a status of a parent node of the corrupted node based on a status bit of the parent node. Repairing the file system also includes disabling the parent node to an off-line mode when the status bit indicates that the parent node is in an on-line mode; fixing the corrupted node while the parent node is in the off-line mode; and enabling the parent node to the on-line mode in response to fixing the at least one corrupted node.Type: GrantFiled: November 24, 2015Date of Patent: September 10, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Asmahan A. Ali, Ali Y. Duale, Mustafa Y. Mah
-
Patent number: 10379979Abstract: A device that provides power fail handling using command suspension includes non-volatile memory circuits and a controller that is configured to determine that a power fail event has occurred. The controller is configured to determine, in response to the determination that the power fail event has occurred, which of the non-volatile memory circuits are executing a first type of memory commands. The controller is also configured to issue a stop command to the determined non-volatile memory circuits to stop execution of the first type of memory commands.Type: GrantFiled: May 31, 2017Date of Patent: August 13, 2019Assignee: Western Digital Technologies, Inc.Inventors: YungLi Ji, Yuriy Pavlenko, Kum-Jung Song
-
Patent number: 10289321Abstract: Spatially coupled journals include information for every portion of physical media, including defective, or “bad”, blocks. Because data cannot be stored to bad blocks, a bad block table is needed before a solid state drive (SSD) can be accessed. Using the information already stored in the journals, the bad block table can be rebuilt following a loss of power. To ensure the journals can be located, a small seed can be stored in off band storage. The seed can include information pointing to a boot catalog stored on the SSD. The boot catalog can be used to determine the locations of journals, which may vary from their predetermined locations depending on the bad blocks of the drive. By storing a small seed, rather than an entire bad block table, the size of external storage needed to maintain the bad block table is reduced.Type: GrantFiled: May 5, 2017Date of Patent: May 14, 2019Assignee: AMAZON TECHNOLOGIES, INC.Inventors: Leonid Baryudin, Phillip Peterson, Daniel Sladic
-
Patent number: 10289482Abstract: A memory device includes a semiconductor memory unit and a controller circuit configured to communicate with a host through a serial interface and access the semiconductor memory unit in response to commands received through the serial interface. The controller circuit, in response to a host command to read parameters of the memory device, updates at least one of parameters of the memory device stored in the memory device based on operational settings of the memory device, and transmits the updated parameters through the serial interface to the host.Type: GrantFiled: March 4, 2016Date of Patent: May 14, 2019Assignee: Toshiba Memory CorporationInventors: Shunsuke Kodera, Toshihiko Kitazume, Kenichirou Kada, Nobuhiro Tsuji, Shinya Takeda, Tetsuya Iwata, Yoshio Furuyama, Hirosuke Narai
-
Patent number: 10282274Abstract: Presenting differences between code entity invocations includes identifying a plurality of families of invocations of a code entity. Each family is defined based upon a plurality of attributes that identify a class of runtime behavior of the code entity. First attribute(s) of a first family are identified. These first attribute(s) substantially contributed to classifying a first class of invocations of the code entity within the first family. Similarly, second attribute(s) of a second family are identified. These second attribute(s) substantially contributed to classifying a second class of invocations of the code entity within the second family. Differences between at least two invocations of the code entity are presented, based on differences between the one or more first attributes and the one or more second attributes.Type: GrantFiled: June 14, 2017Date of Patent: May 7, 2019Assignee: Microsoft Technology Licensing, LLCInventor: Jordi Mola
-
Patent number: 10282564Abstract: A data segment is encrypted to produce an encrypted data segment. The encrypted data segment is dispersed storage error encoded to produce a set of encoded data slices. Auxiliary data is dispersed storage error encoded to produce a set of encoded auxiliary data slices. A sequence of output slices is generated to obscure the set of encoded data slices by interspersing the set of encoded auxiliary data slices within the set of encoded data slices.Type: GrantFiled: August 5, 2014Date of Patent: May 7, 2019Assignee: International Business Machines CorporationInventors: S. Christopher Gladwin, Chuck Wilson Templeton, Jason K. Resch, Gary W. Grube