Abstract: An ECU is equipped with an engine control microcomputer for executing engine control and a throttle control microcomputer for executing throttle control. The engine control microcomputer is programmed to execute a monitor program. A time in the engine control microcomputer is set with a predetermined time each time the monitor program is executed normally. The timer switches automatically its output logic level at a port from high to low, when the time count reaches zero. When the output logic level is switched to low, a throttle motor is disabled.

Abstract: A novel boot method for a system, whose system BIOS has been disabled by erroneous microcode input as the result of inadvertent miscoding or malicious intent. The keyboard BIOS of the system is utilized in the present invention. If the CPU of the computer crashes during a microcode update, the system notes the error (setting a number of flags) and restarts the computer. The restarted system will not perform the microcode update, but goes straight to the normal BIOS activation, avoiding the crash problem. To fix the problem, users need only request the correct microcode from CPU retailers to amend the errors in the BIOS.

Abstract: The present invention provides a system and method of adjusting a heartbeat timeout utilized for monitoring a process in a distributed system. The distributed system includes a plurality of processes monitoring one another by transmitting messages (i.e., heartbeats) indicative of a process being operational. A first process monitoring a second process is operable to receive one or more heartbeats from the second process in the distributed system. If the first process fails to receive a heartbeat from the second process prior to an expiration of the heartbeat timeout, the second process is suspected of failing. If the first process receives a heartbeat from the second process prior to the expiration of the heartbeat timeout, the first process recalculates the heartbeat timeout. Recalculating the heartbeat timeout includes gradually increasing or decreasing the heartbeat timeout based on a period of time to receive a heartbeat.

Abstract: The present invention provides a system and method of detecting a process failure and a network failure in a distributed system. The distributed system includes at least two processes, each executing on a host, operable to transmit messages (i.e., heartbeats) to each other on a plurality of networks in the distributed system. A process in the system is operable to execute a network failure algorithm for detecting failure of a network in the system. The process failure algorithm includes calculating a difference in the period of time to receive a heartbeat on a first network from a process and a period of time to receive a heartbeat on a second network from the process. If the difference exceeds a network failure threshold, the second network is suspected of failing. A process in the system is also operable to execute a process failure algorithm.

Abstract: An electronic control unit includes a microcomputer and an input interface circuit. The microcomputer has square wave input ports, a reference square wave input port, a serial communication port, and an output port. Square wave signals are inputted from sensors to four channels of the input interface circuit. A channel selector included in the input interface circuit the selects square wave signals in orderly sequence for capturing. The microcomputer performs a comparison between a time at which the square wave is captured and a time at which the selected square wave signal is captured for diagnosing operation of an input capturing function.

Abstract: A device for monitoring a processor is described. A watchdog simultaneously monitors the system clock, the software base functions and performs a check of the tests of the system components of the processor. If an error is detected, the watchdog communicates this to the processor, an error counter is incremented and at least one device that is connected to the processor is blocked. If the error counter attains a predetermined value, the block is continued until the device of the present invention is deactivated. If an additional error is detected during a blocking time, the blocking time is extended.

Abstract: A method and apparatus to generate test sequences for pipeline hazards in a pipelined data processing system is presented. An executable specification for the architecture is compiled that includes macroarchitecture and microarchitecture information corresponding to each of the instructions supported by the architecture. A table (20) is constructed from the executable specification that specifies the particular resource utilization parameters associated with each of the instruction types included in the instruction set supported. From this table a resource utilization parameter list (30) is compiled that indicates the relative times at which resources are needed by each instruction and when these resources are released by the instruction. Comparisons between different entries in the resource utilization parameter list corresponding to the same resource are performed such that potential hazards are detected.

Abstract: A method and apparatus for identifying and detecting hazards is presented. An executable specification for the architecture is compiled that includes macroarchitecture and microarchitecture information corresponding to each of the instructions supported by the architecture. A table (20) is constructed from the executable specification that specifies the particular resource utilization parameters associated with each of the instruction types included in the instruction set supported. From this table a resource utilization parameter list (30) is compiled that indicates the relative times at which resources are needed by each instruction and when these resources are released by the instruction. Comparisons between different entries in the resource utilization parameter list corresponding to the same resource are performed such that potential hazards are detected.

Abstract: A method for adjusting failover intervals in a computer network is provided. In one embodiment of the present invention transport protocol requests are sent to a backup server, receiving response messages from the server, and then the rate of transport protocol requests is adjusted according to the response messages.

Abstract: An on-chip watchdog circuit (100) is provided that generates an output signal (175) when an error signal (112) generated by a circuit under test (110) is detected. The on-chip watchdog circuit (100) comprises a logic gate (125) that is connected to a clock signal and receives a signal in response to the error signal 112 generated by the circuit under test (110). A gate output circuit (140) is connected to an output of the logic gate (125). An RC circuit (150) is connected to the gate output circuit (140). A comparator (170) is connected to the RC circuit (150). The comparator (170) is also connected to a voltage divider (160) and provides the output signal (175) in response to the error signal (112) generated by the circuit under test (110), and the on-chip watchdog circuit (100) and the circuit under test (110) are integrated on a same semiconductor microchip.

Abstract: A hybrid multiple redundant computer system having redundant input modules, central processor modules, and output modules operating in parallel, where output circuits within each output module are connected to associated microcontrollers, such that, a first output circuit is connected to a first and a third microcontroller, a second output circuit is connected to a second and the first microcontroller, and a third output circuit is connected to the third and the second microcontroller; each output module further comprising watchdog controllers for detecting faults within the microcontrollers or central processing modules, where the watchdog controllers produce alarm signals upon detection of a failure within these components; the output circuits further including means for providing a 2-of-3 vote among data produced by three central processor modules if alarm signals are not activated and for reverting to a 2-of-2 and 1-of-1 vote in the presence of one and two faulty components respectively.

Abstract: An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayered substrate. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the surface of the insulating layer, in order to use a portion of the multilayer wiring substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground.

Abstract: 1. Method for operating a system controlled by a processor.

Abstract: In an information processing system, a failed bus operation is detected. In response to the detecting, a primary power plan is cycled in the information processing system.

Abstract: An apparatus and method for monitoring the state of a computer system running multiple operating systems shared by a partition manager is provided. A dedicated service processor monitors the individual run state condition of a plurality of processors running a plurality of operating systems. The service processor executes a routine to poll a memory location in each processor in the system to determine if the processor has entered an error loop with interrupts disabled. If any one of the plurality of processors are in an error loop, the service processor executes a routine to send a non-maskable interrupt to the looped processor so that the partition manager may regain control of the processor.

Abstract: A computer system comprising a first computer coupled to a primary PCI bus via a first PCI bus switch and a second computer coupled to the primary PCI bus via a second PCI bus switch. A monitor system is coupled to both the first and second computers as well as the first and second PCI bus switches. In the event of a malfunction in the first computer, the monitor system decouples the first computer from the primary PCI bus, by opening the first PCI bus switch and coupling the second computer to the primary PCI bus by closing the second PCI bus switch.

Abstract: A fault of an operating system (hereafter referred to as “OS”) is observed without adding dedicated hardware. Besides AP fault monitoring, check-point information is preserved at high speed without adding dedicated hardware. In a computer having a multi-OS environment, an AP fault monitor and a monitored AP operate on a first OS. A fault monitor operates on a second OS. Each of the first OS and the AP fault monitor transmits an alive message to the fault monitor by utilizing an inter-OS communication function of a multi-OS controller. The fault monitor monitors the alive message of each of the first OS and the AP fault monitor. The monitored AP transmits an alive message to the AP fault monitor. The AP fault monitor monitors it. The monitored AP preserves check-point information in a region of a memory. In the region of the memory, information is preserved by a fault and restart of the first OS as well.

Abstract: A microprocessor based system, such as a Personal Computer (PC), server, router, word processor or like devices, includes circuit arrangement that monitors the processor for a heartbeat pulse. If the heartbeat pulse is not sensed within a specified time interval the circuit arrangement issues a Soft Reset signal (Unmasked Interrupt) that causes the microprocessor to execute a program that logs the current state of selected entities within the system and a Hard Reset Pulse that resets the system hardware. The log can be used to identify the cause of a problem, whereas the Hard Reset causes the system to reboot and continue normal operation.

Abstract: A session manager has a session timeout mechanism to selectively timeout client-server sessions. The session timeout mechanism has multiple timeout buckets to hold corresponding groups of sessions according to the sessions' timeout periods. Sessions located in different ones of the timeout buckets are set to timeout at different times. The session manager also has a session timeout clock that is incremented every predetermined time unit (e.g., every minute). The session timeout clock maintains a pointer to one of the timeout buckets and advances that pointer with each clock increment. The session timeout clock advances the pointer through all of the timeout buckets, one bucket at a time. The session timeout clock advances the pointer repeatedly through all the buckets. The cycle time for the session timeout clock to reference every timeout bucket is equal to the incremental time unit multiplied by the number of buckets.

Abstract: Systems and methods for efficiently and accurately determining a speed of a faster clock having unknown frequency using a slower clock having a known frequency. A series of measurement pairs are taken from the clocks; each measurement pair including one measurement from the slower clock and one measurement—at the same time—from the faster clock. A lower bound and an upper bound for the measurement pairs are determined. The lower bound and the upper bound are averaged to derive a calibration variable that indicates a number of clock cycles that occur on the faster clock during one cycle of the slower clock. The calibration variable is used to time various processes in a computer system.

Abstract: The electronic chip (10) comprises an interface (11) enabling it to communicate with a terminal and a processing circuit (13) capable of performing processing when the chip communicates with the terminal. A time base circuit (18) is connected to the processing circuit (13) for generating a first signal (SI) during at least one given moment if processing has not yet been completed at said moment. A restart signal (SR) is transmitted to the interface in response to the first signal with the purpose of indicating to the terminal that the chip is still operating.

Abstract: A multi-processor computer system permits various types of partitions to be implemented to contain and isolate hardware failures. The various types of partitions include hard, semi-hard, firm, and soft partitions. Each partition can include one or more processors. Upon detecting a failure associated with a processor, the connection to adjacent processors in the system can be severed, thereby precluding corrupted data from contaminating the rest of the system. If an inter-processor connection is severed, message traffic in the system can become congested as messages become backed up in other processors. Accordingly, each processor includes various timers to monitor for traffic congestion that may be due to a severed connection. Rather than letting the processor continue to wait to be able to transmit its messages, the timers will expire at preprogrammed time periods and the processor will take appropriate action, such as simply dropping queued messages, to keep the system from locking up.

Abstract: A method and apparatus for monitoring the response times of computer system components in order to improve computer system reliability and performance are provided. The method and apparatus are particularly applicable to computer systems with memory circuits, such as SLDRAMs, that have programmable response times. A response time monitoring circuit in the form of a phase detector includes a plurality of flip-flops with the data inputs commonly connected to receive a response ready signal from a component, such as a memory circuit, in response to a command to perform a task. Each clock input of the flip-flop is connected to a clock signal at a different phase of a response period. The outputs of the flip-flops determine the phase at which the response ready signal was generated by the component.

Abstract: Disclosed is a Software Sanity Monitor for automatically detecting and remedying software lock-up conditions without user intervention. Users often refer to these conditions as “hangs” or “forever loops”. Although the Software Sanity Monitor uses the operating software's information, it is designed to execute independent of the operating system software; thereby, eliminating reliance on a “sane” operating system. If a “hang” condition is detected, the Software Sanity Monitor will automatically restart the system after logging the failure and, optionally, notify the user or host system.

Abstract: A system is provided for asymmetrically maintaining system operability that includes a first processing element and a second processing element coupled to the first processing element by a communication link. The first processing element is operable to perform at least one function. The second processing element is operable to perform at least one function of the first processing element in the event the first processing element fails, and further operable to expect and receive keepalive inquiries at an expected rate from the first processing element and to send responses in response to the inquiries to the first processing element. The second processing element is further operable to take remedial action after not receiving any inquiries within a first predetermined time period.

Abstract: A high availability platform runs a fault-tolerant controller process (FTC) and at least one monitored process that indicates its live state by periodically sending a heart-beat message to the FTC. The FTC responds to the heart-beat message by modifying the frequency at which it expects the heart-beat message according to information contained therein. The platform may run an additional process, the monitored process being adapted to regularly send the additional process a message and to notify the FTC that the additional process is dead when it receives an error code from an operating system after sending a message to the additional process.

Abstract: A control device for a disk array of the present invention includes a first element which accesses a plurality of disks of the disk array and a timer which counts to a first timeout value when all of the disks are normal and a second timeout value when one of the disks is defective, unless the first element receives response from the disks. The control device for a disk array also has a second element which determines that an access fails if the timer reaches one of the first or second timeout values. A control method for a disk array of the present invention includes accessing a plurality of disks of the disk array, counting to a first timeout value when all of the disks are normal and a second timeout value when one of the disks is defective, unless there is a response during the accessing step, and determining that an access fails if one of the first or second timeout value is reached during the counting step.

Abstract: A system and method for detecting and handling errors in a computer system are disclosed. The invention is configurable to permit selecting of timelength or time out values, assigned interrupts to be generated and error recover procedures so that failures of system events can be promptly detected and recovered from. The watchdog timer is started with a timelength or time out value and generates an interrupt (i.e., is triggered) if the period of time set as the timelength passes without receiving a reset. The watchdog timer interface interacts and controls the hardware based timer to obtain this watchdog timer functionality. The hardware based timer is generally a high precision timer that exists in hardware architecture for a computer system and is usable by system software. The watchdog timer interface controls and sets various parameters and/or registers of the hardware based timer in order to provide the desired functionality of a watchdog timer.

Abstract: The present invention discloses a method of automatically detecting and storing the CPU clock frequency in a telecommunications hub. The hub includes a known reference clock for a digital signal processor. A first counter counts the reference clock cycles during the same time period in which a second counter counts the processor clock cycles. The number of processor clock cycles counted is divided by the number of reference clock cycles counted and the result is multiplied by the frequency of the reference clock. The calculated processor clock frequency is compared to a table of available CPU clock speeds and the closest available clock speed is selected. The selected available clock speed is then stored as a variable in RAM for use by all software which uses the processor clock as a base for generating absolute timing signals, such as a one second clock.

Abstract: A system and method for observing the two clocking phase signals, finding a point in time when said signals have a phase coincidence which is good enough for fulfilling a phase difference requirement (e.g. 20 ps), and switching from one clock source to the other. The essential idea is not to compare the phases directly but to generate an auxiliary signal out of the two clock signals which is easier to handle in order to find that desired point in time and which reflects all desired properties of the time dependent phase shift between said clock signals. At a predetermined location in the cycle of both clock signals (e.g. its positive transition) a pulse is generated out of each of the clock signals with matched identical delay elements located very close to each other on the same chip for both signals. As they match they produce exactly the same pulse widths. The absolute length of the pulse width is of minor relevance as long as the length of the pulses is the same within close limits.

Abstract: A telecommunications device includes a synchronization bus and a controller coupled to the bus. The controller selects a primary reference clock signal from among a plurality of reference clock signals, generates a first system clock signal according to the primary reference clock signal, and communicates the system clock signal using the bus. The controller detects a loss of signal associated with the primary reference clock signal and, in response, enters holdover mode. The controller continues generating the first system clock signal while in holdover mode and determines the acceptability of a secondary reference clock signal also selected from among the plurality of reference clock signals. The controller performs a switchover from the primary reference clock signal to the secondary reference clock signal if the secondary reference clock signal is acceptable and, in response to the switchover, generates the first system clock signal according to the secondary reference clock signal.

Abstract: In the present invention, a coordinated hierarchy of timing mechanisms preferably cooperate to report errors at different operational levels of a complex of computing devices. Preferably, each timer is able to identify a failure condition at its own level of operation and transmit a time-out condition to a higher level device which may also be a timer. Upon generation of a time-out condition, a system component experiencing a fault condition preferably continues to operate in a degraded mode, informs devices attempting to communicate with the faulty component of a status of the fault condition, and preferably proceeds to identify and correct a failure which caused the time out condition. The timers may be implemented in hardware or software.

Abstract: A method of determining the integrity of a linked list stored in a memory block, comprises the steps of, providing a series of independent bit positions, defining each of the independent bit positions to correspond to one of the cells, setting each of the independent bit positions to a predetermined setting, resetting each of the independent bit positions upon access of its defined corresponding cell, and then, after a predetermined interval testing the independent bit positions. If then any of the independent bit positions have not been reset by the time the test is made, an error condition is set.

Abstract: A method for controlling an electronic control using a circuit that includes a damper capacitor. The method includes substantially discharging the damper capacitor and enabling operation of the electronic control when the damper capacitor is substantially discharged.

Abstract: An operating system hang condition is detected by exploiting the fact that when an operating system hang condition occurs, the operating system kernel generally fails to respond to operating system interrupts. Consequently, an operating system hang condition may be detected by setting a status flag to a first value, generating an operating system interrupt intended for an operating system interrupt handler within an operating system kernel that resets the status flag to a second value, executing the operating system interrupt handler if the operating system kernel is responding to the operating system interrupt and executing a system BIOS interrupt handler that measures a time interval in which the status flag is set to the first value without being reset to the second value.

Abstract: A watchdog method and apparatus for a processing system running one or more tasks for controlling one or more subsystems is described. In one embodiment, the watchdog method configures a reset controller to cause a hardware reset to the one or more subsystems in a predetermined time, and registers one or more tasks in a task table. The method calls a first task in the table and changes a status of the first task to called. For each task in the table, the method determines the status of the task, and, if the status is called, sets a flag to a true state if a second predetermined time has passed since the task was called and a response message has not been received from the called task. The method configures the device to push back the occurrence of the hardware reset to the predetermined time if the flag is not set to the true state. A next task in the table is then called, and its status changed to called. The method again determines the status of each task in the table, and so on.

Abstract: A circuit analyzing device comprises a wiring model information extracting section for generating wiring model information for each wiring of a circuit, a circuit simulation section for analyzing waveform propagation characteristics of each wiring model information that has been extracted by the wiring model information extracting section, a spectrum characteristic information calculating section, a linear simulation section, and an S parameter information calculating section.

Abstract: An apparatus that make it possible for a microcomputer to execute self-programming without the occurrence of shutdown or initialization (restart) includes a flash EEPROM for storing programs and data, a monitoring circuit for monitoring program runaway and malfunction, and the microcomputer. When rewriting of the content of said flash EEPROM (i.e., self-programming) is executed via control by the microcomputer, the monitoring circuit controls output/suppression of an abnormality detection signal on the basis of an externally entered flash EEPROM write-enable signal and a monitoring-circuit operation-control signal output from the microcomputer.

Abstract: A method and system for integrated support for solving problems with personal computer systems comprises monitoring operating system functionality to determine if a computer system failure exists, to identify the computer system failure and to provide a solution of the computer system failure. A robust user interface, including a simple-to-use user button interface, supports single touch user input to indicate a computer system problem or question. Watchdog timers compare the time of hardware and operating system functionality, such as boot sequence operation, against predetermined time periods to determine whether or not a computer failure exists. A computer system failure is determined if a watchdog timer expires upon completion of a predetermined time period without being cleared. A hardware problem is identified on initial boot if the watchdog timer is not cleared by an operating system service routine.

Abstract: In an ECU for vehicles, a clock IC operates with sub power and measures time continuously irrespective of whether a microcomputer is operating. The microcomputer determines whether the clock IC has been reset on the basis of a history indicating that the sub power has fallen below a data holding voltage of an SRAM which also operates on the sub power. Alternatively, the microcomputer determines whether the clock IC has been reset by checking data held in the SRAM. The microcomputer determines failure of a water temperature sensor from a soak time calculated from time data from the clock IC and a detection value of the water temperature sensor on restarting of the engine. When the clock IC has been reset, the microcomputer prohibits this failure determination of the water temperature sensor.

Abstract: A microprocessor runaway monitoring control circuit with which self-diagnosis of a watchdog timer WDT can be carried out safely and cheaply even during operation of the microprocessor (CPU). A microprocessor 101 supplies first and second watchdog clearing signals WD1 and WD2 to first and second watchdog timers WDT1 and WDT2, and when the both of the watchdog clearing signals WD1 and WD2 stop, the microprocessor 101 is reset by way of a logical connector circuit 122. The microprocessor 101 has failure diagnosing means 103 which intentionally stops the first watchdog clearing signal WD1 and diagnoses the response of the first watchdog timer WDT1 on the basis of a monitor signal MN1 and stops the second watchdog clearing signal WD2 and diagnoses the response of the second watchdog timer WDT2 on the basis of a monitor signal MN2, whereby diagnosis of the watchdog timers WDT1, WDT2 is carried out without the microprocessor 101 being stopped.

Abstract: An integrated circuit includes secure logic that requires protection. Secure assurance logic protects the secure logic. The secure assurance logic includes a plurality of protection modules that monitor the occurrence of insecure conditions. Each protection module monitors a different type of insecure condition. Each protection module asserts an alarm signal when an associated insecure condition is detected. The alarm signals asserted by the plurality of protection modules are stored.

Abstract: A processor and an associated method and data processing system are disclosed. The processor includes an issue unit (ISU), a completion unit, and a hang detect unit. The ISU is configured to issue instructions to an execution unit. The completion unit is adapted to produce a completion valid signal responsive to the issue unit completing an instruction. The hang detect unit is configured to receive the completion valid signal from the ISU and adapted to determine the interval since the most recent assertion of the completion valid signal. The hang detect unit is adapted to initiate a hang recovery sequence upon determining that the interval since the most recent assertion of the completion valid signal exceeds a predetermined maximum interval. In one embodiment, the hang recovery sequence includes the hang recovery unit asserting a stop completion signal to a completion unit and a stop dispatch signal to a dispatch unit to suspend instruction completion and dispatch.

Abstract: A computer storage system includes director boards which control transfer of data to and between a host computer, a system cache memory and a disk array. The directors are provided with features which enhance system performance and reliability. A hardware emulation controller permits a high performance processor to be used with existing system circuitry. A control store memory is organized with primary and secondary data areas and primary and secondary parity areas. Data is written to both the primary and secondary areas. A read request accesses data in the primary area and performs a retry in the secondary area in the event of a parity error. A power supply system includes on-board marginable power supplies to facilitate testing and power-up by-pass circuits for protection of sensitive circuitry. A system clock configuration employs primary and secondary clocks to ensure redundancy of synchronized timekeeping.

Abstract: A single processor system features independent multiple watchdog units allocated to a processor unit of the system, the watchdog units operable to monitor for system faults and, upon detecting a fault, further operative to place the processor system into a predetermined fault reaction state. The multiple watchdog units are each provided with respective different watchdog calls which are output to the processor unit depending upon program execution.

Abstract: A watchdog monitor coupled to a device bus includes in at least one executable software the ability to produce, during each frame interval, a strobe addressing a predetermined number to the monitor. The monitor responds to the interrupt and to lack of arrival of the correct predetermined number by generating a fault flag. The monitor also runs an internal counter which is reset at each interrupt signal; the count of the internal counter exceeds a threshold count if an interrupt fails to arrive. Such a timed failure results in setting of a frame fault flag. The monitor further runs an internal clock independent of the system clock. A further missing pulse detector initiates a counter at each monitor clock pulse, and raises a flag if the monitor clock counter counts a duration exceeding the monitor inter-clock-pulse interval.

Abstract: A session manager has a session timeout mechanism to selectively timeout client-server sessions. The session timeout mechanism has multiple timeout buckets to hold corresponding groups of sessions according to the sessions' timeout periods. Sessions located in different ones of the timeout buckets are set to timeout at different times. The session manager also has a session timeout clock that is incremented every predetermined time unit (e.g., every minute). The session timeout clock maintains a pointer to one of the timeout buckets and advances that pointer with each clock increment. The session timeout clock advances the pointer through all of the timeout buckets, one bucket at a time. The session timeout clock advances the pointer repeatedly through all the buckets. The cycle time for the session timeout clock to reference every timeout bucket is equal to the incremental time unit multiplied by the number of buckets.

Abstract: Disclosed herein is a system for controlling the process of performing a command in an HDD. The HDD comprises a register for holding the command control information supplied from a host system, a command register for holding a specific command. The HDD further comprises a CPU. The CPU fetches the command control information from the register when the specific command held in the command register is one for setting the command control information. The CPU controls the process of performing a command in accordance with the command control information, thereby to finish performing the command within a period between the time when the host system issued the command and the time when the host system issues the next command.

Abstract: A computer system employs a first computer; a first bus switch coupled to the first computer; a data bus coupled to the first computer via the first bus switch; a second computer; a second bus switch coupled to the second computer, the data bus being coupled to the second computer through the second bus switch; and a monitor system coupled to the first computer, to the first bus switch, and to the second bus switch.

Abstract: A service processor surveillance mechanism is provided for multiple partitions. Each partition stores its own official response. The surveillance routine checks to see if it has enough time for the service processor to respond to its previous probe. If sufficient time has not passed, the surveillance code returns to the calling function with the partition's official response. If sufficient time has passed, the surveillance code reads the surveillance byte in nonvolatile random access memory. The surveillance code then determines the current state of the service processor and determines whether the official response needs to be updated. If the surveillance code updates the official response, the partition's official response is set to the updated official response and returns the partition's official response. If the official response has not changed since the last time the partition probed the surveillance byte, then the surveillance code returns a neutral value.