Abstract: The present invention facilitates access to timers in a computing device. In particular, a timer system facilitates configuring a hardware interrupt timer in a computing device, the timer being guaranteed to expire at a specific time in a non-real-time environment. A calling application passes parameters to a hardware independent application programming interface (API) to the hardware interrupt timer. The hardware independent API validates the parameters and relays them to a hardware dependent API. The hardware dependent API establishes a connection with the timer in accordance with the validated parameters, and executes a service routine associated with the application upon expiration of the timer.

Abstract: A method, system, and apparatus are provided for identifying unresponsive portions of a computer program. According to the method, program code that can potentially result in unresponsive behavior is wrapped in timers. A timer is started on a background thread at the beginning of the execution of a section of program code. The timer is set to expire after a specified threshold period of time has expired. A determination is made as to whether the timer expires during the execution of the section of program code. If the timer expires during the execution of the section of program code, execution is interrupted and the section of program code is identified as unresponsive and system state information is stored for use in diagnosing the computer program and remedying the unresponsive behavior. The actual system state information stored may be defined by a remote control file and may be stored at or around the time the timer expires.

Abstract: Disclosed are systems and methods for controlling transaction draining for error recovery comprising asserting a control signal to prevent system resources associated with a particular error from issuing new requests, dropping transactions tracked by an out-of-order queue, and issuing transactions not tracked by the out-of-order queue.

Abstract: Described is a synchronization technique that may be used to coordinate processing between endpoints using the connecting message fabric. Processors in a data storage system communicate using the message switch of the message fabric. Each processor is an endpoint within a data storage system. A first endpoint may mark the beginning of the synchronization period by specifying a processing point at which other processors and the first endpoint are to coordinate from the perspective of the first endpoint. Synchronization is performed using local state information about the processing state of each endpoint as reported by each endpoint. The first endpoint waits for successful synchronization within a timeout period in accordance with the first endpoint's local state information. If successful synchronization does not occur prior to the timeout period, the first endpoint broadcasts a message with a new synchronization point to other endpoints.

Abstract: Delivery of energy by a defibrillator or other medical device is inhibited when the processor or software that controls a module of the medical device operates abnormally. A windowed watchdog timer (WWDT) incorporated into one module of the medical device is used to control the operation of other modules of the medical device via a software-based extension technique. As a result, the risk of harm to the patient is reduced compared to medical devices that incorporate over-limit type watchdog timers. In addition, costs associated with implementing WWDTs in multiple modules of the defibrillator are avoided, thereby lowering the overall cost of implementation.

Abstract: According to one embodiment, a telecommunications device includes a bus and a controller coupled to the bus that generates a system clock signal according to a first reference clock signal and communicates the system clock signal using the bus. The controller detects a loss of the first reference clock signal and, in response, continues generating the system clock signal, switches from the first reference clock signal to a second reference clock signal if the second reference clock signal is acceptable, and generates the system clock signal according to the second reference clock signal.

Abstract: In a power controller or other computing resource shared by multiple processors, an ID is written to the lock register, thereby designating a master processor. A timer is then initialized to count for a predetermined period. Periodically, the master processor transmits a “heartbeat” signal to the shared resource, indicating that its operation remains normal. Upon receipt of the heartbeat signal, the timer is reset and begins a new count for the predetermined period. If the timer reaches the end of the period without having received a heartbeat signal, indicating that the master processor has failed or hung, the lock register is cleared again and an interrupt signal is broadcast to all of the processors. The processors compete for master status anew and, when an ID is successfully written to the lock register, the timer is restarted and the new master periodically transmits its heartbeat signal.

Abstract: An apparatus and method to determine if a device error rate equals or exceeds a threshold. In an apparatus embodiment, a system comprises a device, and an interrupt handler executable by a processor. The interrupt handler executes, upon expiration of a time period, to determine if a threshold error rate associated with the device has been equaled or exceeded.

Abstract: A system for controlling power sources of motherboards under test through networks includes a central server (1), a serial device server (3), a bus distributor (4), a number of power controllers (5), and a number of testing computers (8). The central server sets testing parameters, and transmits instructions regarding turning on or off power sources of the testing computers to the serial device server, in order to control the power sources of the testing computers. The serial device server converts the instructions into serial instructions, and generates corresponding serial signals. The bus distributor distributes an address for each power controller, receives the serial signals, and transmits the serial signals to corresponding power controllers. Each power controller turns on power sources of corresponding testing computers in which motherboards under test are installed according to the received serial signal. A related method is also disclosed.

Abstract: An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value.

Abstract: Many computing system environments require continuous availability and high operational readiness. The ability to find, diagnose, and correct actual faults and potential faults in these systems is a high priority. By combining a continually updated database of computing system performance with the ability to analyze that information to detect faults and then communicating that fault information to correct the fault or provide appropriate notification of the fault results in achieving the goals of high availability and operational readiness. FIG. (1) shows how the data collectors, fault detectors and policy actions are combined to meet those goals.

Abstract: In a circuit for detection of internal microprocessor watchdog device execution comprising a microprocessor (6) with the internal watchdog device and with an input/output line (11) transmitting information about microprocessor reset, and a device for resetting the microprocessor system, to the input/output line (11) transmitting information about microprocessor (6) reset, a clock input CK is connected, which triggers the flip-flop (12), whose data input D and an inverted reset input /R are connected to the output of the device (19) for resetting the microprocessor system, and the inverted flip-flop (12) output /Q is connected to the input of the device (19^) for resetting the microprocessor system.

Abstract: A motor controller is provided with: an estimated temperature calculating means that calculates an estimated temperature of a motor; and a control unit that can perform a driving control of the motor only when the estimated temperature is not larger than a predetermined value. A mode switching means switches the control unit and the estimated temperature calculating means between in a normal operation mode in which they can drive the motor and in a sleep mode in which electric power consumption thereof is smaller than in the normal operation mode in accordance with a predetermined condition while the motor is stationary. An activating means activates the estimated temperature calculating means in the sleep mode for a predetermined active time every time a predetermined sleep time is elapsed.

Abstract: A controller is operable in one of a plurality of operational modes, which include an estimated temperature computation performing mode for performing computing of an estimated temperature of the motor and an estimated temperature computation non-performing mode for stopping the computing of the estimated temperature of the motor. An operational mode of the controller is changed from the estimated temperature computation performing mode to the estimated temperature computation non-performing mode according to a predetermined condition in a stopped state of the motor.

Abstract: An electronic control unit includes a microcomputer and an input interface circuit. The microcomputer has square wave input ports, a reference square wave input port, a serial communication port, and an output port. Square wave signals are inputted from sensors to four channels of the input interface circuit. A channel selector included in the input interface circuit the selects square wave signals in orderly sequence for capturing. The microcomputer performs a comparison between a time at which the square wave is captured and a time at which the selected square wave signal is captured for diagnosing operation of an input capturing function.

Abstract: An integrated circuit includes a plurality of processing stages each including processing logic 1014, a non-delayed signal-capture element 1016, a delayed signal-capture element 1018 and a comparator 1024. The non-delayed signal-capture element 1016 captures an output from the processing logic 1014 at a non-delayed capture time. At a later delayed capture time, the delayed signal-capture element 1018 also captures a value from the processing logic 1014. An error detection circuit 1026 and error correction circuit 1028 detect and correct random errors in the delayed value and supplies an error-checked delayed value to the comparator 1024. The comparator 1024 compares the error-checked delayed value and the non-delayed value and if they are not equal this indicates that the non-delayed value was captured too soon and should be replaced by the error-checked delayed value.

Abstract: An integrated circuit supporting a first interface and a second interface and an integrated circuit card having the same includes the first interface capable of communicating with a first host, the second interface communicating with a second host, and a control block. The control block activates the second interface when a voltage level of a contact that the second host can be connected is in a first state at a first-occurring timepoint between a reference timepoint and a state transition timepoint of an external reset signal output from the first host, and deactivates the second interface when the voltage level of the contact is in a second state. The integrated circuit card has the integrated circuit built in.

Abstract: A program product is embedded in a media accessible by a computer operative to request a plurality of program tasks for wakeup so as to execute the plurality of program tasks in a predetermined schedule. The program product causes at least one of the computer and another computer to execute the instructions of measuring a delay period between a request of at least one of a plurality of program tasks and a wakeup thereof. The instructions include comparing the measured delay period with a predetermined first timeout value, thus determining whether at least one of the plurality of tasks is abnormally executed by the computer based on the comparison result.

Abstract: A virtual routing system includes a number of physical routers. One of the physical routers is the master with respect to a given source of traffic, and the others are backups. If the master router fails, then one of the backup routers becomes the master to provide substantially uninterrupted service through the virtual routing system. A virtual redundant routing protocol (VRRP) can be extended to support sub-second advertising of VRRP packets by a master router a backup router. In some cases, sub-second switching is supported, in which a backup router can become a new master router after less than a second of down time by the original master router. Such responsiveness in a virtual routing system is very useful for many applications, such as voice-over-packet applications in which down time of the routing system for more than one second is unacceptable.

Abstract: Systems and methods are provided for securing a multicore computer chip with a watchdog processor. In a system with a watchdog process and any number of other processors and components, the watchdog processor monitors bus communications between the second processor and at least one third component. The watchdog processor may be further independently coupled to at least one of the other components so that it can monitor internal operations of such component, thereby acquiring detailed information about the specific operations of at least one component in the system. The watchdog processor can enforce an interaction policy on bus communications between components, as well as enforce an independent security policy on the monitored components.

Abstract: A system is disclosed for generating a plurality of timeout event triggers in response to a plurality of kinds of timeout events. The system includes an overflow generator, which generates a plurality of overflow signals having a plurality of periods. The system also includes a plurality of trigger generators corresponding to the plurality of kinds of timeout events. Each of the plurality of trigger generators is associated with a corresponding timeout threshold value representing the minimum amount of time that must elapse for the trigger generator to generate a timeout event trigger. For each of the plurality of timeout triggers, a corresponding selection signal selects one of the plurality of periodic overflow signals. The timeout threshold corresponding to each timeout trigger is equal to the period of the corresponding selected overflow signal multiplied by the value of the corresponding control signal.

Abstract: A method and system for performing a bit error rate test on a device with substantial duty cycle output distortion are described herein.

Abstract: An apparatus, system, and method are provided for automatically freeing locked server resources using a timeout value closely related to actual real-time message delays plus a delta value that can be adjusted at a plurality of levels. The levels include default, server, connection, and transaction. The apparatus includes a timer, a communication module, a computation module, and a lock handler. The timer determines a timeout value for communications from a client to a server. The communication module sends an output message to the client and locks a server resource in anticipation of an acknowledgement (ACK) message from the client. The computation module, which calculates an ACK timer, includes a difference between a send time and a current time. If no ACK message has been received from the client and the ACK timer exceeds the timeout value, the lock handler may free the locked server resource.

Abstract: A control apparatus for controlling a digital video apparatus using Universal Serial Bus, comprises a storage unit which stores a control program and a control unit which executes the control program. The control program controls (a) step of judging whether a response to a first request for requesting to change a status of the digital video apparatus to a predetermined status is an ACK or not, (b) a step of judging, if the response is the ACK, whether notification information is received or not before a lapse of a predetermined time, the notification information notifying the control apparatus that the status of the digital video apparatus is changed, and (c) a step of transmitting, if the notification information cannot be received before the lapse of the predetermined time, a second request for requesting information representative of the status of the digital video apparatus to the digital video apparatus.

Abstract: A memory dump program boot method includes the steps of defining, in non-volatile variables that are managed by a boot firmware of a computer system, boot information of a plurality of stand-alone dump programs that are installed in the computer system, and a table variable indicating a corresponding relationship of the plurality of stand-alone dump programs and a plurality of operating systems, specifying the boot information of a corresponding one of the plurality of stand-alone dump programs from the table variables when the boot firmware boots an arbitrary one of the plurality of operating systems, and writing information indicating the specified boot information in the non-volatile variables that are referred to when executing a stand-alone dump, and booting the corresponding one of the plurality of stand-alone dump programs when a booting of the stand-alone dump is instructed, by checking existence of variables that are referred to when executing the stand-alone dump and referring to information of the

Abstract: A selector selects an FF pair (FFs, FFe) in circuit information, a calculator calculates value-capturing condition data at FFe, a divider divides a path set that matches the value-capturing condition data from a set of paths between the FF pair (FFs, FFe), and a multi-cycle path detector determines whether all the paths in the path set are multi-cycle paths. When the path set is a multi-cycle path, it is added to a timing exception path list that is output by an output unit.

Abstract: A method capable of detecting a status of a basic input/output system (BIOS) for setting a clock is applied to a clock generating device of a computer motherboard and sets the clock according to a signal status of the BIOS or a trigger signal. A device capable of detecting the BIOS status for setting the clock is also proposed. The device has a crystal oscillator, a frequency control unit, a phase-lock-loop (PLL) spread-spectrum unit electrically connected with the crystal oscillator and the frequency control unit, a memory unit having a clock setting value stored therein, a detection control unit electrically connected with the memory unit and used to detect a signal status, and a logic control unit electrically connected with the PLL spread-spectrum unit, the frequency control unit and the detection control unit.

Abstract: A method for monitoring a microprocessor and a circuit arrangement having a microprocessor are described. A microprocessor is monitored using an assigned watchdog. The watchdog monitors whether reset pulses are received within a time interval of predetermined duration. If the reset pulse is received, the time interval is reset and restarted. If reset pulses are not received, a reset of the microprocessor is initiated. In suitable operating phases of the microprocessor, a check function of the watchdog is activated. During the execution of the check function, first a reset of the watchdog is executed and then a sequence of waiting loops, whose duration is greater than the duration of the time interval of the watchdog, is executed.

Abstract: To offer a control system that is not only equipped with a high fail-safe function but also capable of avoiding erroneous failure detection. The CPU 110 outputs a drive signal DC for driving the load L according to the input signals from sensors S1 and S2 by means of the load drive element 120. The monitor IC 150 detects abnormal condition of equipment and outputs the first reset signal RES 1 for resetting the CPU 110 and also outputs the second reset signal RES2 when the first reset signal RES1 has been outputted for a specified number of times. The compulsory turn-off circuit 160 stops the output to the load L according to the second reset signal RES2 outputted from the monitor IC 150.

Abstract: A method and system for identifying runaway software agents operating in a computer system is disclosed. An operating window is defined for an agent. The operating window specifies the maximum desired operating time for the agent. When an agent begins operation, its start time is recorded. At a later time, a measurement is made comparing the start time and current measurement time to the operating window. If the comparison indicates that the agent has exceeded the operating window, the agent is identified as a runaway agent. The computer system processes data associated with the runaway agent and displays it to a user interface such as a monitor.

Abstract: A system is provided with a basic input/output system (BIOS) with the ability to intervene, when a suspend process is initiated in response to an AC failure condition to place the system in a suspended to memory state, to initiate a number of data transfer operations to save a persistent copy of an operational state of the system. The BIOS is further equipped to check one or more times whether the data transfer operations are completed, and causing a processor of the system to operate in a reduced power consumption mode at least one time period while the BIOS is not performing the checking.

Abstract: An on-vehicle electronic control device includes an auxiliary microprocessor and subjects a microprocessor allocated to a main part of control to an external diagnosis, thereby improving reliability of performance. A microprocessor including a nonvolatile program memory into which a control program is written is serially connected to an auxiliary microprocessor including an auxiliary nonvolatile program memory. The microprocessor and the auxiliary microprocessor function in cooperation to control on-vehicle electric load groups in response to input signals from on-vehicle sensor groups and on-vehicle analog sensor group. The nonvolatile program memory and the microprocessor are subjected to runaway monitoring performed by a watchdog timer and to an external checksum diagnosis performed periodically by the auxiliary microprocessor. If an anomaly occurs in the runaway monitoring, the external checksum diagnosis, and a checksum interval, parts of electric loads are cut off of power supply by load power relay.

Abstract: In a computer system in which computers each having a plurality of processors are connected with each other, said each computer comprises a system controller for, at the time of a failure within the computer system body, disconnecting own computer from other computer in which said failure has occurred, without informing own processor of such failure.

Abstract: An apparatus and method for reducing false triggering of a signal due to an electrostatic discharge event are disclosed. The method includes detecting a high voltage on a signal received at an input of a delay circuit and delaying the signal between the input of the delay circuit and an output of the delay circuit for a predetermined amount of time. If a low voltage is detected on the signal after the predetermined amount of time, the high voltage is prevented from propagating to the output of the delay circuit.

Abstract: A new method for the detection and correction of environmentally induced functional interrupts (or “hangs”) induced in computers or microprocessors caused by external sources of single event upsets (SEU) which propagate into the internal control functions, or circuits, of the microprocessor. This method is named Hardened Core (or H-Core) and is based upon the addition of an environmentally hardened circuit added into the computer system and connected to the microprocessor to provide monitoring and interrupt or reset to the microprocessor when a functional interrupt occurs. The Hardened Core method can be combined with another method for the detection and correction of single bit errors or faults induced in a computer or microprocessor caused by external sources SEUs.

Abstract: The method according to this invention concerns a method to secure the execution of a program stored in an electronic assembly comprising information processing means and information storage means. The method consists in checking the execution time of at least one sequence in said program with respect to the normal predetermined execution time of said sequence. This invention also concerns the electronic module in which said method is implemented and the card comprising said module.

Abstract: One embodiment disclosed relates to a method of communicating status from a node of a cluster of computer systems. A first status signal is received from a computational node, and a default status signal is generated. The first status signal and the default status signal are used to generate a second status signal. Another embodiment disclosed relates to a method of communicating node status within a cluster of computer systems. A first signal indicative of the status of a current node is generated. A second signal indicative of the status of a preceding node is received. The first signal is transmitted to a next node if the current node is present in the cluster, and the second signal is transmitted to the next node if the current node has been removed from the cluster.

Abstract: A device for monitoring a processor is described. A watchdog simultaneously monitors the system clock, the software base functions and performs a check of the tests of the system components of the processor. If an error is detected, the watchdog communicates this to the processor, an error counter is incremented and at least one device that is connected to the processor is blocked. If the error counter attains a predetermined value, the block is continued until the device of the present invention is deactivated. If an additional error is detected during a blocking time, the blocking time is extended.

Abstract: Disclosed are systems and methods for determining time-outs with respect to a plurality of transactions comprising utilizing a first time-out clock for simultaneously determining time-out states with respect to a first set of transactions of the plurality of transactions, and determining when transactions of the first set of transactions have reached a timed-out state of the time-out states.

Abstract: Methods and systems for preserving dynamic random access memory content in response to a hung processor condition are disclosed. In order to preserve dynamic random access memory content, a first watchdog timer is initiated and strobed at a predetermined time interval less than its timeout value. If a hung processor condition occurs and the strobing of the first watchdog timer fails, the first watchdog timer generates a non-maskable interrupt to the processor. The non-maskable interrupt triggers the processor to execute an interrupt service routine. If the processor is able to execute the interrupt service routine, the interrupt service routine controls the processor to perform a selective system reset and preserve dynamic random access memory contents. If the processor is not capable of executing the interrupt service routine, a board reset occurs and dynamic random access memory contents are cleared.

Abstract: An improved method and system for determining the state of an operating system includes an operating system, a USB host controller that is driven by the operating system to send a polling signal to a USB device, and a management module that monitors the polling signal. If the polling signal has stopped, then the management module takes corrective action to restore the operating system. No specialized software or specialized hardware is required to determine the state of the operating system. The state of the operating system can be determined quickly and efficiently without adding to the costs of the system.

Abstract: The present invention relates to test systems for testing integrated circuit devices and to calibration associated systems and methods. One embodiment of the invention provides a method for providing formatted levels for use in a test system. The method includes: providing on a single CMOS IC, a timing generation circuit operative to provide timing information signals; and a formatter in communication with the timing generation circuit.

Abstract: A method for checking the reset function of an embedded processor is described. First, a check is made to see if a reset “flag” is not set (202) before branching to execute the test routine that initiates the embedded processor's reset (206). The test program sets the flag (204) before initiating the reset. When the processor resets and executes the test program from the beginning again, it determines that the flag was set (202), and it does not execute the reset instructions again.

Abstract: An integrated circuit, a client computer system, and a method for operating the integrated circuit in the client computer system. The integrated circuit includes a first bus interface logic for coupling to a first external bus, a microcontroller configured as an Alert Standard Format management engine, and a watchdog timer coupled to the microcontroller. The microcontroller is further configured to receive Alert Standard Format sensor data over the first external bus. The watchdog timer is coupled to receive a reset input upon a predetermined change in a system state. The watchdog timer is further configured to provide an indication to the microcontroller in response to an expiration of the watchdog timer.

Abstract: The invention relates to a method for monitoring a microcontroller having at least one normal operating state and one state with a reduced power consumption and to a circuit configuration for carrying out the method. The method enables the functionality of the microcontroller to be monitored even in the state with the reduced power consumption. The method includes steps of: during the normal operating state, receiving a status signal having pulses from the microcontroller and resetting the microcontroller if the pulses are not received within a predefined time pattern; and during the state with the reduced power consumption, transmitting a wakeup signal having a sequence of pulses to the microcontroller, and resetting the microcontroller if there is no confirmation by the microcontroller within a predefined time interval after a pulse of the wakeup signal.

Abstract: A method for monitoring a system controlled by a processor utilizes an integrated monitoring unit independent of the processor but integrated together with the processor in an integrated circuit, as well as a watchdog unit for preventing measures that influence the system. The watchdog unit is cyclically reset by the integrated monitoring unit.

Abstract: The invention relates to a method for preventing total failure in a processing unit for sending and receiving protocol information for a large number of transmission channels, wherein a protocol process is started by a controller for every protocol and a separate monitoring process that monitors the orderly time duration of the protocol process can be activated or deactivated parallel thereto for every protocol process. If the previously determined time duration of the protocol process is exceeded, the monitoring process reports it to the controller, whereupon the controller stores relevant data for subsequent localization of errors.

Abstract: A multi-processor computer system permits various types of partitions to be implemented to contain and isolate hardware failures. The various types of partitions include hard, semi-hard, firm, and soft partitions. Each partition can include one or more processors. Upon detecting a failure associated with a processor, the connection to adjacent processors in the system can be severed, thereby precluding corrupted data from contaminating the rest of the system. If an inter-processor connection is severed, message traffic in the system can become congested as messages become backed up in other processors. Accordingly, each processor includes various timers to monitor for traffic congestion that may be due to a severed connection. Rather than letting the processor continue to wait to be able to transmit its messages, the timers will expire at preprogrammed time periods and the processor will take appropriate action, such as simply dropping queued messages, to keep the system from locking up.

Abstract: Before a predetermined processing sequence, the integrated circuit detects the state of at least one timer. The circuit controls the activation of the timer if it is not activated, and disables itself if the timer is activated.

Abstract: A method for monitoring a plurality of servers in a cluster and taking corrective action for the servers. A request to one of the servers is sent. Then, a determination is made if the one server successfully handles the request and how long it took for the one server to handle the request. If a response is received indicating that the one server successfully handled the request, but it took the one server longer than a predetermined time period to handle the request, a dispatcher for the one server is notified to reduce, but not eliminate, a workload of the one server. There is specified a number of consecutive requests that can be sent to a server and not handled by the server within a specified time period for each of the requests; the number indicates that the server is down. A request is sent to one of the servers, and a determination is made that the one server did not successfully handle the request within the specified time period.