Abstract: A microcontroller including a CPU (Central Processor Unit) is capable of detecting the error of its structural part. The CPU executes a first initialization phase in response to a power-on reset signal output from a power-on reset circuit, then executes a second initialization phase in response to a start signal, and then executes usual processing. The CPU outputs a single timer run signal during first initialization phase and repeatedly outputs the timer run signals during usual processing. A watchdog timer starts timing in response to the timer run signal and then outputs an overflow signal on the elapse of a preselected period of time. After receiving the power-on reset signal from the power-on reset circuit, an error detector feeds the CPU with the start signal in response to an overflow signal output from the watchdog timer for the first time.

Abstract: A fault of an operating system (OS) is observed, and in addition to application program (AP) fault monitoring, check-point information is preserved without adding dedicated hardware. In a computer having a multi-OS environment, an AP fault monitor and a monitored AP operate on a first OS. A fault monitor operates on a second OS. Each of the first OS and the AP fault monitor transmits an alive message to the fault monitor by utilizing an inter-OS communication function of a multi-OS controller. The fault monitor monitors the alive message of each of the first OS and the AP fault monitor. The monitored AP also transmits an alive message to the AP fault monitor for monitoring. The monitored AP preserves check-point information in a region of a memory. In the region of the memory, information is preserved by a fault and restart of the first OS as well.

Abstract: A disk memory device is provided that measures a time for reading or writing a prescribed amount of data with an access time measurement part, compares access time data with a previously set limit time with an access time defect determining part, and, when the access time data exceeds the limit time, determines that a corresponding area on a disk memory (4) is defective, and enters the area into a defect list so that the corresponding area is not used. Thereby, when the disk memory device is used for recording/reproducing AV data, data access is performed within a prescribed time, so that videos are reproduced without interruption or data is recorded without lack of frame.

Abstract: A system is described in which a plurality of host computers are coupled to a storage system for storing and retrieving data in the storage system. The storage system includes individually addressable units of storage such as volumes or logical unit numbers. A security management system controls access to each of the individually addressable units of storage based upon the identification of the host permitted to access that unit of storage.

Abstract: A signal duration measurement system compares a known duration, T1, of a test data signal with the duration, T2, of a state of a signal under test. In one embodiment, if T2 compares favorably with T1, then the circuit generating the signal under test ‘passes.’ Otherwise the signal under test ‘fails,’ and a problem has been identified. Furthermore, in one embodiment, T1 can be selectively adjusted to more accurately measure T2. In one embodiment, the test data signal is allowed to travel a signal path, having a known signal propagation delay time, during a single state of the signal under test. The data signal at the beginning of the state, e.g. during the rise of the signal under test, is compared to the data signal captured at the end of the state, e.g. during the fall of the signal under test. If the initial and captured data signals are the same, then the duration of the state of the signal under test is greater than or equal to the signal propagation delay time.

Abstract: A system includes a data processing core coupled to a system memory employing error correction code (ECC) circuitry. The core includes an indicator of when a correctable system memory error occurs and what address is associated with the error. A watchdog timer is instantiated on a system management device. Periodically, the timer prompts the management device to interrupt the processor and poll the error indicator to determine if a memory error has been detected. If an error is detected, the corresponding physical memory address is recorded. If a predetermined number of consecutive errors associated with a single memory address or range of addresses occurs, an alert is issued. In one embodiment, polling the error indicator is infrequent initially. As additional errors are detected, the polling frequency increases. At higher polling frequencies, the system may require a greater number of consecutive errors before taking additional action.

Abstract: A backup memory, a DMA (direct memory access) controller, and a WDT (watch dog timer) are provided in addition to a CPU (central processing unit), a RAM (random access memory), and a peripheral circuit. The DMA controller exercises control so that respective data of the CPU, RAM and peripheral circuit is saved in the backup memory each time the CPU, being under normal operation, supplies a counter reset signal to the WDT, and so that the data that has been saved in the backup memory is restored to the CPU, the RAM and the peripheral circuit, respectively, if the WDT has detected a program runaway and outputted a time-over signal. Therefore, even in a case where a program runaway has occurred in the CPU, normal operation is permitted to be resumed from midway in the program.

Abstract: A method and apparatus for optical performance monitoring that provides for multi-rate and multi-protocol monitoring includes, identifying a protocol associated with each of a plurality of communication signals using respective data rates extracted therefrom, determining, for each of the plurality of communication signals, a respective bit-error rate (BER), and generating an alarm indicative of BER excursions beyond a protocol appropriate BER threshold level.

Abstract: An early clock fault detection method and circuit for detecting clock faults in a multiprocessing system provides an error system that can be used to shutdown the multiprocessing system or a processor before errors caused by loss of synchronization between multiple processors can propagate from the processor causing storage or other systems to be corrupted. The detection circuit counts cycles of a high-frequency internal processor clock generated by multiplying an external master clock signal and detects whether or not a predetermined number of clock cycles have elapsed between transitions of the external master clock signal. The detection circuit provides a clock fault output within less than a master clock cycle, which can be used to shut down the processor, system or interconnect between processors, preventing loss or corruption of data before the high-frequency clock can drift enough to cause errors.

Abstract: A system and method for dynamically altering a clock speed of a clock signal used for timing of data signal transmissions and receptions within an integrated circuit (IC) device. The system includes a clock generator circuit for providing a clock signal used for timing of data signal transmission and reception within the IC; a monitoring circuit for receiving data transmissions generated at different clock speeds and detecting when a data transmission fail point is achieved at a particular clock speed; and, a device for adjusting the clock speed according to a maximum speed allowed for the IC that avoids the data transmission fail point.

Abstract: In a method for function monitoring of an electronic-mechanical position switch in which the wiper voltage of a potentiometer acted upon by an actuation tappet is evaluated in comparison to a threshold value in order to activate or deactivate electronic contacts, during first or second test intervals a microcontroller interrupts watchdog signals or contact-closing control signals and checks the state of the switching contacts. If the expected state transition of the switching contacts from the closed into the open state does not occur, then the control signals make the transition to the contact-opening signal level or the watchdog signals are discontinued.

Abstract: A counter (2) alters its counter variable (C) on the basis of a clock signal which is generated by an oscillator (3). If the reset signal (CT1) intermittently transmitted by the processor (1) during normal operation is absent, the count variable (C) reaches a first limit value (Cgr1). The counter (2) then sends an interrupt signal (IR) to the processor (1). If the reset signal (CT) continues to be absent and the count variable (C) reaches a second limit value (Cgr2), the counter (2) transmits a hardware reset signal (HWR) to the processor (1). This signal or the result of this signal (HWR) is also used to reset the counter (2), i.e. the count variable (C) is set to a predetermined start value (CSTART). Thus, in the absence of the reset signal (CT1) from the processor (1), an interrupt (IR) and a hardware reset signal (HWR) are cyclically transmitted.

Abstract: A method and apparatus for monitoring the response times of computer system components in order to improve computer system reliability and performance are provided. The method and apparatus are particularly applicable to computer systems with memory circuits, such as SLDRAMs, that have programmable response times. A response time monitoring circuit in the form of a phase detector includes a plurality of flip-flops with the data inputs commonly connected to receive a response ready signal from a component, such as a memory circuit, in response to a command to perform a task. Each clock input of the flip-flop is connected to a clock signal at a different phase of a response period. The outputs of the flip-flops determine the phase at which the response ready signal was generated by the component.

Abstract: A two-MCU system includes a main-MCU and a sub-MCU. When any one of operating keys is operated, an operation signal is applied to the sub-MCU. Thereupon, the sub-MCU detects the operation of the operating key, and makes a timer start to count a time period. The sub-MCU, when no specified command is received from the main-MCU irrespective of a lapse of a predetermined time period, determines that the main-MCU is being in a hang-up state. Then, the sub-MCU applies a reset signal to a reset circuit thereby to reset the main-MCU, and the two-MCU system returns from the hang-up.

Abstract: A safety device for a stored-program control includes a controller which exchanges data with a stored-program control and, via a bus controller and a bus system, with the peripheral to be controlled. A memory is provided, in which safety-relevant data of the stored-program control is stored, which is accessible to the controller.

Abstract: The invention comprises, in various embodiments, a method for monitoring an internal test on a remote computer. The method includes reading a line from the remote computer with a processing unit. The line is capable of sending at least one result signal for the test. The method includes sending a fail signal from the processing unit to a reporting device when none of the new result signals are read during any time period of a preselected length.

Abstract: A virtual routing system includes a number of physical routers. One of the physical routers is the master with respect to a given source of traffic, and the others are backups. If the master router fails, then one of the backup routers becomes the master to provide substantially uninterrupted service through the virtual routing system. A virtual redundant routing protocol (VRRP) can be extended to support sub-second advertising of VRRP packets by a master router a backup router. In some cases, sub-second switching is supported, in which a backup router can become a new master router after less than a second of down time by the original master router. Such responsiveness in a virtual routing system is very useful for many applications, such as voice-over-packet applications in which down time of the routing system for more than one second is unacceptable.

Abstract: The disclosed embodiments relate generally to providing increased data integrity in computer systems and, more particularly, to using a system management processor to overcome a computer system failure because of corrupted programming. A system management processor detects an attempted boot by host computer system and starts a watchdog timer. If the system BIOS or other firmware fails to execute, the watchdog timer expires and the system management processor places the system processor(s) in a reset state. The system management processor provides the address of a back-up BIOS or firmware and releases the system processor(s) from the reset state. The system processor(s) are redirected to the back-up BIOS or firmware and the computer system is able to boot.

Abstract: A system and method for automatically managing a distributed software test execution, management and reporting system that includes a network of test computers for executing a plurality of test jobs and at least one client computer for controlling the test computers is disclosed. The method and system include providing the test computers with a service program for automatically registering availability of the computer and the attributes of the computer with the client computer. The execution requirements of each test job are compared with the attributes associated with the available computers, and the test jobs are dispatched to the computers having matching attributes. The method and system further include providing the service programs with a heartbeat function such that the service programs transmit signals at predefined intervals over the network to indicate activity of each test job running on the corresponding computer.

Abstract: Circuitry for detecting operating system hang conditions is provided. The circuitry includes interrupt logic for receiving system interrupts targeted for a central processing unit. Further included is hang detection logic that is in communication with the interrupt logic. The hang detection logic is capable of determining whether the central processing unit has processed an interrupt within a period of time. Hang resolution logic is further provided for removing the central processing unit from a hang state when it is determined that the interrupt has not been processed within the period of time.

Abstract: A stack frame associated with a procedure that can alter or affect a shared resource where the procedure is associated with a child stack and is declared by a parent stack is marked isolated. Isolated stack frames are allotted an additional predefined interval of processing time before commands such as terminate and interrupt applied to the child stack are executed. If the command is a terminate command, after the additional allotted time interval has passed, both child and parent stacks are terminated. If the command is an interrupt command, after the additional allotted time interval has passed, the child stack is interrupted. If the command is a resource-terminated command, an operator is permitted to allocate more resource time to the task or may terminate both parent and child stacks. If a parent stack is terminated, all child stacks of the parent are terminated.

Abstract: A method for operating a watchdog timer associated with a microcontroller that generates refresh commands for the watchdog timer is provided. The refresh commands are separated by a time interval within a predetermined range. The method includes receiving the refresh commands by the watchdog timer, and generating a microcontroller reset command by the watchdog timer when a time interval separating successively received refresh commands is not within the predetermined range. In particular, the generating includes staring a refresh countdown on each receipt of a refresh command by the watchdog timer. A reset countdown is started if the refresh countdown has timed out, and if the refresh countdown has not timed out when a next refresh command is received, then the next refresh command does not restart the reset countdown. The microcontroller reset command is generated if the reset countdown has timed out.

Abstract: A data processor timer comprising a writeable control register, a look-up table and a loadable counter. The loadable counter operates in a first mode to load the count data field and operates in a second mode an entry from said look-up table specified by the count data field. The loadable counter generating a time out signal upon counting a number of clock pulses equal to said count. The writeable control register preferably includes a mode bit selecting the first or second modes. This invention is suitable for a pre-scalar counter as part of a data processor watchdog timer.

Abstract: A system for tracking changes in technical processes, machines or the like having measurement chains for acquiring measured data, having sensors, sensor lines and interpretation electronics, and having governing software. Interdependent measured quantities are combined into measurement groups, the measurement groups are linked with reference quantities, validity conditions are defined for the measured data, and the measured data is utilized only if the validity conditions are fulfilled. The measured data are examined for errors in the instrumentation. For serious, suddenly occurring malfunctions, an alarm is issued, and malfunctions are reported to the operators.

Abstract: Delivery of energy by a defibrillator or other medical device is inhibited when the processor or software that controls a module of the medical device operates abnormally. A windowed watchdog timer (WWDT) incorporated into one module of the medical device is used to control the operation of other modules of the medical device via a software-based extension technique. As a result, the risk of harm to the patient is reduced compared to medical devices that incorporate over-limit type watchdog timers. In addition, costs associated with implementing WWDTs in multiple modules of the defibrillator are avoided, thereby lowering the overall cost of implementation.

Abstract: A system for effecting recovery of a network involving a plurality of computing apparatuses with each respective computing apparatus hosting at least one respective service, includes: (a) at least one control unit substantially embodied in hardware and coupled with each computing apparatus; and (b) at least one control program substantially embodied in software and distributed among at least one of the computing apparatuses. The system responds to a computing apparatus becoming inoperative by effecting a recovery operation. The recovery operation includes distributing the services hosted by the inoperative computing apparatus as distributed services among operating computing apparatuses and returning the distributed services to the inoperative computing apparatus after the inoperative computing apparatus becomes operative. The at least one control unit and the at least one control program cooperate to effect the recovery operation.

Abstract: A computer system may include a host computer system and a storage device such as a tape device that includes one or more tape drives. The host computer system may be configured to provide commands to the storage device and to initiate a timeout period for each command provided to the storage device. The host computer system may be configured to initiate a first timeout period if a first type of command is provided to the storage device, to initiate a second timeout period if a second type of command is provided to the storage device, and to initiate a third timeout period if a third type of command is provided to the storage device, where the first timeout period, the second timeout period, and the third timeout period each have a different duration.

Abstract: An multimedia synchronization services system has been provided that can synchronize input actions and test data measurements associated with activities of a client/server computer system. The system can be applied to virtual test systems coupled to a contact center to provide time latency measurements between input actions to the calling center and resulting contact center functions.

Abstract: A method and apparatus for operating a source synchronous receiver. In one embodiment, a source synchronous receiver may include a clock receiver comprising a clock detector and a clock signal buffer. The clock detector may be configured to detect a first clock signal and assert a clock detect signal responsive to detecting the first clock signal. The clock buffer may receive the first clock signal and produce a second clock signal, which may be driven to a digital locked loop (DLL) circuit, where the second clock signal is regenerated and driven to a data buffer of the source synchronous receiver. The clock detect signal may be received by a clock verification circuit. The clock verification circuit may be configured to initiate a reset of the source synchronous receiver upon a failure to receive the clock detect signal.

Abstract: A communication network for use in an automobile includes a main electronic control unit (ECU) that communicates with plural sub-ECUs connected to the main ECU through a communication line. Messages transmitted periodically with a certain interval from each sub-ECU to the main ECU and received by the main ECU in a monitoring interval are counted to obtain the number of message receipts. The number of message receipts is compared with a criterion number preset for each sub-ECU, and if the former is smaller than the later, it is determined that the sub-ECU is under failure. Further, if the number of message receipts is smaller than the criterion number as to all of the sub-ECUs, it is determined that there is a failure or failures in the communication line.

Abstract: A service processor surveillance mechanism is provided for multiple partitions. Each partition stores its own official response. The surveillance routine checks to see if it has enough time for the service processor to respond to its previous probe. If sufficient time has not passed, the surveillance code returns to the calling function with the partition's official response. If sufficient time has passed, the surveillance code reads the surveillance byte in nonvolatile random access memory. The surveillance code then determines the current state of the service processor and determines whether the official response needs to be updated. If the surveillance code updates the official response, the partition's official response is set to the updated official response and returns the partition's official response. If the official response has not changed since the last time the partition probed the surveillance byte, then the surveillance code returns a neutral value.

Abstract: A real time based system and a method for monitoring the same are disclosed, in which applications in operation are monitored by a system monitoring module at a constant time period to detect whether they operate abnormally. The system monitoring module detects whether all the applications currently in operation are controlled normally, so that it is possible to effectively detect any abnormal status of the system in the real time environment. Thus, reliability of the real time based system can be improved.

Abstract: Systems and methods for providing automated diagnostic services for a cluster computer system are provided. One embodiment is a method for providing automated diagnostic services for a cluster computer system comprising a plurality of nodes. Each of the plurality of nodes may provide an application to a plurality of clients. Briefly described, one such method comprises the steps of: receiving a current value of a network parameter related to cluster middleware associated with the cluster computer system; analyzing the current value of the network parameter relative to a predetermined reference value for the network parameter; and providing information based on the analysis of the current value relative to the predetermined reference value.

Abstract: An integrated circuit, a client computer system, and a method for using a watchdog timer as a check before changing the system state of a computer system. The integrated circuit includes a first bus interface logic for coupling to a first external bus, a watchdog timer, and logic configured to receive a request for a system reset. The watchdog timer is coupled to receive a reset input upon a predetermined change in a system state. The watchdog timer is further configured to provide an indication in response to an expiration of the watchdog timer. The logic is configured to query the watchdog timer for the expiration of the watchdog timer in response to receiving the request for the system reset.

Abstract: A method of managing at least one client computer program in a managed application environment can include receiving a request from at least one of a plurality of client computer programs to begin a timer. The timer can correspond to an identified task of the client computer program which has been identified as a time-out susceptible task, and which is executing within a particular thread of execution of the client computer program. The timer corresponding to the request and the time-out susceptible task can be selectively started in a separate thread of execution. The identified task can be timed. If the timer expires, a recovery action can be performed corresponding to the time-out susceptible task.

Abstract: In a computer system having a first repeater and a second repeater, the first repeater coupled to the second repeater by a bus, the first repeater operable to transmit a transaction and a control signal to the second repeater, a method, performed by the second repeater, of generating an error comprising: predicting, in a first cycle, that a transaction should be transmitted from the first repeater to the second repeater; determining if a control signal was received within a predetermined number of cycles of the first cycle; and if the control signal is not received within the predetermined number of cycles of the first cycle, then generating an error.

Abstract: A microprocessor runaway monitoring control circuit with which self-diagnosis of a watchdog timer WDT can be carried out safely and cheaply even during operation of the microprocessor (CPU). A microprocessor 101 supplies first and second watchdog clearing signals WD1 and WD2 to first and second watchdog timers WDT1 and WDT2, and when the both of the watchdog clearing signals WD1 and WD2 stop, the microprocessor 101 is reset by way of a logical connector circuit 122. The microprocessor 101 has failure diagnosing means 103 which intentionally stops the first watchdog clearing signal WD1 and diagnoses the response of the first watchdog timer WDT1 on the basis of a monitor signal MN1 and stops the second watchdog clearing signal WD2 and diagnoses the response of the second watchdog timer WDT2 on the basis of a monitor signal MN2, whereby diagnosis of the watchdog timers WDT1, WDT2 is carried out without the microprocessor 101 being stopped.

Abstract: In a monitor apparatus for a sequential-function-chart-type programmable controller, a standard value of an active time of an arbitrary step in a sequential-function-chart program is stored, and the active time of the arbitrary step is measured during execution of the program. An anomalous state of the arbitrary step is detected through comparison between the measured active time and the reference value. Further, data indicating whether each step in the sequential-function-chart program has been executed are stored. The program is displayed such a manner that an anomalous step, a step or steps which have been executed, and a step or steps which have not yet been executed are distinguished from one another.

Abstract: In the present invention, a coordinated hierarchy of timing mechanisms preferably cooperate to report errors at different operational levels of a complex of computing devices. Preferably, each timer is able to identify a failure condition at its own level of operation and transmit a time-out condition to a higher level device which may also be a timer. Upon generation of a time-out condition, a system component experiencing a fault condition preferably continues to operate in a degraded mode, informs devices attempting to communicate with the faulty component of a status of the fault condition, and preferably proceeds to identify and correct a failure which caused the time out condition. The timers may be implemented in hardware or software.

Abstract: A method for operating at least one computing device and at least one monitoring circuit (watchdog) which is allocated to the at least one computing device and which is to be controlled by the computing device according to a specific temporal pattern, in particular, for a control or safety device for a motor vehicle, the computing device being reset if the monitoring circuit fails to be controlled according to the temporal pattern. To synchronize, in as easy a manner as possible, the computing device to the monitoring circuit, subsequent to a start-up of the computing device from a reset mode into a working mode, a time base may be ascertained which elapses subsequent to the start-up of the computing device until a reset of the computing device occurs due to a failure to control the monitoring circuit according to the temporal pattern, and the monitoring circuit is controlled at time intervals that are determined as a function of the time base.

Abstract: Process and apparatus for communication between an Information Handling System (HIS) and a display having On “Screen Display” (OSD) capability. The HIS system includes a processor under control of an operating system, a graphics system and an electronic circuit which operates independently on the processor and the graphics system. The display receives a graphics channel with the graphics signals. An additional service channel is used for the interaction between the host and the display, and also for allowing the independent electronic circuit to have a direct access to the On Screen Display capability of the display. The service channel may be advantageously a DDC/CI communication link, and the electronic circuit may be a hardware monitoring circuit which is operational even before the booting process of the processor. No additional Liquid Crystal Display is thus required.

Abstract: A method, system, and apparatus for isolating fatal data fetch errors to a single partition within a logically partitioned data processing system. In one embodiment, the logically partitioned data processing system includes a plurality of operating systems and a plurality of processors is provided. Each of the operating systems is assigned to a separate one of a plurality of logical partitions. Each of the processors is assigned to one of the plurality of logical partitions. The logically partitioned data processing system also includes a hypervisor for creating and maintaining separation of the plurality of logical partitions. The hypervisor contains services and functions accessed by each of the logical partitions and, to prevent fatal data fetch errors in one partition from effecting other partitions within the logically partitioned data processing system, the hypervisor includes a plurality of data structure areas.

Abstract: A microcomputer including a runaway detection control unit for monitoring a communication between external processing units that are provided outside the microcomputer, and a memory access control unit. When detecting that the communication between an external processing unit and the CPU gets into a runaway state while the CPU is performing a memory access to the external processing unit in a handshaking method, the runaway detection control unit outputs a pseudo acknowledge signal to the memory access control unit, in place of the normal acknowledge signal. When receiving the pseudo acknowledge signal via the memory access control unit, the CPU switches the memory access method for the external processing unit to the fixed waiting mode.

Abstract: A script is created which accurately monitors filesystem usage. Initially, a filesystem is identified to be monitored. Growth parameters for the particular filesystem are stipulated which, if exceeded, will result in notification to an administrator of the system. Thresholds are set for the selected growth parameters. Script execution timing is set, and the script is automatically executed at the preset time intervals. Each time the script executes, a comparison is made between the system specifics and preset growth thresholds. If a filesystem exceeds a threshold, then notification is provided to the system administrator.

Abstract: A watchdog timer including a counter, a watchdog enable mechanism, and a timeout control. The watchdog enable mechanism is set to an enabled state by receiving an enabling input and set to a disabled state only by a power cycle or a hardware reset. The timeout control is coupled to the counter and to the watchdog enable mechanism. The timeout control enables a error signal if the watchdog enable mechanism is enabled and the counter is not updated before completing a count.

Abstract: The present invention provides a method and system for audio data retrieval from an optical media. The method includes reading a sector of audio data from the optical media, the sector comprising a sector data and a sector sub-code; collecting the sector sub-code; correcting any errors in the sector data in a fixed time period; calculating a time offset between a time for the collecting of the sector sub-code and the fixed time period; and matching the corrected sector data to the sector sub-code based on the calculated time offset. A method and system for retrieving audio data from an optical media has been disclosed. The present invention uses a fixed time period for the sector data error correction process. By using a fixed correction time, the sector data and the sector sub-code can be automatically matched based upon an offset calculated from the fixed correction time.

Abstract: Disclosed are a system and method of launching an operating system on a processing system. A firmware interface may be initially launched on a processing system. The firmware interface may comprise logic to attempt launching an operating system on the processing system. Upon detection that the attempt is unsuccessful, the processing system may be automatically reset.

Abstract: Disclosed are systems and methods for controlling transaction draining for error recovery comprising asserting a control signal to prevent system resources associated with a particular error from issuing new requests, dropping transactions tracked by an out-of-order queue, and issuing transactions not tracked by the out-of-order queue.

Abstract: Disclosed are systems and methods for determining time-outs with respect to a plurality of transactions comprising utilizing a first time-out clock for simultaneously determining time-out states with respect to a first set of transactions of the plurality of transactions, and determining when transactions of the first set of transactions have reached a timed-out state of the time-out states.

Abstract: The present invention provides a system and method of detecting a process failure and a network failure in a distributed system. The distributed system includes a plurality of processes, each executing on a host, operable to transmit messages (i.e., heartbeats) to each other on a network. A process in the system is operable to execute a process failure algorithm for detecting failure of a process in the system. The process failure algorithm includes calculating a difference in the period of time to receive a heartbeat from a first processes and a period of time to receive a heartbeat from a second process in the system. If the difference exceeds a process failure threshold, the second process is suspected of failing. A process in the system is also operable to execute a network failure algorithm for detecting failure of a network connecting a plurality of hosts in the system.