Abstract: A method of testing a data connection using at least one test sequence, the method including providing a first bit sequence by a first generator; duplicating the first bit sequence to generate a second bit sequence identical to the first; and generating the at least one test sequence based on the first and second bit sequences and transmitting the at least one test sequence over a data connection to be tested.

Abstract: Failing bus lane detection using syndrome analysis, including a method for receiving a plurality of syndromes of an error detection code, the error detection code associated with a plurality of frames that have been transmitted on a bus that includes a plurality of lanes and is protected by the error detection code. The method includes performing for each of the lanes in each of the syndromes: decoding the syndrome under an assumption that the lane is a failing lane, the decoding outputting a decode result; determining if the decode result is a valid decode; and voting for the lane in response to determining that the decode result is a valid decode. A failing lane is then identified in response to the voting, with the failing lane being characterized by having more votes than at least one other lane on the bus.

Abstract: To increase the number of analog inputs at low cost, an analog input system includes: one or more analog slave units each connected to a bus to which a CPU unit is connected, and each including an A/D-conversion device converting an analog value outputted by an external device into a first digital value, a buffer memory buffering a second digital value to be transferred to the CPU unit, and a nonvolatile storage device containing specific information of its own unit; and an analog master unit connected to the bus and including an operation section performing operation processing based on the specific information stored in the storage device with the first digital value being used as an input, to calculate the second digital value, the master unit performing on each of the slave input units the operation processing and processing of transferring the calculated second digital value to the buffer memory.

Abstract: An apparatus, system, and method are disclosed for resetting and bypassing microcontroller stations. A command module asserts and de-asserts a reset line in response to a command. A reset module resets a microcontroller station if the command module asserts and de-asserts the reset line within a time interval. In addition, the reset module bypasses the microcontroller station if the command module asserts and holds the reset line for a time period exceeding the time interval.

Abstract: A method for detecting a failure in a serial topology. The method may comprise sending a predetermined pattern to a plurality of devices communicatively connected to an initiator in a serial topology; receiving a return result from each of the plurality of devices in response to the predetermined pattern; recognizing a problem associated with a particular device among the plurality of devices, the problem being recognized based on the return result from the particular device; sending a plurality of test patterns to the particular device; receiving a plurality of test results from the particular device in response to the plurality of test patterns; and determining a cause of the problem based on the plurality of test results, the cause of the problem being at least one of: a cable failure and a device failure.

Abstract: A method for maintaining reliable communication between a command initiator and a target device is provided. After the command initiator detects an error corresponding to the target device and a path between the command initiator and the target device, the command initiator performs a downshift evaluation. The initiator maintains a transmission speed if the downshift evaluation determines that forgoing a transmission speed downshift is required, and reduces the transmission speed if the downshift evaluation determines that transmission speed downshift is required. The command initiator then logs the downshift evaluation result and reports any transmission speed change to a user.

Abstract: A control apparatus includes a lower layer control unit configured to perform control of a load, an upper layer control unit configured to control the lower layer control unit, a communication unit configured to perform communication between the upper layer control unit and the lower layer control unit via a communication line, a detection unit configured to detect power supply voltage of the lower layer control unit, wherein the upper layer control unit detects communication abnormality of the communication unit and notifies the communication abnormality, the upper layer control unit notifying abnormality of power supply voltage of the lower layer control unit, in such a manner as to be identified from the communication abnormality of the communication unit.

Abstract: Various embodiments for automated error recovery in a computing storage environment by a processor device are provided. In one embodiment, pursuant to performing one of creating a new and rebuilding an existing logical partition (LPAR) operable in the computing storage environment by a hardware management console (HMC) in communication with the LPAR, at least one failure scenario is evaluated by identifying error code. If a failure is caused by an operation of the HMC and a malfunction of a current network connection, a cleanup operation is performed on at least a portion of a current HMC configuration, an alternative network connection to the current network connection is made, and a retry operation is performed.

Abstract: A method for maintaining reliable communication on a bidirectional communication link is provided. A receiver on the bidirectional communication link detects an error and maintains a count of detected errors. The transmitter on the bidirectional communication link polls the receiver in order to determine the count of detected errors, and performs a downshift evaluation for the bidirectional communication link. In response to performing the downshift evaluation for the bidirectional communication link, the transmitter maintains a transmission speed of the bidirectional communication link if the downshift evaluation determines that forgoing transmission speed downshift is required for the bidirectional communication link, and reduces the transmission speed of the path if the downshift evaluation determines that transmission speed downshift is required for the bidirectional communication link.

Abstract: Methods for managing response data within an information handling system (IHS), where the method includes the step of obtaining response data from at least one component in the IHS, the response data generated in response to receiving a command. The method also includes accumulating the response data from the at least one component to compute a total response time.

Abstract: A method tests hard disk ports located on a motherboard of a computing device. Each of the hard disk ports connects to a respective serial port of a test fixture. The test fixture includes a group of serial ports, a multiplexer and a storage device. Each of the hard disk ports is selected to be tested during the process of hard disk ports test. A data transmission path is formed by building a connection between the storage device and a channel of the multiplexer corresponding to the hard disk port. Data are written to the storage device and read from the storage device through the data transmission path. The hard disk port is working normal if the written data are identical to the read data. The hard disk port is not working normally if the written data are not identical to the read data.

Abstract: An application attempts to use a first protocol stack to send a first message to a server. After attempting to send the first message to the server, the application attempts to use a second protocol stack to send a second message to the server. After attempting to send the second message to the server, the application performs a timeout activity before a timeout period for the second message expires when the first message timed out. Alternatively, when the timeout period for the second message expires and the first message did not time out, the application performs the timeout activity. When the client device received a response to the second message from the server before the timeout period for the second message expires, the application performs a different activity.

Abstract: Auto-detection and configuring systems and methods for interconnected, position dependent control devices are disclosed. Embedded identification and configuration keys are associated with each of the control devices in a network, such that specific connection nodes for each controller may be determined by electronically reading the identification as the control devices are installed. Hardware and software compatibility issues may be detected and resolved, including self configuring of the control devices with the proper software where possible. Otherwise, error conditions are signaled.

Abstract: When a controller identifies a universal serial bus (USB) device connected to a USB interface, it outputs a control signal to close a relay and a first start test signal to an electronic device to test a USB interface of the electronic device. When the test of the USB interface is completed, to the controller adds one to an inside counter, and determines whether the count value reaches a preset count value. If the count value reaches the preset count value, the controller outputs a finish test signal to the electronic device. If the count value does not reach the preset count value, the controller controls the closed relay to open and outputs a second start test signal to close a next relay to test a next USB interface of the electronic device corresponding to the now closed relay.

Abstract: A method and an apparatus for failure notification are provided. The method includes: sending, when it is detected that a failure occurs in a multicast label switch path, failure information to a downstream node of a multicast tree where a failed point locates, where the multicast label switch path is established based on a multicast label distribution protocol; and forwarding the failure information through the downstream node, where the failure information arrives at a leaf node of the multicast tree where the failed point locates. According to the method and the apparatus for failure notification of the present invention, finally, the failure information is transmitted to a leaf node. After the failure information is obtained, the leaf node may take appropriate measure to ensure the normal service and improve the reliability of the network.

Abstract: In described embodiments, a transceiver supports two or more rates using an oversampling clock and data recovery (CDR) circuit sampling high rate data with a predetermined CDR sampling clock. A timing recovery circuit detects and accounts for extra or missing samples when oversampling lower rate data. An edge detector detects each actual data symbol edge and provides for an edge decision offset in a current instant's block of samples. An edge error is generated from the previous instant's actual and calculated edges; and an edge distance between actual edges of the current and previous instants is generated. Filtered edge distance and error are combined to generate a calculated edge position for the data symbol edge for the current instant. The edge decision offset is applied to the current calculated edge position to identify a sample value to generate a decision for the data symbol to detect the current data value.

Abstract: In a method for correcting errors occurring in attention (AT) commands of a mobile device, the mobile device includes a first user identity module (UIM) chipset, a second UIM chipset, a buffer and a timer. The method sets a response time for a communication between the first UIM chipset and the second chipset according to an AT command, backups the AT command into the buffer, and counts a communication time using the timer. When the communication time exceeds the response time, the method restarts the first UIM chipset using a watchdog timer and restarts the second UIM chipset by resetting voltage levels of I/O pins of the second UIM chipset. The method further clears the communication data stored in the buffer, reads the AT command from the buffer and resends the AT command to control the first UIM chipset to communicate with the UIM second chipset normally.

Abstract: A method for accurately tracking fault status in a computer system. The method includes storing a prior state for a sensor associated with a component of the computer system and receiving a sensor reading. When the prior state indicates the sensor was unavailable or unreadable such as when the component was removed, the method includes resending or re-emitting a faulty event to the fault diagnosing module, e.g., after reinsertion of the component in the computer system while it is still faulty. The method may include, prior to the triggering of the resending of the faulty event, determining that the sensor is in a non-nominal state. The method may also include storing in the data storage a definition of a nominal state for the sensor such that the determining the sensor is in the non-nominal state includes comparing one or more sensor readings with the nominal state definition.

Abstract: An I/O device includes a host interface that may receive and process transaction packets sent by a number of processing units, with each processing unit corresponding to a respective root complex. The host interface includes an error handling unit having error logic implemented in hardware that may determine, as each packet is received, whether each transaction packet has an error and to store information corresponding to any detected errors. The error handling unit may include an error processor that may be configured to execute error processing instructions to determine any error processing operations based upon the information. The error processor may also generate and send one or more instruction operations, each corresponding to a particular error processing operation. The error handling unit may also include an error processing unit that may execute the one or more instruction operations to perform the particular error processing operations.

Abstract: A method and system for taking over devices are provided. In a solution, a first control board first performs topology discovery on a Peripheral Component Interconnect Express (PCIE) bus, and reserves resources for a Switch (SW) where a NON-Transparent (NT) bridge is located and devices connected to down ports of the SW according to a set resource reservation policy when the topology discovery proceeds to the NT bridge, where the SW and the devices are currently controlled by a second control board. After the SW and the devices are taken over from the second control board, the resource reserved in advance may be allocated to the SW and the devices, so that the devices that are taken over operate normally under control of the first control board. Dual control is implemented through direct taking over devices, and a response speed for processing a device request is improved.

Abstract: The disk controller has a plurality of channel control units, a plurality of cache memories, a plurality of disk control units, and a plurality of internal switch units. Each channel control unit or disk control unit sends to one of the cache memory units a request packet requesting execution of processing. The cache memory unit sends a response packet in response to the received request packet. Each internal switch unit monitors the request packet sent from the channel control unit or disk control unit, and judges whether or not the response packet to the request packet has passed through the internal switch unit within a first given time period since the passage of the request packet. In the case where the response packet has not passed through the internal switch unit within the first given time period, the internal switch unit sends a failure notification.

Abstract: Disclosed are methods and apparatus for error handling within jobs that utilize a plurality of tasks for data transfer of individual data records to a storage destination. For each task, one or more failed records may be logged to a file for later insertion. If a high percentage of a task's output (e.g., writes to another data storage system) is determined to be failing, the task short-circuits itself. Each task is also configured to perform checkpoint logging as the task completes work. If the entire job later short-circuits and is to be restarted, the restarted job only repeats a minimal amount of previously completed work for the tasks which have not already completed their data insertions. Together, these techniques can ensure that in the face of periodic failures, the job completes long-running job in a minimal time with minimal effects.

Abstract: A multiprocessor computer system comprises one or more watchdog timers operable to detect failure of a memory operation based on passage of a certain timing period from a memory operation being issued without a valid response. An error handler is operable to take corrective action regarding the failed memory operation, such as to provide at least one of hardware state management and application state management.

Abstract: A data processing system includes an input/output (I/O) host bridge to which at least one I/O adapter is coupled by an I/O link. In a register of the I/O host bridge, a configuration partitionable endpoint (PE) field is set to identify a PE to be used for an I/O configuration operation. Thereafter, the host bridge initiates the I/O configuration operation on the I/O link and determines if an error occurred for the I/O configuration operation. In response to a determination that an error occurred for the I/O configuration operation, an error state is set in the I/O host bridge only for the PE indicated in the configuration PE field of the register in the I/O host bridge, wherein I/O configuration errors are isolated to particular PEs.

Abstract: A semiconductor device including an electronic circuit, a memory, and an error detecting module. The electronic circuit is configured to receive an input signal having been generated by a test module, and generate an output signal based on the input signal. The memory is configured to store a predetermined output value that is expected to be output from the electronic circuit based on the electronic receiving the input signal, wherein the predetermined output value is stored in the memory prior to the input signal being generated by the test module. The error detecting module is configured to (i) generate a sample value of the output signal, (ii) compare the sample value of the output signal to the predetermined output value stored in the memory, and (iii) generate a result signal that indicates whether the sample value of the output signal matches the predetermined output value.

Abstract: A network monitor and control apparatus for controlling the monitoring of a network are provided. The network monitor includes an error monitor including an error information gatherer for gathering error information of a monitor target apparatus; and a monitor result notifier for notifying of monitor results, wherein if there are N types of monitor target functions, the error monitor includes N error information gatherers for the respective N types of monitor target functions (N=1, 2, 3, . . . ) and wherein each of the N error information gatherers gathers the error information from one of an existing monitor target apparatus and a newly added monitor target apparatus on a per monitor target function basis.

Abstract: A device may detect and report failure in point-to-point Ethernet links. In one implementation, the device may determine, based on a periodic timing signal, whether at least one packet was received on an incoming Ethernet link during a previous period of the periodic timing signal. The device may update an entry in a circular buffer to indicate whether the at least one packet was received during the previous period of the periodic timing signal and analyze the circular buffer to determine whether there is a signal failure on the incoming Ethernet link.

Abstract: A wireless USB hub for connecting a plurality of remote peripheral devices to a computer for communication therewith without the need to physically connect the peripheral devices to the hub via a cable connection. The wireless USB hub includes a receiver for receiving wireless data transmissions from one or more remote peripheral devices. The wireless USB hub further includes a hub controller for passing appropriate peripheral device information to a USB upstream port and then to a computer.

Abstract: Various embodiments herein include at least one of systems, methods, and software to detect and reduce messages from network entity management clients that are not utilized by a network management system. Once identified, the network management system may send a command to the network entity management clients to no longer send particular message types to the network management system. The network management system may also, or alternatively configured to take no action when such messages are subsequently received.

Abstract: An electronic adapter device and an electronic system that comprises the electronic adapter device are described. The electronic adapter device comprises a device and a redundant device able to receive data from a first plurality of electronic devices and redundant data from a second plurality of electronic devices, and able to select therefrom first data and first redundant data respectively. The electronic adapter device also comprises a controller able to receive the selected first data and the selected first redundant data and is able to generate therefrom an error signal indicating a fault in an electronic device of the first plurality or a fault in the device.

Abstract: Methods and systems for capturing error information regarding a Serial Advanced Technology Attachment (SATA). An initiator device is enhanced in accordance with features and aspects hereof to detect an error condition in operation of the system and to transmit error information to the SATA target device during a soft reset condition applied to the SATA target device. The SATA target device discards all such frames received during the soft reset condition until the initiator device clears the soft reset condition. The error information may be captured for further analysis and debug of the error condition by suitable error analyzer equipment such as a SATA bus analyzer. The initiator device may be a SATA initiator or a Serial Attached SCSI (SAS) initiator using the SATA Tunneling Protocol (STP). Features and aspects hereof may also include a SAS/SATA bridge device coupling a SAS initiator to the SATA target device.

Abstract: A network adaptor which performs CPU loads and stores to remote memory over network fabrics. The network adaptor receives a transfer request from a compute node and converts the request to a remote transfer request, which is transmitted to the network. The network adaptor then monitors the network connection for a remote completion response. When the network adaptor receives the remote completion response within a specific time period, the network adaptor transmits a first completion response to the compute node. If the network adaptor does not receive the remote completion response within the specific time period, the network adaptor transmits an “early completion response” to the compute node. The network adaptor continues to monitor for the actual response. This allows the compute node to continue processing without having to wait for the actual response to be received. The method handles small payloads efficiently and also accounts for long completion delays.

Abstract: An apparatus, and an associated method, reports when incidence of email or other data-message communication of a wireless network system. An analyzer analyzes logged information and determines the incidence, such as by calculating a ratio, of delayed versus timely message communications. If the ratio, or other indication, is beyond a threshold, a reporter generates a report to alert the high incidence of delayed communications.

Abstract: A data processing system includes an input/output (I/O) host bridge to which at least one I/O adapter is coupled by an I/O link. In a register of the I/O host bridge, a configuration partitionable endpoint (PE) field is set to identify a PE to be used for an I/O configuration operation. Thereafter, the host bridge initiates the I/O configuration operation on the I/O link and determines if an error occurred for the I/O configuration operation. In response to a determination that an error occurred for the I/O configuration operation, an error state is set in the I/O host bridge only for the PE indicated in the configuration PE field of the register in the I/O host bridge, wherein I/O configuration errors are isolated to particular PEs.

Abstract: A method to minimize performance degradation during communication path failure in a data processing system, comprising a host computer, a storage controller, and a plurality of physical communication paths in communication with the host computer and the storage controller, where the method establishes a threshold communication path error rate, and determines an (i)th actual communication path error rate for an (i)th physical communication path, wherein that (i)th communication path is one of the plurality of physical communication paths. If the (i)th actual communication path error rate is greater than the threshold communication path error rate, the method discontinues use of the (i)th physical communication path.

Abstract: A method and circuit for implementing enhanced memory reliability using memory scrub operations to determine a frequency of intermittent correctable errors, and a design structure on which the subject circuit resides are provided. A memory scrub for intermittent performs at least two reads before moving to a next memory scrub address. A number of intermittent errors is tracked where an intermittent error is identified, responsive to identifying one failing read and one passing read of the at least two reads.

Abstract: A computer program product, apparatus, and method for handling exception condition feedback at a channel subsystem of an I/O processing system using data from a control unit are provided. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes sending a command message to the control unit, and receiving a response message in response to the command message. The response message includes exception condition feedback identifying a termination reason code in response to unsuccessful execution of at least one command in the command message. The method also includes interrupting a CPU in the I/O processing system, and reporting status associated with the exception condition feedback to the CPU in an interrupt response block.

Abstract: A redundancy manager manages commands to peripheral devices in a computer system. These peripheral devices have multiple pathways connecting it to the computer system. The redundancy manager determines the number of independent pathways connected to the peripheral device, presents only one logical device to the operating system and any device driver and any other command or device processing logic in the command path before the redundancy manager. For each incoming command, the redundancy manager determines which pathways are properly functioning and selects the best pathway for the command based at least partly upon a penalty model where a path may be temporarily penalized by not including the pathway in the path selection process for a predetermined time. The redundancy manager further reroutes the command to an alternate path and resets the device for an alternate path that is not penalized or has otherwise failed.

Abstract: An I/O device includes a host interface that may be configured to receive and process a plurality of transaction packets sent by a number of processing units, with each processing unit corresponding to a respective root complex. The host interface includes an error handling unit having error logic implemented in hardware that may be configured to determine whether each transaction packet has an error and to store information corresponding to any detected errors within a storage. More particularly, the error handling unit may perform the error detection and capture of the error information as the transaction packets are received, or in real time, while the error handling unit may include firmware that may subsequently process the information corresponding to the detected errors.

Abstract: A master includes a unit configured to register, for each slave, an expected communication time needed to exchange control data; a unit configured to register a slave in which a communication error is detected during exchange of the control data in a communication period; and a unit configured to re-execute exchange of the control data with the registered slave in the same communication period as that in which the communication error is detected. The unit configured to re-execute exchange of control data calculates a remaining resending time that can be used to re-execute exchange of the control data and, when the remaining resending time is longer than the expected communication time of the registered slave, resends the control data.

Abstract: A method, device, and system are disclosed. In one embodiment method includes determining a left edge and right edge of a valid data eye for a memory. The method continues by periodically checking the left and right edges for movement during operation of the memory. If movement is detected, the method retrains the valid data eye with an updated left edge and right edge.

Abstract: A controller capable of self-monitoring, a redundant storage system having the same, and its method are proposed. Each controller is arranged with a self-monitoring operating circuit and a watchdog unit. The self-monitoring operating circuit can periodically issue a confirmation signal to the watchdog unit. The watchdog unit comprises a counter unit for counting a predetermined time interval, and if it does not receive the confirmation signal issued by the self-monitoring operating circuit over the predetermined time interval, it will send out an output signal to the self-monitoring operating circuit. The self-monitoring operating circuit will then generate a plurality of global reset signals to shut down the entire operation of the controller. Another controller will take over the functions of the shut-down controller.

Abstract: A method of validating multi-cluster computer interconnects includes calculating a cable interconnect table associated with the multi-cluster computer, and distributing the cable interconnect table to a first transceiver in the first computer cluster and a second transceiver in the second computer cluster. The method also includes connecting a first end of a cable to the first transceiver and a second end of the cable to the second transceiver, transmitting a first neighbor identification from the first cluster to the second cluster, and a second neighbor identification from the second cluster to the first cluster, comparing the first neighbor identification with a desired first neighbor identification from the cable interconnect table to establish a first comparison result and the second neighbor identification with a desired second identification from the cable interconnect table to establish a second comparison result, and generating an alert based on the first and second comparison results.

Abstract: An Electrical Fast Transient/Burst (EFT/B) detection and recovery system for a Universal Serial Bus (USB) device. The system includes a USB core and a burst controller. The USB core provides serial communications with a host device through a USB data channel. The burst controller is coupled to the USB core. The burst controller detects an EFT/B event and automatically reconnects the USB core to the host device in response to recognition of a suspend state of the USB core by the host device.

Abstract: A plurality of integrated circuits in a system, each having a program memory loaded with different sections of a program, and a second memory. The integrated circuits perform the program, such that, when one of the integrated circuits requires a portion of the program, which is contained in its own program memory, it extracts it from the program memory and uses it, but when it requires a portion of the program, which is not contained in its own program memory, it reads it from the program memory of one of the other integrated circuits into its second memory and runs that portion of the program from there. In one example, the system is a line card, and the program is specific to one DSL protocol.

Abstract: A storage subsystem has a plurality of storage devices. An indication of failure of at least one of the plurality of storage devices is detected. In response to detecting the indication of failure, monitoring is performed for a further condition. According to the monitored further condition, it is determined whether the at least one storage device has failed or whether communication has been lost to the storage subsystem. In response to determining that communication has been lost, state information of the storage subsystem is preserved to enable restoration of the storage subsystem after communication to the storage subsystem is recovered.

Abstract: A method for controlling an execution of a first DMA task, the method includes comprises monitoring an execution of the first DMA task, the method characterized by including defining a first DMA task execution interval and a first DMA task execution sub-interval; and performing a first possible timing violation responsive operation if the first DMA task was not completed during the first DMA task execution sub-interval. A device having a first DMA task controlling capabilities, the device includes a memory unit; characterized by including a DMA controller that is adapted to monitor an execution of the first DMA task that involves an access to the memory unit, and to perform a first possible timing violation responsive operation if the first DMA task was not completed during a first DMA task execution sub-interval.

Abstract: An apparatus and method are provided for connecting a host Enterprise System Connection Architecture (ESCON) Input/Output (I/O) interface to a cache of a data storage system. The apparatus includes (a) a set of at least 4 pipelines, each pipeline being coupled on a first end to the host ESCON I/O interface and being coupled on a second end to the cache, (b) a plurality of line processors, each line processor controlling one or more of the pipelines of the set of pipelines, and (c) in each pipeline, a protocol engine, the protocol engine configured to distinguish user data from frame header data and separate the user data from the frame header data for transport over the pipeline.

Abstract: An automatic testing system and method for judging whether a universal serial bus device is configured to a computer are provided. The automatic testing system includes a computer and a testing device for testing the universal serial bus device. By judging whether the universal serial bus device is configured to the computer, the automatic testing system could determine the timing of performing an automatic testing procedure on the universal serial bus device.

Abstract: Method, system and computer program product embodiments for, in an input/output (I/O) link handling complex instruction chains, a messaging scheme incorporating a method of error recovery between an initiator processor and a receiver processor, are provided. An operation initiation message is been sent from the initiator processor to the receiver processor for the receiver processor to begin work on an operation. If determined to be necessary, a terminate operation message is sent from the initiator processor to the receiver processor. The initiator processor withholds sending additional messages for the operation until a terminate operation response message is received. Once the terminate operation message is received, outstanding messages in process are flushed from the receiver processor. The receiver processor withholds sending additional messages to the initiator processor as the outstanding messages are completed.