Abstract: A computer program product, apparatus, and method for providing exception condition feedback at a control unit to a channel subsystem in an I/O processing system are provided. The computer program product includes a tangible storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes receiving a command message at the control unit from the channel subsystem, and detecting an exception condition in response to unsuccessful execution of at least one command in the command message. The method further includes identifying a termination reason code associated with the exception condition, writing the termination reason code to a response message, and sending the response message to the channel subsystem.

Abstract: In a server composed of a server module having a processor in it, an I/O module having an I/O extension slot for accommodating an I/O extension adapter to expand the server's I/O capability, and a management module managing the entire server, the server module and the I/O extension slot (and through it, ultimately the I/O extension adapter) are interconnected using a PCI Express interface and the I/O module and the management module are interconnected using a special interface carrying detection information indicating whether an I/O extension adapter is actually mounted on the I/O extension slot. In the event of a link failure on the PCI Express interface, link recovery is attempted by grasping the status of the link based on the detection information obtained through the special interface.

Abstract: A system and method enables a file server, to support multi path input/output operations for Fibre Channel devices. Upon each Fibre Channel Arbitrated Loop initialization event generated, the system and method updates a path and device instance to track multiple paths to a given device. While the file server is attempting input/output operations, the failure of a given path can be corrected by the use of another path associated with a given device. The data structures generated by the low levels of the storage operating system are exposed for use by upper level services for routing a storage device identification purposes.

Abstract: A method for automatically detecting and correcting one or more hang conditions within one or more of a master device and target device of a serial bus interface when one or more signals are held in an invalid state. A hang timer monitors one or more operations of the serial bus when the serial bus is participating in a serial bus transfer. If the transfer does not end before the bus timeout value has been exceeded, the hang timer will issue a reset to the state machine forcing the state machine back to an idle state. The hang timer will also disable the serial bus drivers of the state machine, whereby the hang condition is corrected.

Abstract: A computer program product, apparatus and method for managing recovery and control of a communications link via out-of-band signaling. An exemplary embodiment includes sending a command, sending an invalidate request to a buffer associated with the command and receiving a response to the invalidate request at least one of prior to the command reaching the recipient and after the command reaching the recipient.

Abstract: A method and system for improving communications for systems (200) including at least one communications protocol (CP) enabled server device (206, . . . , 212). The method comprises performing a first diagnostic process (400). The first diagnostic process includes classifying at least one CP enabled server device as a malfunctioning device or an operational device. The method also includes preventing the CP enabled server device from participating in write or read transactions if it is classified as a malfunctioning device in the first diagnostic process. The CP enabled server device is prevented from participating in write or read transaction until the CP enabled server devices is reclassified in a subsequent repetition of the first diagnostic process as an operational device. The method further includes performing a write or read process with the CP enabled server device if it is classified as an operational device in the first diagnostic process.

Abstract: A system and method for verifying system-on-chip interconnect includes a first linear feedback shift register coupled to an output interface of a first system-on-chip component, a second linear feedback shift register instantiated in a second system-on-chip component, and a comparator coupled to the second linear feedback shift register and the input interface of the second system-on-chip. Another method for verifying includes generating a pseudo-random number sequence with the first linear feedback shift register and the second linear feedback shift register using an identical first initial state, and comparing an output of the first linear feedback shift register with an output of the second linear feedback shift register and reporting a miss-compare.

Abstract: A system for testing hardware components includes a test pattern injector and a test pattern detector coupled to verification paths that pass through hardware components. The test pattern injector generates unique test patterns. A test pattern tests hardware features of the hardware components of a corresponding verification path. The test pattern injector injects the test patterns into the corresponding verification paths. The test pattern detector establishes expected test patterns. An expected test pattern matches an injected test pattern of a corresponding verification path. The test pattern detector determines whether received test patterns match the expected test patterns.

Abstract: A failover method for a cluster computer system in which a plurality of computers sharing a resource are connected by a heartbeat path for providing each computer with lines for monitoring operations of the other computers and a reset path. Resetting may be conducted based upon a registered priority for resetting the computers.

Abstract: A semiconductor device comprises: a task state storage configured to store an executing state of a processing task of software executed by a CPU and to output an executing state signal to show the executing state of the processing task; a task validity judging section configured to acquire an interruption signal corresponding to the processing task based on a control of the CPU and the execution state signal, and to output a valid signal when the processing task is executed validly; a clear signal output section configured to output a clear signal in response to the valid signal; and a watchdog timer configured to clear a timer count value when the clear signal is acquired within a prescribed time and to output a reset signal when the clear signal is not acquired within the prescribed time.

Abstract: The present invention is a system and method for supporting an alternative peer-to-peer communication over a network in a SAS cluster when a node cannot communicate with another node through a normal I/O bus (Serial SCSI bus). At startup, driver may establish the alternative path for communication but may not use it as long as there is an I/O Path available. In the present invention, two types of P2P calls, such as event notification calls and cluster operation calls may be supported.

Abstract: A method of validating multi-cluster computer interconnects includes calculating a cable interconnect table associated with the multi-cluster computer, and distributing the cable interconnect table to a first transceiver in the first computer cluster and a second transceiver in the second computer cluster. The method also includes connecting a first end of a cable to the first transceiver and a second end of the cable to the second transceiver, transmitting a first neighbor identification from the first cluster to the second cluster, and a second neighbor identification from the second cluster to the first cluster, comparing the first neighbor identification with a desired first neighbor identification from the cable interconnect table to establish a first comparison result and the second neighbor identification with a desired second identification from the cable interconnect table to establish a second comparison result, and generating an alert based on the first and second comparison results.

Abstract: A configuration is such as to change a mode setup of other crossbars influenced by an error occurring in one of plural crossbars from a first mode to a second mode for operating each of them independently (i.e., in a singularization mode) in the case of placing plural crossbars (i.e., crossbar units) for connecting incorporated units (i.e., processing units) and operating the plural crossbars in the first mode (i.e., a dualized mode) for dualizing them, thereby continuing an operation of a system by using a normally operable part when an error occurs in a part of the system.

Abstract: A master includes a unit configured to register, for each slave, an expected communication time needed to exchange control data; a unit configured to register a slave in which a communication error is detected during exchange of the control data in a communication period; and a unit configured to re-execute exchange of the control data with the registered slave in the same communication period as that in which the communication error is detected. The unit configured to re-execute exchange of control data calculates a remaining resending time that can be used to re-execute exchange of the control data and, when the remaining resending time is longer than the expected communication time of the registered slave, resends the control data.

Abstract: Method and application server for providing an asynchronous error notification from an application server to an application server controller in a network is provided. The method at the application server includes generating an error message when an error occurs at/during Open Service Gateway initiative (OSGi) framework runtime. The method also includes converting the error message as a Universal Plug and Play (UPnP) event. Moreover, the method includes providing the UPnP event comprising error information to the application server controller. The application server includes a receiver configured to receive a command from an application server controller to install an application in an Open Service Gateway initiative (OSGi) framework available at the application server. The application server also includes a processor configured to generate an error message when an error occurs during installation of the application in the framework and convert the error message as a Universal Plug and Play (UPnP) event.

Abstract: A method of detecting signal faults comprises sampling at least three redundant signals; calculating a difference signal for each unique pair-wise comparison of the at least three sampled redundant signals; comparing each difference signal to an expected distribution for the difference signals; and determining if one of the at least three redundant signals is faulty based on the comparison of each difference signal to the expected distribution.

Abstract: A mechanism is provided for providing reliability of communication. A first processor determines a current state of links coupled to ports of a first processor of the data processing system. Each port of the first processor comprises a plurality of links to a corresponding port on a second processor of the data processing system. The current state of the links indicates a level of error associated with each link. The first processor determines, for each link, if a level of error associated with the link exceeds a threshold. For each link whose level of error exceeds the threshold, the first processor tags the link with an error identifier in a switch associated with the ports of the first processor. The first processor reduces a level of usage for transmitting data on ports associated with links tagged with the error identifier.

Abstract: A sequencing control circuit includes a chip (30), a first control circuit (10), a second control circuit (20), and a lagging voltage terminal (700). The chip is connected to a first voltage terminal (100) and a second voltage terminal (300). The first control circuit is connected to the chip. The second control circuit is connected to a signal terminal (600) of an electronic component. The lagging voltage terminal is connected to the first control circuit for providing a signal posterior to a signal from the first voltage terminal. When the lagging voltage terminal and the signal terminal both input a high level signal, the output terminal of the first control circuit and the second control circuit both output a high level signal, thereby ensuring that the signal from the second voltage terminal is posterior to the signal from the first voltage terminal being input to the chip.

Abstract: Disclosed is an automation system (1) for executing safety-relevant automation functions. Said automation system (1) comprises one or several control componentries (10) and one or several input/output componentries (30, 30?,50) that are connected thereto. The control componentry (10) is provided with standard program parts (11, 12) and fail-safe program parts (13, 14) to communicate with the connected input/output componentries (30, 30?,50) via corresponding standard bus protocols (S) and fail-safe bus protocols (F). At least one of the input-output componentries (30) is controlled by both the standard program parts (11, 12) via the communicated standard bus protocol (S) and the fail-safe program parts (13, 14) via the communicated fail-safe bus protocol (F), said fail-safe bus protocol (F) having greater priority for said input/output componentry (30) than the standard bus protocol (S).

Abstract: A system controlling apparatus includes a renewal detecting unit that acquires FWD data from an FWD of an operations system core I/O device bridge and stores the acquired FWD data in an FWD data storing unit. If an operations system core I/O device bridge fails, an FWD data copy processing unit copies the FWD data to an FWD of a standby system core I/O device bridge; and a system is rebooted after an operations bridge switchover processing unit switches OFF the operations system core I/O device bridge and switches ON the standby system core I/O device bridge.

Abstract: A master includes a unit configured to register, for each slave, an expected communication time needed to exchange control data; a unit configured to register a slave in which a communication error is detected during exchange of the control data in a communication period; and a unit configured to re-execute exchange of the control data with the registered slave in the same communication period as that in which the communication error is detected. The unit configured to re-execute exchange of control data calculates a remaining resending time that can be used to re-execute exchange of the control data and, when the remaining resending time is longer than the expected communication time of the registered slave, resends the control data.

Abstract: The emulation of a data processing I/O protocol employs a process which obviates the need to consider hardware specific functionality for which emulation is not an optimal solution. The particular protocol described in exemplary fashion herein is the OSA protocol as defined by Open System Adapter standards. The use of this emulation is also seen to leave in place all of the software tools otherwise employed.

Abstract: A system and method enables a file server, to support multi path input/output operations for Fibre Channel devices. Upon each Fibre Channel Arbitrated Loop initialization event generated, the system and method updates a path and device instance to track multiple paths to a given device. While the file server is attempting input/output operations, the failure of a given path can be corrected by the use of another path associated with a given device. The data structures generated by the low levels of the storage operating system are exposed for use by upper level services for routing a storage device identification purposes.

Abstract: A system and method for creating different start cache and bus states using multiple test patterns for processor design verification and validation is presented. A test pattern generator/tester re-uses test patterns in different configurations that alter cache states and translation lookaside buffer (TLB) states, which produces different timing scenarios on a broadband bus. The test pattern generator/tester creates multiple test patterns for a multi-processor system and executes the test patterns repeatedly in different configurations without rebuilding the test patterns. This enables a system to dedicate more time executing the test patterns instead of building the test patterns. By repeatedly executing the same test patterns in a different configuration, the invention described herein produces different start cache states, different TLB states, along with other processor units, each time the test patterns execute that, in turn, changes the bus timing.

Abstract: An Electrical Fast Transient/Burst (EFT/B) detection and recovery system for a Universal Serial Bus (USB) device. The system includes a USB core and a burst controller. The USB core provides serial communications with a host device through a USB data channel. The burst controller is coupled to the USB core. The burst controller detects an EFT/B event and automatically reconnects the USB core to the host device in response to recognition of a suspend state of the USB core by the host device.

Abstract: The present invention assesses memory (DIMM) strength by calculating frequency content of a radiated field which is collected by an apparatus, such as a dipole antenna. Radiated field is created by accelerated charge, which is a function of the slew rate or DIMM strength. Radiated power is directly proportional to the frequency at which bits are driven. By separating the radiated field from the near field or stored field, the DIMM strength content is isolated from other functional DIMM issues, such as tRCD latency, refresh cycles, addressing mode, etc. By examining the radiated power, the disadvantages of the prior art, such as by probing the DIMM's contacts, are avoided.

Abstract: A PCI Express link state management system and method thereof is disclosed. The PCI Express link state management system includes an upstream device, a downstream device and a link. The upstream device outputs a configuration request to the downstream device to change a device power state of the downstream device. At the time, the link is in a first link state. The downstream device outputs a power entering signal to the upstream device and counts a time period. The link enters to a recovery state and further then return to the first link state if the downstream device does not receive a power request acknowledging signal before the time period is expired.

Abstract: A method and system for testing a modular data-processing component. Register information associated with a modular data-processing component to be tested at a test location can be identified and stored. The modular data-processing component can then be tested and removed from said test location. Thereafter, the register information can be retrieved and provided for use with testing of a new data-processing component at said test location without losing said register information during testing of multiple modular data-processing components. The register information can be, for example, PCI configuration data and the modular data-processing component can be an HAB.

Abstract: In information processing between computers which perform a remote operation via a network, all or a part of process information being executed by an operation target and data for use in a process are transmitted beforehand to an operation unit, and the operation unit continues the processing by use of the process information transmitted beforehand when connection via the network for communication between the computers is interrupted or cut. When it is detected that the communication returns to a normal state, the process information being executed by the operation unit and the data for use in the process are transmitted to the operation target, and the operation target continues execution of an information processing program by use of the received process information and the data for use in the process.

Abstract: An image sensing device includes an image sensing unit, an interface unit, a control endpoint, an isochronous endpoint, a bulk endpoint, an interrupt endpoint, and an interface unit controller. The image sensing unit senses a moving image and a still image. The interface unit is connected to an external device. The control endpoint receives from the external device a command requesting transfer of the still image. The isochronous endpoint transfers the moving image sensed by the image sensing unit to the external device. The bulk endpoint transfers the still image sensed by the image sensing unit to the external device. The interrupt endpoint transfers error information. The error information includes information indicating that an error has occurred during sensing of the still image. The interface unit controller transfers the error information to the external device through the interrupt endpoint in response to the occurrence of the error.

Abstract: A computer-implemented method, apparatus, and computer program product are disclosed for routing error messages in a multiple host computer system environment to only those host computer systems that are affected by the error. The environment includes multiple host computer systems that share multiple devices utilizing a switched fabric. An error is detected in one of the devices. Routing tables that are stored in fabric devices in the fabric are used to identify ones of the host computer systems that are affected by the error. An error message that identifies the error is routed to only the identified ones of the host computer systems.

Abstract: A test method for verifying installation validity of a peripheral component interconnected (PCI) devices on an electronic device having a test module, comprises the steps of: (a) storing information of onboard devices and slots on motherboards of different electronic devices and information of PCI devices added in the slots of the motherboards in a first data storing device; (b) storing a bill of material (BOM) showing all possible configurations of the different computers in a second data storing device; (c) generating a configuration file according to the BOM and information of the motherboards and PCI devices; (d) the test module in the computer checking actual hardware configuration of the computer and comparing the actual configuration with the corresponding information recorded in the configuration file; (e) outputting a test result.

Abstract: A redundant storage controller system that robustly provides failure analysis information (FAI) to an operator of the system is disclosed. The system includes first and second storage controllers in communication with one another, such as via a PCI-Express link. When one of the controllers fails, the FAI is transferred from the failed controller to the surviving controller over the link. The operator issues a command to the surviving storage controller, which responsively provides the FAI. In one embodiment, the failed storage controller writes the FAI to the second storage controller. In one embodiment, each storage controller periodically writes the FAI before there is a failure. In one embodiment, the second storage controller reads the FAI from the failed storage controller. The FAI may include boot logs, crash logs, debug logs, and event logs. The FAI may also be written to a disk drive connected to the controllers.

Abstract: Method, apparatus and system for isolating input/output adapter error domains in a data processing system. Errors occurring in one input/output adapter are isolated from other input/output adapters of the data processing system by functionality in a host bridge that connects the input/output adapters to a system bus of the data processing system, thus permitting the use of low cost, industry standard switches and bridges external to the host bridge.

Abstract: A SAS expander adaptively configures a Serial-Attached-SCSI (SAS) PHY to accommodate varying lengths of a cable coupling the PHY to a remote PHY. The expander (a) configures the SAS PHY with settings of an entry of a table of PHY configuration settings, each entry in the table having different PHY configuration setting values; (b) clears a counter; (c) operates the PHY to communicate with the remote PHY for a monitoring period, after configuring the PHY and clearing the counter; (d) increments the counter when the PHY detects a PHY event during the monitoring period, and otherwise decrements the counter; (e) repeats steps (c) and (d) unless the counter rises above a threshold; and (f) when the counter rises above the threshold, repeats steps (a) through (e), wherein step (a) is performed with the settings of a different entry of the table.

Abstract: A semiconductor device that includes a module under test that is integrated with the semiconductor device, that receives an input signal from a test module, and that provides an output signal to at least one output terminal based on the input signal. An error detecting module is integrated with the semiconductor device, samples values of the output signal, and outputs the sampled values to the test module.

Abstract: Systems and methods for providing collision detection in a memory system including a memory system for storing and retrieving data for a processing system. The memory system includes resource scheduling conflict logic for monitoring one or more memory resources for detecting resource scheduling conflicts. The memory system also includes error reporting logic for generating an error signal in response to detecting a resource scheduling conflict at one or more of the memory resources.

Abstract: A method and circuit for reducing SATA (Serial Advanced Technology Attachment) transmission data errors by adjusting the period of sending two consecutive ALIGN Primitives. The method reads a counting value of an 8b/10b coding error counter at a predetermined period and adjusts the period of sending two consecutive ALIGN Primitives according to the counting value. Because the system dynamically adjusts the period of sending two consecutive ALIGN Primitives according to the channel condition, the SATA transmission data errors can be reduced.

Abstract: Embodiments of a system and method for distributed file system I/O recovery in storage networks. Embodiments may detect loss of access to a server in the storage network and recover application I/O requests in real-time once access to the server is restored. Embodiments may detect server and/or network failures and store failed and new I/O requests. Recovery from the failure (e.g. network reconnect, server node reboot, or failover, if this is a clustered environment) may be detected and, after recovery is detected, any stored failed and new I/O requests may be sent to the server. In one embodiment, to detect recovery from the failure, a failed I/O request may be repeatedly re-issued until the I/O request succeeds. Embodiments may be implemented in a variety of storage environments, including environments where clients issue direct I/O over a storage network to storage and control I/O over a network to a server.

Abstract: A self-synchronizing data bus analyzer is provided which can include a generator linear feedback shift register (LFSR) to generate a first data set, and can include a receiver LFSR to generate a second data set. The data bus analyzer may also include a bit sampler to sample the first data set received through a data bus coupled to the generator LFSR and output a sampled first data set. A comparator can be included to compare the sampled first data set with the second data set generated by the receiver LFSR and provide a signal to the receiver LFSR to adjust a phase of the receiver LFSR until the second data set is substantially the same as the first data set.

Abstract: A host apparatus capable of sensing failure in an external device connected thereto through communication cable, comprises an external signal detector for sensing failure in the external device by detecting signals of the external device through the communication cable; a display for outputting a predetermined message; and a controller for displaying a predetermined warning message informing the failure on the display, if the external signal detector senses the failure in the external device. Therefore, a user can be informed of the failure in the external device.

Abstract: A method according to one embodiment may include communicating, by a far end device with a near end device, using a Serial ATA (SATA) communications protocol; receiving, by the far end device, a SATA signal sequence having two bits, the state of which define at least one loopback mode; defining, by the far end device, a reserved and/or error state if both of the bits are set; and processing, by the far end device, the two bits together to determine if the two bits are in a state that defines at least one loopback mode or if the two bits are set. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Abstract: A test system is disclosed wherein a device under test (DUT) includes a trace logic analyzer (TLA) that receives and stores test data. The test system includes both a master tester and a slave tester. The slave tester operates at a high speed data rate substantially faster than that of the master tester. The master tester instructs the TLA to monitor data that the DUT receives from the slave tester to detect a predetermined data pattern within the data. The slave tester transmits data including the predetermined data pattern to the DUT. The DUT receives the data. When the TLA in the DUT detects the predetermined data pattern in the received data, the TLA stores that data pattern as a stored data pattern. The master tester retrieves the stored data pattern and compares the stored data pattern with the original predetermined data pattern. If the master tester determines that the stored data pattern is the same as the original predetermined data pattern, then the master tester generates a pass result.

Abstract: The invention relates to a recovery of a hardware module of an electronic device from a malfunction state. The hardware module is connected via a signal line to a recovery component of the device, a state of the signal line being controlled by the hardware module. The recovery component monitors a state of the signal line. Whenever the signal line is detected not to assume a predetermined state during a predetermined period of time, the recovery component causes a hardware reset of the hardware module.

Abstract: A method includes receiving a first command for accessing a tape storage system, the first command containing an indicator that the first command was issued as a result of a failover from a first path to the storage system to a second path to the tape storage system. The method further includes determining whether the first command is a repeat of a second command already received by the tape storage system. The first command is processed based on determining whether the first command is a repeat of the second command.

Abstract: A DGP, upon detecting the occurrence of a fault in an IOP that controls a CH, causes another IOP that can control the CH to control the CH and reports to an EPU the occurrence of the fault in the CH and the recovery from the fault. The DGP stores information in a CH configuration table indicating that the other IOP is controlling the CH. Upon receiving the reports of the occurrence of the fault in the CH and the recovery, the EPU refers to the CH configuration table, verifies that the other IOP is controlling the CH, and provides data transfer instructions to the other IOP.

Abstract: A method for controlling input and output of a virtualized computing platform is disclosed. The method can include creating a device interface definition, assigning an identifier to a paging device and configuring commands useable by a virtual input output server. The commands can be sent to the input output server and can be converted by the input output server into paging device commands. A hypervisor can assist in facilitating the communication configuration. Other embodiments are also disclosed.

Abstract: According to one embodiment, an electronic apparatus includes a timing detection module which detects a timing of notification to a user in association with execution of an application, a photographing module which captures an image at the timing of notification, which is detected by the timing detection module, a face image detection module which detects a face image of a person from the image which is captured by the photographing module, a direction detection module which detects a direction of the face on the basis of the face image, a setting module which sets a notification method in accordance with the direction of the face, which is detected by the direction detection module, and a notification module which gives a notice according to the notification method which is set by the setting module.

Abstract: Systems, methodologies, media, and other embodiments associated with validating a bus are described. One exemplary system embodiment includes an integrated circuit operably connectable to a bus, the bus being connectable to an external device configured to drive one or more electrical signals onto the bus. The integrated circuit may comprise a first logic configured to receive a test sequence of electrical signals from the bus, a second logic configured to produce a check sequence of electrical signals related to the test sequence of electrical signals, and a compare logic operably connected to the first logic and the second logic. The compare logic may be configured to determine whether the bus is correctly transmitting data based, at least in part, on comparing the test sequence and the check sequence.

Abstract: A central node for a data bus system includes a bus monitor unit with receiver means for registering signals on the data bus, and evaluation means which detect incorrect communication on the data bus and at least temporarily block communication by the user that causes the incorrect communication or compensate the incorrect communication of a user which is triggered by the interference influences. The bus monitor unit includes timing means which are triggered according to time patterns for the transmission of each user of the data bus, in order to detect an incorrect communication of a user if the latter transmits outside the time provided for it. The bus monitor unit is integrated into the central bus node and a plurality of bus branches of different users are combined at the central node so that the bus monitor unit can check a plurality of users for incorrect communication. In order to increase reliability, in addition to the bus monitor unit, a diagnostic unit is integrated into the central node.