Recovery Partition Patents (Class 714/6.12)
  • Publication number: 20140095927
    Abstract: Techniques for achieving high-availability using a single processor (CPU). In a system comprising a multi-core processor, at least two partitions may be configured with each partition being allocated one or more cores of the multiple cores. The partitions may be configured such that one partition operates in active mode while another partition operates in standby mode. In this manner, a single processor is able to provide active-standby functionality, thereby enhancing the availability of the system comprising the processor.
    Type: Application
    Filed: June 24, 2013
    Publication date: April 3, 2014
    Inventors: Vineet M. Abraham, Bill Ying Chin, William R. Mahoney, Aditya Saxena, Xupei Liang, Bill Jianqiang Zhou
  • Patent number: 8683261
    Abstract: Instructions within a processor are managed by receiving, at a recovery unit of the processor, an instruction that modifies a control register residing within the recovery unit. The recovery unit receives a first set of data associated with the instruction from a general register. A second set of data associated with the instruction is retrieved from the control register by the recovery unit. The recovery unit performs at least one binary logic operation on the first set of data and the second data.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: March 25, 2014
    Assignee: International Business Machines Corporation
    Inventors: Michael Cremer, Guenter Gerwig, Frank Lehnert, Peter Probst
  • Publication number: 20140082412
    Abstract: A storage control system includes: storage units each including a first storage area storing information and a second storage area storing management information that contains attribute information of partition information indicating how information is stored in partitions obtained by partitioning the first storage area; an obtaining unit to obtain the management information from the plurality of storage units; a determination unit to determine whether abnormal management information is present in the obtained management information by comparing the obtained management information with itself; and a recovery unit to reconfigure, when it is determined there is the abnormal management information, for each unit of partition, information stored in the first storage area of the storage unit from which the abnormal management information has been obtained by using one of the storage units from which normal management information has been obtained, based on attribute information of the normal management information
    Type: Application
    Filed: September 10, 2013
    Publication date: March 20, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Tadashi MATSUMURA, Noriyuki YASU, Tomohiko MUROYAMA, Motoki SOTANI
  • Patent number: 8677374
    Abstract: In a method for managing resources in a virtualized computing environment, a command to initiate execution of an operating system image dump process for a logical partition of the virtualized computing environment is received while the logical partition is in a process of terminating. One or more resources that are allocated to the logical partition that will not be utilized by the logical partition during execution of the operating system image dump process are determined. A notification to a hypervisor program in the virtualized computing environment is sent. The notification identifies the one or more resources. One of the one or more resources is reallocated. The operating system image dump process is executed.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: March 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Vishal C. Aslot, Brian W. Hart, Anil Kalavakolanu, Evelyn T. Yeung
  • Patent number: 8656214
    Abstract: A dual ported replicated data cache. The cache is configured for storing input data blocks. The cache includes an augmenter for producing an augmented data block with parity information from the input data block, a first memory array for storing the augmented data block, and a second memory array for storing the augmented data block.
    Type: Grant
    Filed: May 24, 2010
    Date of Patent: February 18, 2014
    Inventors: Guillermo Rozas, Alex Klaiber, Robert Masleid
  • Patent number: 8650434
    Abstract: Systems and methods for reading and writing a set of data using a journaling service are provided. The journaling service may be used to identify and record data storage operations associated with one or more shares of data stored in one or more share locations. The journaling service may use logs to record each of the read and write requests to the share locations. In some embodiments, the log may be a queue data structure that stores information associated with failed data storage operations. In some embodiments, the journaling service may leverage both memory and disk storage in order to maintain the journaling queue. In some embodiments, the journaling queue may maintain information associated with the state of each share location. In some embodiments, this information may be used by the journaling service to determine when to monitor and record information regarding data storage operations associated with the share locations.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: February 11, 2014
    Assignee: Security First Corp.
    Inventors: Rick L. Orsini, Mark S. O'Hare
  • Publication number: 20140040661
    Abstract: Some aspects of the disclosure relate to a data storage system that includes multiple memory device storage devices. If a memory device of a memory device array fails within a first data storage device, some portions of the lost or corrupted data from the failed memory device are recovered by reading them from a second data storage device. Other portions of the lost or corrupted data from the failed memory device are recovered from parity information in the first data storage device.
    Type: Application
    Filed: October 14, 2013
    Publication date: February 6, 2014
    Applicant: NetApp Inc.
    Inventor: Atul Goel
  • Patent number: 8645748
    Abstract: A system, method and computer program product for providing “bare metal” computer hardware with full operating system capabilities, including: (a) executing software contained in computer hardware read-only memory; (b) transferring software control to a location of a start-up program; (c) performing initialization of devices of the computer hardware; (d) selecting an origin storage device for restoration of an operating system to a destination storage device of the computer hardware; (e) establishing a connection with an origin for restoration of an operating system to the computer hardware; (f) initiating a transfer of the operating system data from selected origin to the computer hardware; (g) performing optional substitution of the computer hardware drivers; (h) performing optional structural modifications to the restored operating system; and (i) restoring the operating system to the computer hardware from a data storage device located either locally or remotely, from full or incremental operating system
    Type: Grant
    Filed: December 25, 2012
    Date of Patent: February 4, 2014
    Assignee: Acronis International GmbH
    Inventors: Dmitry M. Chepel, Serguei M. Beloussov, Maxim V. Lyadvinsky, Maxim V. Goldobin
  • Patent number: 8639984
    Abstract: A system of debugging computer code includes a processor: obtaining state information corresponding to a first machine at a checkpoint initiated during execution of the computer code on the first machine; and configuring the second machine to a same operating state as the first machine at the checkpoint to create a mirrored version of the first machine. The system also includes receiving a notification that execution of the program on a first machine has failed, and in response to receiving the notification: triggering a processor of the second machine to initiate execution of a copy of the code from a specific code execution point at which the checkpoint was; activating a debugger module to run concurrently with the execution of the program on the second machine and collect and store the debug data as corresponding to execution failure of the computer code at the first machine.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: January 28, 2014
    Assignee: International Business Machines Corporation
    Inventor: Adam J. McNeeney
  • Patent number: 8639973
    Abstract: Some embodiments of the invention provide techniques whereby a user may perform a system reset (e.g., to address system performance and/or reliability degradation, such as which may be caused by unused applications that unnecessarily consume system resources, an attempted un-install of an application that left remnants of the application behind, and/or other causes). In some embodiments, performing a system reset replaces a first instance of an operating system on the system with a new instance of the operating system, and removes any applications installed on the system, without disturbing the user's data.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: January 28, 2014
    Assignee: Microsoft Corporation
    Inventors: Desmond T. Lee, Vinit Ogale, Keshava Prasad Subramanya, Sri Sai Kameswara Pavan Kumar Kasturi, Hongliu Zheng, Yunan Yuan, Gregory W. Nichols, Stephan Doll, Kiran Kumar Dowluru, Calin Negreanu
  • Patent number: 8621267
    Abstract: The embodiments described herein generally relate to methods and systems for using an extended patching procedure for correction or repair of logical data portions, pages, or sectors of a computer data storage device. The extended patching procedure targets for repair not only the page(s) appearing to be defective or unusable based on a failed read operation for a data transfer request, but also additional pages. Determining the additional pages to include for automatic patching is based on: statistical distribution analyzes to include pages within the physical or logical vicinity of the original page, information about the underlying storage device technology or Input/Output (I/O) subsystem, and/or historical data about error conditions for areas related to the original page. Preemptively patching pages based on extended page lists improves system performance by reducing the total number of costly repair processes and by avoiding situations involving correction actions that fail to resolve.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: December 31, 2013
    Assignee: Microsoft Corporation
    Inventors: Alexandre Santana da Costa, Umair Ahmad, Brett A. Shirley, Matthew G. Gossage
  • Patent number: 8601310
    Abstract: In one embodiment, an apparatus includes memory comprising a first portion in which data contained therein is mirrored and a second portion wherein data contained therein is not mirrored, a memory allocator for allocating the first portion of the memory to critical data and allocating the second portion of the memory to non-critical data, and a processor for mirroring the critical data and receiving an indication of a memory error. If the memory error occurs in the first portion of the memory, a mirrored copy of the critical data is used. If the memory error occurs in the second portion of the memory, the memory error is contained so that the apparatus can continue to operate programs using the memory not affected by the memory error.
    Type: Grant
    Filed: August 26, 2010
    Date of Patent: December 3, 2013
    Assignee: Cisco Technology, Inc.
    Inventor: Roland Dreier
  • Patent number: 8572434
    Abstract: Described are computer-based methods and apparatuses, including computer program products, for system health monitoring. Backup set metadata is received, wherein the backup set metadata comprises information about backup data sets that are received by a backup storage system. One or more processes that process the backup set metadata through an emulated processing flow path are executed, wherein the one or more processes are also implemented in the backup storage system. Two or more potential processing states are determined within the emulated processing flow path. A reason code is determined for each backup set metadata entry of the backup set metadata indicative of a reason that the backup set metadata entry is in a processing state of the two or more potential processing states. A problem with the manner in which the backup set metadata is flowing through the emulated processing flow path is identified based on the reason codes.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: October 29, 2013
    Assignee: Sepaton, Inc.
    Inventors: Jane Riegel, John Chernoch
  • Patent number: 8555105
    Abstract: The method determines whether a particular node of a high availability cluster is functioning properly or is a failed node. The method dumps node process state information as a dump data for the failed or crashed node in a shared storage area of the high availability cluster. A high availability cluster manager identifies the dump data that corresponds to the failed node as the most recent dump data for that failed node. The high availability cluster manager interrogates the dump data using kernel debugger services to identify a process trace and thereby identify the crash-causing application for the failed node. The method determines if the dump data includes a process match for the failed node process. The high availability cluster manager may initiate a crash-causing application notification to administrators or other entities of the high availability cluster.
    Type: Grant
    Filed: April 12, 2010
    Date of Patent: October 8, 2013
    Assignee: International Business Machines Corporation
    Inventors: James A. Goodwin, Manjunath B. Muttur
  • Patent number: 8539279
    Abstract: Embodiments of the present invention provide methods, apparatuses, systems, and computer software products for data storage. A corrupted node under a first meta-volume node in a hierarchical tree structure is deleted. The hierarchical tree structure further includes a source node under the first meta-volume node. The corrupted node and the source node each include a respective set of local pointers. The corrupted node and the source node represent respective copies of a logical volume. The source node is reconfigured to become a second meta-volume node having the same set of local pointers as the source node. A first new node is created under the second meta-volume node in the hierarchical tree structure to represent the corrupted node. A second new node is created under the second meta-volume node to represent the source node. The first and second new nodes are configured to have no local pointers.
    Type: Grant
    Filed: January 2, 2013
    Date of Patent: September 17, 2013
    Assignee: International Business Machines Corporation
    Inventors: Haim Helman, Shemer Schwarz, Omri Palmon, Kariel E. Sandler
  • Patent number: 8539280
    Abstract: A storage system is capable of configuring a failover system by use of a first storage processing device to which first storage media are connected and a second storage processing device to which second storage media are connected. The storage system sets the RAID level of the second storage media to a RAID level with lower redundancy than the RAID level of the first storage media, if the storage capacity of the second storage media is smaller than the storage capacity of the first storage media.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: September 17, 2013
    Assignee: Buffalo Inc.
    Inventors: Satoru Goto, Yukihito Hara
  • Patent number: 8499025
    Abstract: Parallel Processing Communication Accelerator (PPCA) systems and methods for enhancing performance of a Parallel Processing Environment (PPE). In an embodiment, a Message Passing Interface (MPI) devolver enabled PPCA is in communication with the PPE and a host node. The host node executes at least a parallel processing application and an MPI process. The MPI devolver communicates with the MPI process and the PPE to improve the performance of the PPE by offloading MPI process functionality to the PPCA. Offloading MPI processing to the PPCA frees the host node for other processing tasks, for example, executing the parallel processing application, thereby improving the performance of the PPE.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: July 30, 2013
    Assignee: Massively Parallel Technologies, Inc.
    Inventor: Kevin D. Howard
  • Patent number: 8499192
    Abstract: A method for writing and reading data in memory cells, comprising, when writing a data in a block of a first memory zone, a step consisting of writing in a second memory zone a temporary information structure metadata comprising a start flag, an identifier of the temporary information structure, an information about the location of the block in the first memory zone, and a final flag, and, after a power on of the first memory zone, searching for an anomaly in temporary information structures present in the second memory zone.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: July 30, 2013
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Hubert Rousseau
  • Patent number: 8495295
    Abstract: There are provided a mass storage system and a method of operating thereof. The method comprises: a) dividing the storage space into a first portion configured to be available to a client and a second portion configured to be unavailable to a client, thus giving rise, respectively to an available storage space and a spare storage space; b) distributing the available space and the spare space over the disk drives thus giving rise to available space and spare space allocated to each given disk drive; c) detecting underperformance of at least one disk drive among the plurality of disk drives; d) responsive to detecting underperformance, decreasing respective available space allocated to said at least one underperforming disk drive and respectively increasing spare space allocated to said at least one underperforming disk drive thus giving rise to a re-configured allocation of the available space; and e) transferring the stored data in accordance with said re-configured allocation of the available space.
    Type: Grant
    Filed: May 10, 2010
    Date of Patent: July 23, 2013
    Assignee: Infinidat Ltd.
    Inventor: Haim Kopylovitz
  • Patent number: 8489915
    Abstract: A storage integrity system in a dispersed storage network scans an address range of data slices to identify errors in one of a plurality of encoded data slices, wherein the plurality of encoded data slices are generated from a data segment using an error encoding dispersal function. When the storage integrity system detects an error, it identifies one of the encoded data slices for rebuilding. The identified data slice is rebuilt in response to the type of error. For example, when the type of the error includes a temporary error, the storage integrity system waits a predetermined time period to determine whether the error still exists prior to rebuilding the identified data slice.
    Type: Grant
    Filed: April 26, 2010
    Date of Patent: July 16, 2013
    Assignee: Cleversafe, Inc.
    Inventors: Greg Dhuse, Andrew Baptist, Zachary J. Mark, Jason K. Resch, Ilya Volvovski
  • Patent number: 8479039
    Abstract: The present invention provides a method of protecting against errors in a boot memory, the method comprising initiating booting of a processor by executing primary boot code from a primary boot memory, and based on the execution of the primary boot code: accessing a data structure comprising a plurality of redundant portions of boot information stored on a secondary boot memory; performing an error check on a plurality of the portions to determine whether those portions contain errors and, based on the error checks, to identify a valid portion; and booting the processor using the valid portion of boot information.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: July 2, 2013
    Assignee: Icera Inc.
    Inventors: David Alan Edwards, Joe Woodward
  • Patent number: 8473777
    Abstract: Method and system for performing recovery for a replicated copy of a storage space presented as a logical object is provided. An attribute associated with the logical object for enabling the recovery is set and when the storage space is replicated the attribute is stored as metadata for the replicated copy of the storage space. Based on the attribute, a clone of the logical object is presented as a writable option to write to the first replicated copy. After the write operation where information is written to the clone, a second replicated copy with the clone information is created. The clone is deleted after the second copy is generated.
    Type: Grant
    Filed: April 29, 2010
    Date of Patent: June 25, 2013
    Assignee: Netapp, Inc.
    Inventors: Muralidharan Rangachari, Anagha Barve, Vineeth Karinta
  • Patent number: 8468384
    Abstract: For writing, flash memory devices are physically accessed in a page-oriented mode, but such devices are not error-free in operation. According to the invention, when writing information data in a bus write cycle in a sequential manner into flash memory devices assigned to a common data bus, at least one of said flash memory devices is not fed for storage with a current section of said information data. In case an error is occurring while writing a current information data section into a page of a current one of said flash memory devices, said current information data section is written into a non-flash memory. During the following bus write cycle, while the flash memory device containing that defective page is normally idle, that idle time period is used for copying the corresponding stored section of said information data from said non-flash memory to a non-defect page of that flash memory device.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: June 18, 2013
    Assignee: Thomson Licensing
    Inventors: Thomas Brune, Michael Drexler, Dieter Haupt
  • Publication number: 20130124917
    Abstract: A method and system for recovering from stack-overflow or stack-underflow faults without restarting software or hardware. At every task switch operation in an application program, a portion of the memory stack is copied to a backup location, so that portion of the stack can be restored if it is subsequently corrupted by a stack-overflow or stack-underflow fault during the execution of the next task. State variable data is similarly copied to a backup location, so that it can be used to restore or estimate the output of the next task if that task experiences a fault. Techniques are disclosed for selecting which state variable data and which portion of the memory stack to copy to backup, and for detecting a stack-overflow or stack-underflow fault and restoring state variable and memory data in the event of such a fault.
    Type: Application
    Filed: November 16, 2011
    Publication date: May 16, 2013
    Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventor: Dipankar Das
  • Publication number: 20130111263
    Abstract: A method is disclosed for recovering data associated with a damaged file stored in a NAND gate array memory. The method includes the steps of: identifying all meta data associated with the damaged file; identifying each logical block address of all identified meta data; collecting all physical block addresses associated with one of the identified logical block addresses or the identified meta data; counting in a replace table (ReplTable) a number of matches to a physical block address of the damaged file for each physical block address of the damaged file; choosing a block in a linked list that corresponds to the physical block address of the block in the linked list; and linking all chosen blocks to form a replicated file.
    Type: Application
    Filed: November 26, 2012
    Publication date: May 2, 2013
    Applicant: The Board of Governors for Higher Education, State of Rhode Island and Providence Plantations
    Inventor: The Board of Governors for Higher Education, State of Rhode Island and Providence Plantations
  • Patent number: 8407515
    Abstract: A method and apparatus for transparently handling recurring correctable errors and uncorrectable errors in a mirrored memory system prevents costly system shutdowns for correctable memory errors or system failures from uncorrectable memory errors. When a high number of correctable errors are detected for a given memory location, a memory relocation mechanism in the hypervisor moves the data associated with the memory location to an alternate physical memory location transparently to the partition such that the partition has no knowledge that the physical memory actualizing the memory location has been changed. When a correctable error occurs, the memory relocation mechanism uses data from a partner mirrored memory block as a data source for the memory block with the uncorrectable error and then relocates the data to a newly allocated memory block to replace the memory block with the uncorrectable error.
    Type: Grant
    Filed: May 6, 2008
    Date of Patent: March 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Peter Joseph Heyrman, Naresh Nayar, Gary Ross Ricard
  • Patent number: 8402346
    Abstract: An n-way parity protection technique enables recovery of up to n storage device (e.g., disk) failures in a parity group of a storage array encoded to protect against n-way disk failures. The storage array is created by first configuring the array with m data disks, where m=p?1 and p is a prime number and a row parity disk. n?1 diagonal parity disks are then added to the array. Each diagonal parity set (i.e., diagonal) is associated with a slope that defines the data and row parity blocks of the array that are included in the diagonal. All diagonals having a common slope within a parity group are organized as a diagonal parity class. For each diagonal parity class, a diagonal parity storage disk is provided to store the diagonal parity.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: March 19, 2013
    Assignee: NetApp, Inc.
    Inventors: Atul Goel, Peter F. Corbett
  • Publication number: 20130067273
    Abstract: A mechanism is provided for optimizing and enhancing performance for parity based storage, particularly redundant array of independent disk (RAID) storage. The mechanism optimizes a repetitive pattern write command for performance for storage configurations that require parity calculations. The mechanism eliminates the need for laborious parity calculations that are resource intensive and add to IO latency. For repetitive write commands that span across the full stripe of a RAID5 or similar volume, the mechanism calculates parity by looking at the pattern and the number of columns in the volume. The mechanism may avoid the XOR operation altogether for repetitive pattern write commands. The mechanism may enhance secure delete operations that use repetitive pattern write commands by eliminating data reliability operations like parity generation and writing altogether.
    Type: Application
    Filed: September 12, 2011
    Publication date: March 14, 2013
    Applicant: International Business Machines Corporation
    Inventors: Rahul M. Fiske, Kalyan C. Gunda, Carl E. Jones, Sandeep R. Patil, Subhojit Roy
  • Patent number: 8381023
    Abstract: A memory system according to the present invention includes, in addition to an computing device, a plurality of first blocks that are provided to store information including user information, and first physical addresses not overlapping one another are assigned to, respectively, and a plurality of second blocks that are provided to store first physical addresses of initial defect blocks out of the plurality of first blocks, respectively, wherein the computing device finds the first physical address corresponding a inputted given logical address, based on a given mirror logical address corresponding to the given logical address, and information stored in the second blocks.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: February 19, 2013
    Assignee: MegaChips Corporation
    Inventor: Shinji Tanaka
  • Patent number: 8381021
    Abstract: In one embodiment, an intelligent communications device for operating in a network is disclosed. The device includes a storage device having a plurality of partitions storing images for performing boot operations. The device also includes a detection module that is operative to detect a boot failure, and a first restoration module that is operative to restore an active image with a first backup image, in response to a detected boot failure from an active image. The device further includes a second restoration module that is operative to restore a second backup image in response to a detected boot failure after restoration from a first backup image. The device also includes a programmable processor that is programmed to cause execution of boot operations and functions performed by the detection module, first restoration module, and second restoration module.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: February 19, 2013
    Assignee: Itron, Inc.
    Inventors: Edward Glenn Howard, Thomas Hunter Cobbs
  • Patent number: 8381022
    Abstract: Embodiments of the present invention provide methods, apparatuses, systems, and computer software products for data storage. A first copy of a logical volume is created. A second copy of the logical volume is created based on the first copy of the logical volume, such that the first and second copies are represented by respective first and second sets of pointers to physical storage locations in which data used by the copies is stored. Responsively to a corruption of at least part of the data that is used by the first copy. The first copy is restored from the second copy by replacing the first set with the pointers in the second set.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: February 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Haim Helman, Shemer Schwarz, Omri Palmon, Kariel E. Sandler
  • Patent number: 8370680
    Abstract: A solid state storage system includes a flash memory region comprising a plurality of memory blocks and a plurality of replacement blocks corresponding to error-occurred blocks when errors occur in the memory blocks; and a memory controller configured to perform a control operation to replace the error-occurred blocks with the replacement blocks, wherein the error-occurred blocks comprise correctable blocks and uncorrectable blocks, and wherein the memory controller determines whether the error-occurred blocks are the correctable blocks or the uncorrectable blocks and controls zones of the replacement blocks, replaced in correspondence to the correctable blocks, to be allocated a plurality of times.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: February 5, 2013
    Assignee: SK Hynix Inc.
    Inventors: Myung Suk Lee, Jeong Soon Kwak, Kyeong Rho Kim, Yang Gi Moon
  • Patent number: 8352807
    Abstract: A host device 200A includes a data buffer 250. When data has been already written to a part of a physical block and data is additionally written to the physical block, it is determined whether or not the data written to the physical block is held in the data buffer. When the data is held, data is written to the block, and when an error exists, data in unit of physical blocks is rewritten. When the data is not held in the data buffer, a new physical block is required to be secured and then, data is written to the new block. Thereby, even when power is shut off or an error occurs during writing in the semiconductor memory device, destruction of data already written is prevented.
    Type: Grant
    Filed: January 6, 2010
    Date of Patent: January 8, 2013
    Assignee: Panasonic Corporation
    Inventors: Hideaki Yamashita, Takeshi Ootsuka
  • Patent number: 8352780
    Abstract: For writing, flash memory devices are physically accessed in a page-oriented mode, but such devices are not error-free in operation. According to the invention, when writing information data in a bus write cycle in a sequential manner into flash memory devices assigned to a common data bus, at least one of said flash memory devices is not fed for storage with a current section of said information data. In case an error is occurring while writing a current information data section into a page of a current one of said flash memory devices, said current information data section is written into a non-flash memory. During the following bus write cycle, while the flash memory device containing that defective page is normally idle, that idle time period is used for copying the corresponding stored section of said information data from said non-flash memory to a non-defect page of that flash memory device.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: January 8, 2013
    Assignee: Thomson Licensing
    Inventors: Thomas Brune, Michael Drexler, Dieter Haupt
  • Patent number: 8347137
    Abstract: A system, method and computer program product for providing “bare metal” computer hardware with full operating system capabilities, including: (a) executing software contained in computer hardware read-only memory; (b) transferring software control to a location of a start-up program; (c) performing initialization of devices of the computer hardware; (d) selecting an origin storage device for restoration of an operating system to a destination storage device of the computer hardware; (e) establishing a connection with an origin for restoration of an operating system to the computer hardware; (f) initiating a transfer of the operating system data from selected origin to the computer hardware; (g) performing optional substitution of the computer hardware drivers; (h) performing optional structural modifications to the restored operating system; and (i) restoring the operating system to the computer hardware from a data storage device located either locally or remotely, from full or incremental operating system
    Type: Grant
    Filed: September 23, 2009
    Date of Patent: January 1, 2013
    Assignee: Acronis International GmbH
    Inventors: Dmitry M. Chepel, Serguei M. Beloussov, Maxim V. Lyadvinsky, Maxim V. Goldobin
  • Patent number: 8341456
    Abstract: An apparatus of recording data on a recording medium includes an optical recording device and a microcomputer. The recording medium has a lead-in area, a lead-out area, and a data zone, where the data zone has a user data area and a spare area. When the microcomputer receives a command for physically overwriting first data in a first area within the user data area and determines that the first area is included in a pre-recorded area, it controls the recording device to record the first data in a first replacement area instead and to record a first entry in a TDMA, where the first entry specifies the locations of the first area and the first replacement area.
    Type: Grant
    Filed: August 15, 2005
    Date of Patent: December 25, 2012
    Assignee: LG Electronics, Inc.
    Inventor: Yong Cheol Park
  • Patent number: 8327183
    Abstract: A switch connected to a network system including a computer and a storage apparatus: controlling read/write request from the computer to the storage apparatus and controlling to store journal data in the storage apparatus; wherein the storage apparatus includes a first storage area for storing data to be used by the computer and a second storage area for storing journal data including write data and first update log information corresponding to the write data when there is a write request from the computer for writing data in the first storage area; wherein when the switch detects an event of status change related to the network system, the switch marks a first point of time corresponding to the event as a recovery request point, and creates second update log information corresponding to the recovery request point.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: December 4, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Akira Deguchi, Yoshiaki Eguchi, Kenta Ninose
  • Patent number: 8261133
    Abstract: The present invention is a method, computer-readable medium and an apparatus for protection and recovery of non-redundant computer-readable information stored in a memory having multiple segments that features replacing computer-readable information stored in one of the multiple segments based upon a determination that computer-readable information stored in one of the remaining segments of the multiples segments is in a desired state. To that end, the memory device operates synergistically with a shelf manager, which maintains a state of computer-readable information in the differing address ranges of the memory device, so that any computer-readable information replaced in memory device may be achieved by executing uncorrupted computer-readable information stored in the memory device.
    Type: Grant
    Filed: August 4, 2006
    Date of Patent: September 4, 2012
    Assignee: Oracle America, Inc.
    Inventors: Gunawan Ali-Santosa, Rajeev Bharol
  • Patent number: 8245078
    Abstract: A user interface is provided through which a user may specify a container for data recovery. In response to the specification of a container for recovery, another user interface is provided through which the user can select a consistency group or a journal file to be utilized for recovery. In response to receiving a selection of a journal file for data recovery, a user interface is provided through which a user may specify a point in time, an event, or a snapshot at which time recovery for the corresponding volume should occur. In response to receiving a selection of a consistency group for recovery, a user interface is provided through which a user may specify a snapshot performed across two or more volumes of the consistency group that should be utilized for recovery.
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: August 14, 2012
    Assignee: American Megatrends, Inc.
    Inventors: Paresh Chatterjee, Narayanan Balakrishnan, Anandh Mahalingam, Balasubramaniam Veeranna
  • Publication number: 20120159240
    Abstract: Described is the backup and/or restore of virtual disks In general, metadata is backed up for restoring a virtual disk. To restore the disk, a physical disk is created, with the virtual disk the created on a partition of the physical disk. Backup and restore is described for nested virtual disks, including for block level restore. Further described is backing up of critical virtual disks and their containers, and virtual disk backup with respect to basic disks and dynamic volumes.
    Type: Application
    Filed: February 27, 2012
    Publication date: June 21, 2012
    Applicant: MICROSOFT CORPORATION
    Inventors: Abhinav Srivastava, Ran Kalach, Jingbo Wu, Dinesh Haridas
  • Patent number: 8200933
    Abstract: Assuring recovery from failure of a storage server in a distributed column chunk data store of operably coupled storage servers, includes: partitioning a data table into chunks; implementing a distribution scheme with a specified level of redundancy for recovery of one or more failed servers among multiple storage servers; distributing the column chunks according to the distribution scheme; calculating column chunk parity; storing the calculated column chunk parity; managing metadata for the column chunk data store; and updating the metadata for distributing the column chunks among remaining storage servers upon receiving an indication to remove a storage serve.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: June 12, 2012
    Assignee: Yahoo! Inc.
    Inventor: Radha Krishna Uppala
  • Publication number: 20120137167
    Abstract: A system and method for mitigating memory errors in a computer system. Faulty memory is identified and tested by a memory manager of an operating system. The memory manager may perform diagnostic tests while the operating system is executing on the computer system. Regions of memory that are being used by software components of the computer system may also be tested. The memory manager maintains a stored information about faulty memory regions. Regions are added to the stored information when they are determined to be faulty by a diagnostic test tool. Memory regions are allocated to software components by the memory manager after checking the stored information about faulty memory regions. This ensures a faulty memory region is never allocated to a software component of the computer system.
    Type: Application
    Filed: November 30, 2010
    Publication date: May 31, 2012
    Applicant: Microsoft Corporation
    Inventors: Garrett Leischner, Andrew J. Lagattuta, Matthew Jeremiah Eason, Landy Wang, John R. Douceur, Baskar Sridharan, Edmund B. Nightingale
  • Publication number: 20120110376
    Abstract: Various embodiments of the present invention provide systems and methods for managing solid state drives. As an example, a storage system is described that include at least a first flash memory block and a second flash memory block, and a control circuit. The first flash memory block and the second flash memory block are addressable in the storage system. The control circuit is operable to identify the first flash memory block as partially failed, receive a write request directed to the first flash memory block; and direct the write request to the second flash memory block.
    Type: Application
    Filed: January 11, 2012
    Publication date: May 3, 2012
    Inventors: David L. Dreifus, Robert W. Warren, Brian McKean
  • Patent number: 8156393
    Abstract: To provide a memory system which determines a memory state such as an exhaustion level and allows a memory to be efficiently used. The memory system includes a NAND type flash memory 1 in which data can be electrically written/erased, a nonvolatile memory 2 which counts the number of erase operations of the NAND type flash memory 1 and retains the number of erase operations and a maximum number of erase operations, and a controller 3 which has a connection interface 31 to be given a self-diagnosis command from a computer 4, and retrieves the number of erase operations and the maximum number of erase operations from the nonvolatile memory 2 based on the self-diagnosis command and outputs the number of erase operations and the maximum number of erase operations to the computer 4 through the connection interface 31.
    Type: Grant
    Filed: November 28, 2007
    Date of Patent: April 10, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasushi Nagadomi, Daisaburo Takashima, Kosuke Hatsuda, Shinichi Kanno
  • Patent number: 8151136
    Abstract: A method and a device for correcting a code data error are disclosed. A main processor included in a digital processing device in accordance with an embodiment of the present invention writes in a shared memory third code data error-corrected by a predetermined error correcting method or second code data written in a backup area if there is an error in first code data written in a code data area of a nonvolatile memory. The main processor or an application processor performs an operation corresponding to the third code data. With the present invention, a system can be stably operated thanks to promptly dealing with an error when the error in boot codes is detected or generated.
    Type: Grant
    Filed: September 11, 2006
    Date of Patent: April 3, 2012
    Assignee: MTekvision Co., Ltd.
    Inventor: Jong-Sik Jeong
  • Patent number: 8145985
    Abstract: In a data processing system processing circuitry executes a plurality of data processing instructions. A unified cache memory stores data and instructions processed by the processing circuitry. The unified cache memory has a plurality of sets, each set having a plurality of ways, each with one or more information fields. Cache memory control circuitry has a control register for controlling allocation of each way of the plurality of ways for one of: (1) a first type of information; (2) a second type of information; or (3) both the first type of information and the second type of information. The cache memory control circuitry further individually controls a selection of a type of error detection among a plurality of types of error detection for each way of the unified cache memory based upon the allocation control indicated by the control register.
    Type: Grant
    Filed: September 5, 2008
    Date of Patent: March 27, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventor: William C. Moyer
  • Publication number: 20120054540
    Abstract: In one embodiment, an intelligent communications device for operating in a network is disclosed. The device includes a storage device having a plurality of partitions storing images for performing boot operations. The device also includes a detection module that is operative to detect a boot failure, and a first restoration module that is operative to restore an active image with a first backup image, in response to a detected boot failure from an active image. The device further includes a second restoration module that is operative to restore a second backup image in response to a detected boot failure after restoration from a first backup image. The device also includes a programmable processor that is programmed to cause execution of boot operations and functions performed by the detection module, first restoration module, and second restoration module.
    Type: Application
    Filed: October 6, 2010
    Publication date: March 1, 2012
    Applicant: SmartSynch, Inc.
    Inventors: Edward G. Howard, Thomas H. Cobbs
  • Patent number: 8127099
    Abstract: Disclosed are a method, information processing system, and computer readable medium for resource recovery. The method comprises associating at least one bit with at least one block of memory. The bit denotes a borrow status for the block of memory. The bit is set for resource recovery. A resource recovery event is detected and in response to the bit being enabled for resource recovery, the block of memory is borrowed for a given duration of time. The block is borrowed to temporarily store information associated with the resource recovery there into until the information is written to persistent storage.
    Type: Grant
    Filed: December 26, 2006
    Date of Patent: February 28, 2012
    Assignee: International Business Machines Corporation
    Inventors: Tara Astigarraga, Michael E. Browne, Joseph Demczar, Eric C. Wieder
  • Publication number: 20120047396
    Abstract: An embodiment of a data-read path includes a defect detector and a data-recovery circuit. The defect detector is operable to identify a defective region of a data-storage medium, and the data-recovery circuit is operable to recover data from the data-storage medium in response to the defect detector. For example, such an embodiment may allow identifying a defective region of a data-storage disk caused, e.g., by a scratch or contamination, and may allow recovering data that was written to the defective region.
    Type: Application
    Filed: August 20, 2010
    Publication date: February 23, 2012
    Applicant: STMicroelectronics, Inc.
    Inventors: Shayan Srinivasa GARANI, Sivagnanam PARTHASARATHY
  • Patent number: 8122284
    Abstract: Reciprocal data storage protection is combined with “N+1” hardware provisioning and on-demand resynchronization to guarantee full data availability without impairing performance. Pairs of nodes are identified that act as backups for each other, where each node stores a secondary copy of data allocated to its reciprocal, paired node. A single extra node is brought online to take over the role of a failed node and assumes the role of the primary node it replaced.
    Type: Grant
    Filed: June 17, 2010
    Date of Patent: February 21, 2012
    Inventors: Tracy M. Taylor, Craig Leckband, Yongmin Chen