Abstract: A computer-implemented method for enabling debugging can include receiving, at a peripheral device connected through an expansion socket to a base CPU platform, a scan dump instruction from a network computing device connected to the base CPU platform across a network connection and executing, by a System-on-Chip at the peripheral device in response to the scan dump instruction, a debugging procedure. The debugging procedure can include capturing a snapshot of memory of the peripheral device and transmitting the snapshot to the network computing device through memory addresses that have been assigned to memory-mapped input/output. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: Systems and methods that make use of cluster-level redundancy within a distributed storage management system to address various node-level error scenarios are provided. According to one embodiment, a first node of multiple nodes of distributed storage system represented in a form of a cluster of the multiple of nodes, identifies the potential existence of an error associated with a Redundant Array of Independent Disks (RAID) stripe. A list of block identifiers (IDs) associated with the RAID stripe may then be identified. Rather than performing a traditional RAID recovery/reconstruction approach that is resource intensive in nature and that requires an excessive amount of rebuild time, a more efficient RAID stripe resynchronization process may be performed to restore data associated with the RAID stripe.

Abstract: Systems, methods and apparatuses to log memory errors in memory devices that can perform wear leveling based on physical addresses used in the memory devices to address select memory cells. For example, a controller of a memory sub-system communicates with a memory device installed in the memory sub-system to access memory cells in the memory device. During the communication to access memory cells in the memory device, the controller can determine a memory error at a first address. If the controller transmits the first address to the memory device for memory access at the time of the memory error, the memory device converts the first address to a second address to perform the memory access. The controller can be configured to determine the second address and record, in an error log, the memory error in association with the second address.

Abstract: A memory system includes a non-volatile memory and a memory controller. The memory controller includes a counter, the memory controller being configured to control a write operation to the non-volatile memory and a read operation from the non-volatile memory and configured to obtain wear information of the non-volatile memory. The memory controller is configured to update the counter based on the wear information, generate a trigger with a predetermined probability, and execute a persistence process configured to store information of the counter in a non-volatile manner based on the trigger.

Abstract: A modular Error Correction Code (ECC) scheme in a multi-channel IO link of an integrated circuit device is provided. The integrated circuit device may include core logic circuitry that may be configured after manufacturing. To accommodate the resulting variation, the modular ECC scheme may allow for partitioning a parity check matrix associated with the configuration of the core logic and peripheries coupled to the core logic. The parity check matrix is partitioned into smaller block matrices that is programmable. Multiple ECC modules corresponding to the block matrices are used to provide error detection and correction in the multi-channel IO link. The modular ECC scheme combined with programmable matrices (configurability) enables multi-channel IO link to be flexible to form different IO topologies.

Abstract: Disclosed is a method for accessing memory cells arranged in rows and columns. The method includes activating a specific row of the rows of the memory cells, and flipping data bits stored in memory cells of the specific row in response to determining that concentrated activation occurs at the specific row.

Abstract: A system includes a processor and a memory set coupled to the processor. The system also includes a repair circuit coupled to the memory set. The repair circuit includes a first repair circuit and a second repair circuit. The repair circuit also includes a test controller configured to select between the first repair circuit and the second repair circuit to perform an in-field self-repair of the memory set.

Abstract: Disclosed in some examples are methods, systems, devices, memory devices, and machine-readable mediums for using a non-defective portion of a block of memory on which there is a defect on a different portion. Rather than disable the entire block, the system may disable only a portion of the block (e.g., a first deck of the block) and salvage a different portion of the block (e.g., a second deck of the block).

Abstract: Methods, systems, and devices for temperature exception tracking in a temperature log for a memory system are described. The memory system may store the temperature log separate from data to which the temperature information corresponds. For example, a memory device may store data in a relatively higher-level cell and the corresponding temperature information in a relatively lower-level cell. To perform a write operation, the memory system may determine a current temperature at which the data is being written or was written to a partition of a memory device and may indicate in the temperature log if the current temperature is entering a temperature range that is outside a threshold temperature (e.g., a nominal temperature). To perform a read operation, the memory system may determine if the data to read was written to the memory device outside the threshold temperature to determine whether to perform temperature compensation for the read operation.

Abstract: A file system in a user space partition of virtual memory may be mounted by a computing device that runs a virtual machine which includes a set of storage disks. The file system in user space may then expose one or more virtual files associated with one or more storage disks that correspond to one or more loop devices configured to map files of the virtual machine to the one or more virtual files. The computing device may then receive a request to read a data block stored at the virtual machine and may identify a file and corresponding virtual file that stores the requested data block based on a set of metadata provided by the loop devices. The computing device may then determine the location of the data block stored at the virtual machine, and may read the data block from the determined location.

Abstract: Methods, systems, and devices for managing address access information are described. A device may receive a command for an address of a memory array. Based on or in response to the command, the device may read a first set of tag bits from the memory array. The first set of tag bits may indicate access information for a set of addresses that includes the address. The device may determine a second set of tag bits based on the command and the address. The second set of tag bits may indicate updated access information for the address. The device may generate a codeword based on the first set of tag bits and the second set of tag bits and may store the codeword in the memory array.

Abstract: A processing device detects a read operation at a memory device that is directed at a word line group from among multiple word line groups of the memory device. The processing device increments a read counter associated with the word line group based on the read operation being directed at the word line group. The processing device determines the read counter exceeds a read-disturb threshold and performs read-disturb handling on the word line group in response to determining the read counter exceeds the read-disturb threshold.

Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.

Abstract: Methods, systems, and devices for techniques for temperature-based access operations are described. A memory system may be configured to write temperature information to metadata during a write operation. The temperature information may indicate a temperature range within which the memory system may be during the write operation. The memory system may perform a corresponding read operation based on the temperature information written to the metadata and a temperature of the memory system during the read operation. A server may determine and indicate parameters associated with writing the temperature information to the metadata. Additionally, or alternatively, the server may indicate trim parameters for use in performing read operations based on temperature information received from the memory system. In some examples, the memory system may perform targeted refresh operations at locations based on temperature information stored associated with the locations.

Abstract: A method of operating a microelectronic package includes a processing device stacking vertically with at least one memory device. The method includes a step of: reading data stored in a plurality of memory cells of a plurality of memory units of the memory device, with the processing device, with a plurality of signal channels each of which is dedicated to transmit signals from the processing device to one of the memory units and vice versa.

Abstract: A mobile phone having a flash memory reset function, which solves a malfunction of the mobile phone due to an abnormal state of a flash memory, and a flash memory control apparatus thereof. The flash memory control apparatus includes an application processor configured to provide the hold signal and the chip select signal for resetting when it is determined, on the basis of error information due to a read error of an integrated circuit operating by reading flash data, that an abnormal case due to a read error for the flash data has occurred more than a predetermined number of times; and a flash memory configured to reset the flash data when the hold signal and the chip select signal for resetting are received.

Abstract: An electronic device for displaying a target advertisement which displays a content screen on a display based on content data received from an external server, transmits information about the electronic device to the external server for a target advertisement, and receives first target advertisement information determined based on the information about the electronic device from the external server and displays a target advertisement by using the received first target advertisement information.

Abstract: A testing method for a packaged chip includes: acquiring a target chip; in the post-burn-in test process, testing a first data retention time of each memory unit on the target chip; comparing the first data retention time of each memory unit with a preset reference time; and, determining that the target chip is a qualified chip if the first data retention time of each memory unit is not less than the preset reference time. In the present application, by testing the first data retention time of each memory unit on the target chip in the post-burn-in test process, it is determined that the target chip is a qualified chip if the first data retention time of each memory unit is not less than the preset reference time.

Abstract: A data storage device and method for preventing data loss during an ungraceful shutdown are provided. In one embodiment, a data storage device is provided comprising a volatile memory; a non-volatile memory; and a controller. The controller is configured to detect an ungraceful shutdown; and in response to detecting the ungraceful shutdown: generate a reduced set of parity bits for data stored in the volatile memory, wherein the reduced set of parity bits comprises fewer parity bits than a full set of parity bits used in a graceful shutdown; and store the data and the reduced set of parity bits in the non-volatile memory. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: An information handling system may include a plurality of information handling resources comprising firmware elements; at least one processor; and a computer-readable medium having instructions thereon that are executable by the at least one processor for: storing metadata associated with data that is stored in the plurality of firmware elements of the information handling system; and implementing a single filesystem configured to allow unified access to the data via the metadata.

Abstract: A memory management method is provided according to the invention. The method includes: reading a physical unit and updating a read count of the physical unit; scanning the physical unit if the updated read count is not less than a read count threshold; and adjusting the read count threshold according to the read count and a read error bit. Therefore, a data unit that needs to be scanned can be determined to reduce unnecessary data scanning.

Abstract: The present technology relates to an electronic device. The storage device according to the present technology may include a memory device and a memory controller. The memory device may include a plurality of memory blocks. The memory controller may control the memory device to perform a recovery operation for a first sudden power off on a target block on which a program operation is stopped due to the first sudden power off among the plurality of memory blocks, and perform a program operation of storing lock data including information indicating completion of the recovery operation for the first sudden power off in a page next to a page on which the recovery operation is completed in the target block.

Abstract: A processing device detects a read operation at a memory device that is directed at a word line group from among multiple word line groups of the memory device. The processing device increments a read counter associated with the word line group based on the read operation being directed at the word line group. The processing device determines the read counter exceeds a read-disturb threshold and performs read-disturb handling on the word line group in response to determining the read counter exceeds the read-disturb threshold.

Abstract: An illustrative method includes a data protection system detecting a request provided by a source to perform an operation with respect to a storage system, the request including a logical address that comprises a logical element representative of a storage location within the storage system, determining whether the logical address further comprises an authorization element indicating that the source is authorized to initiate operations with respect to the storage system, and performing, based on the determining whether the logical address includes the authorization element, an action with respect to the operation.

Abstract: Creation of trivial snapshot instances is presented herein. A method comprises determining that a trivial snapshot instance representing a sub-grouping of storage devices included in an enterprise storage array device has not been accessed within a defined duration of time value; marking the trivial snapshot instance for deletion from the enterprise storage array device based on an expiration of the defined duration of time value; and deleting the trivial snapshot instance from the enterprise storage array device.

Abstract: A processing device in a memory system maintains a counter to track a number of read operations performed on a data block of a memory device and determines that the number of read operations performed on the data block satisfies a first threshold criterion. The processing device further determines whether a number of scan operations performed on the data block satisfies a scan threshold criterion. Responsive to the number of scan operations performed on the data block satisfying the scan threshold criterion, the processing device performs a first data integrity scan to determine one or more first error rates for the data block, each of the one or more first error rates corresponding to a first set of wordlines of the data block, the first set comprising first alternating pairs of adjacent wordlines.

Abstract: Recording an indicator of time at which a super block is erased, recording an indicator of time at which a first page of the super block is programmed, and recording an indicator of time at which a last page of the super block is programmed.

Abstract: A variety of applications can include systems and/or methods of optimizing results from scanning a memory device, where the memory device has stacked multiple reliability specifications. Information about a block of multiple blocks of a memory device can be logged, where the information is associated with a combination of reliability specifications. A refresh of the block can be triggered based on exceeding a threshold condition for the combination of reliability specifications.

Abstract: A system includes a plurality of memory devices and a processing device (e.g., a controller), operatively coupled to the plurality of memory devices. The processing device is to detect a power-on of the system and determine a read-retry trigger rate (TR) of a subset of codewords of the plurality of memory devices during a time interval after an initialization of the memory component. The processing device is further to determine whether the TR satisfies a threshold criterion. In response to the TR not satisfying the threshold criterion, the processing device is to initialize a full-memory refresh of the plurality of memory devices.

Abstract: A semiconductor memory device including a memory cell array and an error relief circuit may be provided. The memory cell array includes plurality of memory cells which store data and are coupled to a plurality of word-lines and a plurality of bit-lines. The error relief circuit includes a replacement memory. The error relief circuit receives a command and an address from an external device, stores a first data associated with a first address in the replacement memory in response to detecting a sequence of the consecutively received commands with respect to the first address, and inputs/outputs the first data associated with the first address through the replacement memory.

Abstract: The present technology relates to an electronic device. According to the present technology, a storage device having improved original data recovery capability may include a memory device including a plurality of memory cells, and configured to perform a read operation on data stored in the plurality of memory cells according to read mode information, and to output read data associated with the read operation and a memory controller configured to receive the read data, change the read mode information when error correction decoding for the read data fails, and control the memory device to perform the read operation again according to the changed read mode information. The read mode information may include information on a data interface between the memory device and the memory controller.

Abstract: The memory error determination device includes a processor configured to: detect a memory element in which an error has occurred in each of a plurality of layers included in a memory being three-dimensionally stacked, specify a position of each memory element in which the error has occurred in each of the plurality of layers, and determine that, when the position of each memory element in which the error has occurred is linearly aligned across a predetermined number of layers among the plurality of layers, the predetermined number being two or more, an error that has occurred in the memory is a soft error due to radiation incident on the memory.

Abstract: A method of controlling repair of a volatile memory device, includes, performing a patrol read operation repeatedly to provide error position information of errors included in read data from a volatile memory device, generating accumulated error information by accumulating the error position information based on the patrol read operation performed repeatedly, determining error attribute based on the accumulated error information, the error attribute indicating correlation between the errors and a structure of the volatile memory device, and performing a runtime repair operation with respect to the volatile memory device based on the accumulated error information and the error attribute. The errors may be managed efficiently to prevent failure of the volatile memory device, and thus performance and lifetime of the volatile memory device and the storage device may be enhanced.

Abstract: A basic input/output system may be configured to, during a boot of the information handling system and responsive to a condition for launching the secondary operating system: initialize a network driver for communicating with a network via a network interface, download from a secure, verified network location within the network a security manifest file for a most recent version of the secondary operating system, the security manifest file comprising metadata regarding a file system layout for the most recent version of the secondary operating system, based on the file system layout of the security manifest file and an actual file system layout of the secondary operating system as stored within an information handling system, determine one or more portions of the secondary operating system requiring update, and download the one or more portions of the secondary operating system and apply the one or more portions to the secondary operating system as stored within the information handling system.

Abstract: A method is used in ensuring data integrity in data storage. A set of physical pages that include data for a virtual page is identified on a storage device. A set of reconstructed pages is generated from other storage devices, and each reconstructed page corresponds to a page in the set of physical pages. One or more pages from the set of physical pages and the set of reconstructed pages with data yielding a checksum that matches a checksum for the virtual page is identified, and data corresponding to the virtual page from the identified one or more pages is obtained.

Abstract: A method for preventing read disturbance accumulation in a cache memory. The method includes accessing a plurality of data lines in a cache set, generating a plurality of corrected data from a plurality of initial data based on a plurality of error correction codes (ECCs), and selecting a respective corrected data of the plurality of corrected data based on a respective way of a plurality of ways. Each of the plurality of data lines includes a respective data field of a plurality of data fields and a respective ECC field of a plurality of ECC fields. The plurality of initial data are stored in the plurality of data fields and the plurality of ECCs are stored in the plurality of ECC fields. Each of the plurality of ways is associated with a respective data line of the plurality of data lines.

Abstract: A method includes performing a quantity of write cycles on memory components. The method can further include monitoring codewords, and, for each of the codewords including a first error parameter value, determining a second error parameter value. The method can further include determining a probability that each of the codewords is associated with a particular one of the second error parameter values at the first error parameter value and determining a quantity of each of the codewords that are associated with each of the determined probabilities. The method can further include determining a statistical boundary of the quantity of each of the codewords and determining a correlation between the quantity of write cycles performed and the corresponding determined statistical boundary of the quantity of each of the codewords.

Abstract: Provided herein may be a memory controller and an operating method thereof. The memory controller may include: a read fail control circuit configured to perform, when the read operation fails, an assist read operation of determining optimal read voltages to be used to read the selected memory cells, and determine whether a threshold voltage distribution of the selected memory cells is an abnormal distribution based on read-related information obtained by the read operation and the assist read operation; and an error correction code (ECC) engine configured to perform an ECC decoding operation on hard decision data obtained by reading the selected memory cells using the optimal read voltages based on whether the threshold voltage distribution of the selected memory cells is the abnormal distribution.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller. The memory controller is configured: to store, in a buffer, a data set read from a cell unit, and an expected data set generated by an error correction on the data set; to count a number of first and second memory cells corresponding to a first and a second combination of data in the data set and the expected data set, respectively, among the memory cells in the cell unit; to calculate a shift amount of a read voltage used in a read operation from the cell unit, based on the number of the first and second memory cells; and to apply the shift amount to a next read operation from the first cell unit.

Abstract: To provide a storage device by which distribution of data to an added memory device may be carried out in a short period of time. In a case where any new SSD is added to the storage device, a storage controller carries out first data distribution processing moving any piece of user data in a parity group from existing SSDs to the added SSD and second data distribution processing increasing the number of pieces of the user data configuring the parity group from a first number to a second number after the first data distribution processing and storing the user data in a plurality of memory devices SSDs.

Abstract: A method for execution by a dispersed storage and task (DST) processing unit includes: generating an encoded data slice from a dispersed storage encoding of a data object and determining when the encoded data slice will not be stored in local dispersed storage. When the encoded data slice will not be stored in the local dispersed storage, the encoded data slice is stored via at least one elastic slice in an elastic dispersed storage, an elastic storage pointer is generated indicating a location of the elastic slice in the elastic dispersed storage, and the elastic storage pointer is stored in the local dispersed storage.

Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.

Abstract: Provided is a controller in which resources can be safely shared by a plurality of processors, such as multi-processors or multi-core processors. The controller is provided with the plurality of processors which each manage the resources or share the resources and include a first processor configured to perform processing with an influence on the integrity of the resources and a second processor. The second processor performs sequence processing for maintaining the integrity of the resources in accordance with the contents of the processing by the first processor, upon receiving a request message requesting the processing to be started.

Abstract: Restore operations in containerized environments are disclosed. An ephemeral instance of an application is created and a datastore is mounted to the ephemeral instance. The ephemeral instance is not accessible to users or application. The backup data is restored to the datastore. Once restored, the datastore is then mounted to a production instance and production resumes.

Abstract: Memory components can be determined to store one or more stripes of data. Data for one or more stripes of data can be stored based on the determined memory components. An indication that an endurance condition of the memory components has satisfied an endurance condition threshold can be received. In response to receiving the indication that the endurance condition of the memory components has satisfied the endurance condition threshold, the memory components that are to store a subsequent stripe of data can be changed. Data for the subsequent stripe of data can be stored based on the changed memory components.

Abstract: Apparatus, media, methods, and systems are disclosed for improved data relocation based on read-level voltages. A data storage system may include a non-volatile memory device including a source region and a destination region. The destination region may include a first destination block and a second destination block. A controller may read first data in the source region using a first read-level voltage, and read second data in the source region using a second read-level voltage. The controller may associate, based on the first and second read-level voltages, each of the first data and the second data with a respective one of the first and the second destination blocks. The controller may cause each of the first and second data to be stored in the associated one of the first and second destination blocks.

Abstract: An electronic device includes a processor, a timer and a memory device. The memory device stores a value for power-on hours. During the process of booting the electronic device, the processor triggers the timer to start counting down. When the timer expires, the processor updates the value of power-on hours.

Abstract: The rate at which reads on a target memory portion initiate error recovery procedures can be monitored in real-time. Trigger rates can be used to perform analysis of a memory sub-system or to implement improvements in the memory sub-system. Trigger rate monitoring can include accessing a count of error recovery initializations for a target memory portion, wherein the count of error recovery initializations corresponds to a number of times a first stage of a multi-stage error recovery process was performed. Trigger rate monitoring can further include accessing a count of read operations corresponding to the target memory portion. The count of error recovery initializations and the count of read operations can be used to compute a trigger rate. The trigger rate, or multiple trigger rates from various times or from various target memory portions, can be used to compute a metric for the memory portion(s).

Abstract: A computer program product, system, and method for switching over from using a first primary storage to using a second primary storage when the first primary storage is in a mirror relationship. Migration operations are initiated to migrate data in the first primary storage to a second primary storage while the data in the first primary storage indicated in first change recording information is mirrored to a secondary storage and switch from using the first primary storage to the second primary storage. Resynchronization operations are initiated to indicate changes to data in the second primary storage in a second change recording information, copy writes from the second primary storage indicated in the first and the second change recording information to the secondary storage, and mirror writes to the second primary storage to the secondary storage in response to the copying the writes.

Abstract: A data writing method, a memory controlling circuit unit and a memory storage device are provided. The method includes: receiving a plurality of data; writing the plurality of data into a first physical erasing unit by using a multi-page programming mode; and writing at least one first data of the plurality of data into a second physical erasing unit by using a single-page programming mode; verifying the plurality of data stored in the first physical erasing unit; and if the verification fails, performing a writing operation to a third physical erasing unit by using the multi-page programming mode according to the at least one first data and the plurality of data.