Abstract: Embodiments of systems, apparatuses, and methods for utilizing a faulty cache line in a cache are described. In some embodiments, a graphics processing unit is allowed to access a faulty cache line in the cache. A cache access request to access a faulty cache line from a central processing unit core is remapped to access a fault-free cache line.

Abstract: A memory system comprises a flash memory and a memory controller. The flash memory comprises a plurality of memory blocks. The memory controller performs a read retry operation on a memory block containing an uncorrectable read error until an accurate data value is read from the memory block. The memory controller then controls the flash memory to perform an erase refresh operation on the memory block.

Abstract: One embodiment of the present invention sets forth a memory module that includes at least one memory chip, and an intelligent chip coupled to the at least one memory chip and a memory controller, where the intelligent chip is configured to implement at least a part of a RAS feature. The disclosed architecture allows one or more RAS features to be implemented locally to the memory module using one or more intelligent register chips, one or more intelligent buffer chips, or some combination thereof. Such an approach not only increases the effectiveness of certain RAS features that were available in prior art systems, but also enables the implementation of certain RAS features that were not available in prior art systems.

Abstract: A technique is provided for a cache. A cache controller accesses a set in a congruence class and determines that the set contains corrupted data based on an error being found. The cache controller determines that a delete parameter for taking the set offline is met and determines that a number of currently offline sets in the congruence class is higher than an allowable offline number threshold. The cache controller determines not to take the set in which the error was found offline based on determining that the number of currently offline sets in the congruence class is higher than the allowable offline number threshold.

Abstract: A hybrid drive is disclosed comprising a head actuated over a disk comprising a plurality of data sectors, a volatile semiconductor memory (VSM), and a non-volatile semiconductor memory (NVSM). A first write command is received from a host, the first write command comprising first data. The first data is stored in the VSM and written to a first data sector on the disk. The first data is read from the first data sector at least once during a first read operation, and when the first read operation fails, the first data is written to the NVSM. The first data sector is read at least once during a second read operation, and when the second read operation fails, the first data sector is mapped out.

Abstract: System and methods of selectively managing errors in memory modules. In an exemplary implementation, a method may include monitoring for persistent errors in the memory modules. The methods may also include mapping at least a portion of the memory modules to a spare memory cache only to obviate persistent errors. The method may also include initiating memory erasure on at least a portion of the memory modules only if insufficient cache lines are available in the spare memory cache.

Abstract: Memory devices and methods are disclosed, including a method involving erasing a block of memory cells. After erasing the block, and before subsequent programming of the block, a number of bad strings in the block are determined based on charge accumulation on select gate transistors. The block is retired from use if the number of bad strings exceeds a threshold. Additional embodiments are disclosed.

Abstract: A repair control circuit and a semiconductor integrated circuit using the same, which can reduce test time, are provided. The semiconductor integrated circuit includes a plurality of memory blocks in which a plurality of word lines are arranged, a plurality of word line drivers driving one or more of the plurality of word lines in response to a plurality of memory block selection signals, and a repair control circuit determining whether to perform a repair through comparison of repair addresses generated in response to surplus addresses and the plurality of memory block selection signals with external addresses.

Abstract: A storage controller is configured to determine a reliability metric of a storage division of a solid-state storage medium based on one or more test read operations. The storage division may be retired based on the reliability metric and/or the age of the data on the storage division. A storage division comprising aged data may be marked for post-write reliability testing, which may comprise determining a post-write reliability metric in response to grooming and/or reprogramming the storage division. The storage controller may project the reliability metric of the storage division to the end of a predetermined data retention period. Portions of a storage divisions that exhibit poor reliability may be removed to improve the reliability of the storage division without taking the entire storage division out of service.

Abstract: A storage apparatus for storing data includes a plurality of physical media provided with storage areas to store data, a storage group determining unit configured to determine, upon detecting a request to write new data to a virtual volume to be accessed, a storage group from which to allocate storage area by selecting a storage group from among a plurality of storage groups made up of the plurality of physical media, wherein the selected storage group is other than any storage groups that include a physical medium where a failure has occurred, and a storage area allocator configured to allocate storage area on the physical media existing within the storage group that was determined by the storage group determining unit to the virtual volume, the size of the storage area corresponds to the data size of the new data.

Abstract: According to one embodiment, a data storage apparatus includes a read module, an error detector and a controller. The read module is configured to read data from a flash memory, more precisely from a rewrite area and a write-back area, both provided in the flash memory. The error detector is configured to detect errors, if any, in the data read. The controller is configured to keep rewriting data, without correcting the errors the error detector has detected in the rewrite area of the flash memory.

Abstract: Methods, devices, and systems for determining location of error detection data are described. One method for operating a memory unit having a bad group of memory cells includes determining a location of where to store error detection data for data to be stored across a plurality of memory units, including the memory unit having the bad group, based at least partially on a location of the bad group and storing the error detection data in the determined location.

Abstract: A method of operating a disk drive comprises scanning each Logical Block Address (LBA) of the disk drive to detect a read error or reading the LBA from a media defect list. The LBA may then be converted to a corresponding physical location on the media and a scan of the corresponding physical location and of nearby physical locations that are within a proximity threshold of the corresponding physical locations may be performed to find media defects. Based thereon, it may then be determined whether a media scratch is present and at least one or more data sectors associated with the media scratch may be relocated to a spare location on the media if the media scratch is determined to be present. If the media scratch is determined not to be present, only the data sector associated with the corresponding physical location may be relocated to the spare location.

Abstract: A computer is programmed to execute a diagnostic procedure either on a pre-set schedule or asynchronously in response to an event, such as an error message, or a user command. When executed, the diagnostic procedure automatically checks for integrity of one or more portions of data in the computer, to identify any failure(s). In some embodiments, the failure(s) may be displayed to a human, after revalidation to exclude any failure that no longer exists.

Abstract: Dynamically replicated memory is usable to allocate new memory space from failed memory pages by pairing compatible failed memory pages to reuse otherwise unusable failed memory pages. Dynamically replicating memory involves detecting and recording memory faults, reclaiming failed memory pages for later use, recovering from detected memory faults, and scheduling access to replicated memory pages.

Abstract: A Solid-State Disk (SSD) controller enables dynamic higher-level redundancy mode management with independent silicon elements to provide graceful degradation as non-volatile (e.g. flash) memory elements fail during operation of an SSD implemented by the controller. Higher-level error correction provides correction of lower-level uncorrectable errors. If a failure of one of the non-volatile memory elements is detected, then the higher-level error correction is dynamically transitioned from operating in a current mode to operating in a new mode. The transition includes one or more of reducing free space available on the SSD, rearranging data storage of the SSD, recovering/storing failed user data (if possible), and determining/storing revised higher-level error correction information. Operation then continues in the new mode. If another failure of the non-volatile memory elements is detected, then another transition is made to another new mode.

Abstract: Embodiments of the present invention provide methods, apparatuses, systems, and computer software products for data storage. A corrupted node under a first meta-volume node in a hierarchical tree structure is deleted. The hierarchical tree structure further includes a source node under the first meta-volume node. The corrupted node and the source node each include a respective set of local pointers. The corrupted node and the source node represent respective copies of a logical volume. The source node is reconfigured to become a second meta-volume node having the same set of local pointers as the source node. A first new node is created under the second meta-volume node in the hierarchical tree structure to represent the corrupted node. A second new node is created under the second meta-volume node to represent the source node. The first and second new nodes are configured to have no local pointers.

Abstract: In a storage sub-system adopting a redundant configuration for preventing data loss and continuing processing during failure, when failure occurs, a controller unit in which failure has occurred is blocked so as not to affect the normal controller unit, so that the performance of the storage sub-system is deteriorated and the redundancy thereof is lost until maintenance and component replacement is performed. According to the present invention, self diagnosis of the blocked area is executed and a failure area is isolated. Then, the blocked area is reconnected to the storage sub-system, so as to prevent deterioration of performance and overload of the device until maintenance and replacement is performed, and to reduce the time of failure analysis during maintenance by specifying the detailed failure area via self diagnosis.

Abstract: An address selector replaces an address pointing to a defective instruction in a built-in firmware. The address selector includes a comparing unit and a multiplexer. The comparing unit provides a comparison result by comparing a current address received from a processor with a predetermined address pointing to the defective instruction.

Abstract: In accordance with the present disclosure, a dynamic random access memory (DRAM) component is described. The DRAM component may comprise an integrated circuit, with the integrated circuit including an array of volatile memory cells. A first volatile memory cells of the array of volatile memory cells may be defective. The integrated circuit may also include non-volatile memory, and the non-volatile memory may contain a reference to the first volatile memory cell.

Abstract: Electronic apparatus, systems, and methods of operating and constructing the electronic apparatus and/or systems include an embedded processor disposed in a logic chip to direct, among other functions, self-testing of an electronic device structure in conjunction with a pattern buffer disposed in the logic chip, when the electronic device structure is coupled to the logic chip. Additional apparatus, systems, and methods are disclosed.

Abstract: A memory address remapping architecture is applied to execute an address remapping method for repairing a main memory. A valid flag and an essential flag in a TCAM corresponding to at least one subcube address in a spare memory are initialized, and the main memory is checked to find out some faulty cell addresses. The Hamming distance between the subcube address and the faulty cell address is calculated, and the faulty cell address is merged into the subcube address by a masked bits concentrator when the Hamming distance is not larger than an address-width degree of the subcube address and the merged number of the subcube address is not larger than a threshold value.

Abstract: A data protection method for damaged memory cells is provided. A power-on self-test (POST) is executed, and an initial backup memory is reserved in a memory. An operating system (OS) is executed, and data is loaded from a kernel region of the OS in the memory into a mirror region, so that when a processor accesses the data in the kernel region, it also accesses the data in the mirror region. An uncorrectable error (UE) is detected to determine a damaged page, and a backup page is selected from the initial backup memory or dynamically obtained from the OS to back up data in the damaged page. A mapping address of the damaged page and backup page are recorded into a page mapping table in a memory controller. Accordingly, when the OS accesses the damaged page, the memory controller accesses the backup page instead according to the page mapping table.

Abstract: Discarded memory devices unfit for an original purpose can be reclaimed for reuse for another purpose. The discarded memory devices are tested and evaluated to determine the level of performance degradation therein. A set of an alternate usage and an information encoding scheme to facilitate a reuse of the tested memory device is identified based on the evaluation of the discarded memory device. A memory chip controller may be configured to facilitate usage of reclaimed memory devices by enabling a plurality of encoding schemes therein. Further, a memory device can be configured to facilitate diagnosis of the functionality, and to facilitate usage as a discarded memory unit. Waste due to discarded memory devices can be thereby reduced.

Abstract: An electronic circuit includes first and second circuits that include corresponding built-in-self-test (BIST) engines to perform memory testing operations on corresponding first and second memory block and generate first and second memory repair data. A multiplexer receives the first and second memory repair data and selectively transmits the first memory repair data during a first test cycle and the second memory repair data during a second test cycle. A shadow register buffers the first memory repair data during the first test cycle and a fuse processor sequentially receives and stores the first and second memory repair data during the second test cycle.

Abstract: A method of managing a bad storage region of a memory device may include detecting a bad page of a selected data block that has failed in one of a program operation, a read operation, and an erase operation on the memory device; and performing a mapping process so that the detected bad page is excluded from a storage region to which data is to be programmed, wherein remaining pages of the selected data block excluding the bad page are allowed to be used as a storage region in a garbage collection operation.

Abstract: For writing, flash memory devices are physically accessed in a page-oriented mode, but such devices are not error-free in operation. According to the invention, when writing information data in a bus write cycle in a sequential manner into flash memory devices assigned to a common data bus, at least one of said flash memory devices is not fed for storage with a current section of said information data. In case an error is occurring while writing a current information data section into a page of a current one of said flash memory devices, said current information data section is written into a non-flash memory. During the following bus write cycle, while the flash memory device containing that defective page is normally idle, that idle time period is used for copying the corresponding stored section of said information data from said non-flash memory to a non-defect page of that flash memory device.

Abstract: In accordance with embodiments of the present disclosure, a method may comprise identifying one or more portions of the memory having defects. The method may also include storing one or more addresses in the memory defect list, each of the one or more addresses associated with a portion of the one or more identified portions. The method may further include indicating to components of an information handling system that the one or more identified portions are unusable such that the other components are prevented from allocating and using the one or more identified portions.

Abstract: Methods of memory management are described which can accommodate non-maskable failures in pages of physical memory. In an embodiment, when an impending non-maskable failure in a page of memory is identified, a pristine page of physical memory is used to replace the page containing the impending failure and memory mappings are updated to remap virtual pages from the failed page to the pristine page. When a new page of virtual memory is then allocated by a process, the failed page may be reused if the process identifies that it can accommodate failures and the process is provided with location information for impending failures. In another embodiment, a process may expose information on failure-tolerant regions of virtual address space such that a physical page of memory containing failures only in failure-tolerant regions may be used to store the data instead of using a pristine page.

Abstract: A memory apparatus includes a memory having a main memory area and a replacement area, and a memory controller having a function of issuing instructions corresponding to commands to carry out transmission and reception of data and reading of status information of the memory.

Abstract: Searching for patterns stored on a hardware storage device. A method includes, as part of a memory refresh operation, performing a read to read contents of a portion of a memory. The method further includes writing the read contents of the portion of memory back to the portion of memory. The read contents are provided to data comparison logic. Using the data comparison logic; the read contents are compared to predetermined data patterns. A determination is made as to whether or not the contents match at least one of the predetermined data patterns. When the read contents match at least one of the predetermined data patterns, a software readable indicator is provided indicating that the read contents match at least one of the predetermined data patterns. Similar embodiments may be implemented using hard drive head wear leveling operations.

Abstract: The invention provides a data storage device. In one embodiment, the data storage device is coupled to a host, and comprises a downgrade memory and a controller. The downgrade memory comprises a plurality of blocks, wherein each of the blocks comprises a plurality of pages, each of the pages comprises a plurality of sectors, and some of the sectors are defect sectors. The controller generates a defect table for recording a plurality of defect addresses of the defect sectors in the blocks, receives a plurality of data sectors to be written to the downgrade memory from the host, determines a plurality of first physical sector addresses for storing the data sectors according to the defect table, and sends write commands to the downgrade memory to direct the downgrade memory to write the data sectors to the downgrade memory according to the first physical sector addresses.

Abstract: Memory systems and related defective block management methods are provided. Methods for managing a defective block in a memory device include allocating a defective block when a memory block satisfies a defective block condition. The allocated defective block is cancelled when the allocated defective block satisfies a defective block cancellation condition.

Abstract: The systems and methods described herein may provide a flush-retire instruction for retiring “bad” cache locations (e.g., locations associated with persistent errors) to prevent their allocation for any further accesses, and a flush-unretire instruction for unretiring cache locations previously retired. These instructions may be implemented as hardware instructions of a processor. They may be executable by processes executing in a hyper-privileged state, without the need to quiesce any other processes. The flush-retire instruction may atomically flush a cache line implicated by a detected cache error and set a lock bit to disable subsequent allocation of the corresponding cache location. The flush-unretire instruction may atomically flush an identified cache line (if valid) and clear the lock bit to re-enable subsequent allocation of the cache location. Various bits in the encodings of these instructions may identify the cache location to be retired or unretired in terms of the physical cache structure.

Abstract: The present disclosure includes methods, devices, and systems for error detection/correction based memory management. One embodiment includes performing a read operation with respect to a particular group of memory cells of a memory device and, if the read operation results in an uncorrectable error, determining whether to retire the particular group of memory cells in response to a status of an indicator corresponding to the particular group of memory cells, wherein the status of the indicator indicates whether the particular group of memory cells has a previous uncorrectable error associated therewith.

Abstract: An information storage device includes a semiconductor memory divided into storage regions and a management unit. The management unit manages the storage regions so that any storage region which caused read or write errors a predetermined threshold number of times, which may be two or more, is made unavailable for storing data.

Abstract: One embodiment of the present invention sets forth a memory module that includes at least one memory chip, and an intelligent chip coupled to the at least one memory chip and a memory controller, where the intelligent chip is configured to implement at least a part of a RAS feature. The disclosed architecture allows one or more RAS features to be implemented locally to the memory module using one or more intelligent register chips, one or more intelligent buffer chips, or some combination thereof. Such an approach not only increases the effectiveness of certain RAS features that were available in prior art systems, but also enables the implementation of certain RAS features that were not available in prior art systems.

Abstract: Embodiments are described for managing memory faults. An example system can include a memory controller module to manage memory cells and report memory faults. An error buffer module can store memory fault information received from the memory controller. A notification module can be in communication with the error buffer module. The notification module may generate a notification of a memory fault in a memory access operation. A system software module can provide services and manage executing programs on a processor. In addition, the system software module can receive the notifications of the memory fault for the memory access operation. A notification handler may be activated by an interrupt when the notification of the memory fault in the memory access operation is received.

Abstract: A memory system according to the present invention includes, in addition to an computing device, a plurality of first blocks that are provided to store information including user information, and first physical addresses not overlapping one another are assigned to, respectively, and a plurality of second blocks that are provided to store first physical addresses of initial defect blocks out of the plurality of first blocks, respectively, wherein the computing device finds the first physical address corresponding a inputted given logical address, based on a given mirror logical address corresponding to the given logical address, and information stored in the second blocks.

Abstract: According to one embodiment, an information recording apparatus for recording, in a free area, first low-quality recorded data having an error rate not less than a first error rate upon finalization of a recording medium, the information recording apparatus includes a reader, a measurement module, a detector, and a recorder. The reader is configured to read recorded data from a recording area of the recording medium. The measurement module is configured to measure an error rate of the recorded data of each predetermined data block. The detector configured to detect the first low-quality recorded data based on an error rate measurement result of the measurement module. The recorder is configured to correct an error in the first low-quality recorded data, and record error-corrected recorded data corresponding to the first low-quality recorded data at a spare recording position of the free area of the recording medium.

Abstract: An electronic device is provided including an input/output (I/O) interface, a plurality of memory elements, a controller coupled to the I/O interface and the plurality of memory elements. In the device, the controller configured for operating the plurality of memory elements during a normal operating mode of the electronic device, where responsive to receiving a command for replacing a selected memory sector in the electronic device during the normal operating mode, the controller is configured for identifying one or more available spare memory sectors in the electronic device and modifying at least one memory map in the electronic device to replace the selected memory sector with the one of the available spare memory sectors.

Abstract: A solid state storage system includes a flash memory region comprising a plurality of memory blocks and a plurality of replacement blocks corresponding to error-occurred blocks when errors occur in the memory blocks; and a memory controller configured to perform a control operation to replace the error-occurred blocks with the replacement blocks, wherein the error-occurred blocks comprise correctable blocks and uncorrectable blocks, and wherein the memory controller determines whether the error-occurred blocks are the correctable blocks or the uncorrectable blocks and controls zones of the replacement blocks, replaced in correspondence to the correctable blocks, to be allocated a plurality of times.

Abstract: Various embodiments comprise apparatus, methods, and systems including method comprising searching for a group address among a plurality of group addresses in a mapping table, and if a match is found, performing a memory operation on a first plurality of memory blocks indicated by the mapping table, and if a match is not found, performing a memory operation on a second plurality of memory blocks, the second plurality of memory blocks having the group address.

Abstract: The system and method are for efficient detection and restoration of data storage array defects. The system may include a data storage subsystem, wherein the data storage subsystem includes a data storage array, read-write logic coupled to the data storage array, a parity generator for producing and storing check data during write operations to the data storage array and generating check data during read operations on the data storage array, and a parity checker for verifying the stored check data with generated check data and identifying defective data read-write elements during read operations on the data storage array. The subsystem may further include a Built-in Self Test (BIST) generator operating only on the identified defective data read-write elements for determining defective data storage elements in the defective data read-write elements, and a restoration mechanism for restoring the valid operation of data access elements containing the defective data storage elements in the data storage array.

Abstract: For writing, flash memory devices are physically accessed in a page-oriented mode, but such devices are not error-free in operation. According to the invention, when writing information data in a bus write cycle in a sequential manner into flash memory devices assigned to a common data bus, at least one of said flash memory devices is not fed for storage with a current section of said information data. In case an error is occurring while writing a current information data section into a page of a current one of said flash memory devices, said current information data section is written into a non-flash memory. During the following bus write cycle, while the flash memory device containing that defective page is normally idle, that idle time period is used for copying the corresponding stored section of said information data from said non-flash memory to a non-defect page of that flash memory device.

Abstract: A region-based management method of a non-volatile memory is provided. In the region-based management method, the storage space of all chips in the non-volatile memory is divided into physical regions, physical block sets, and physical page sets, and a logical space is divided into virtual regions, virtual blocks, and virtual pages. In the non-volatile memory, each physical block set is the smallest unit of space allocation and garbage collection, and each physical page set is the smallest unit of data access. The region-based management method includes a three-level address translation architecture for converting logical block addresses into physical block addresses.

Abstract: An apparatus of recording data on a recording medium includes an optical recording device and a microcomputer. The recording medium has a lead-in area, a lead-out area, and a data zone, where the data zone has a user data area and a spare area. When the microcomputer receives a command for physically overwriting first data in a first area within the user data area and determines that the first area is included in a pre-recorded area, it controls the recording device to record the first data in a first replacement area instead and to record a first entry in a TDMA, where the first entry specifies the locations of the first area and the first replacement area.

Abstract: Each cache line of a cache has a lockout state that indicates whether an error has been detected for data accessed at the cache line, and also has a data validity state, which indicates whether the data stored at the cache line is representative of the current value of data stored at a corresponding memory location. The lockout state of a cache line is indicated by a set of one or more lockout bits associate with the cache line. In response to a cache invalidation event, the state of the lockout indicators for each cache line can be maintained so that locked out cache lines remain in the locked out state even after a cache invalidation. This allows memory error management software executing at the data processing device to robustly manage the state of the lockout indicators.

Abstract: A solid state drive may include one or more memory cell arrays divided into a plurality of blocks. A first portion of the blocks may be designated for storing user data and a second portion of the blocks may be designated as reserved blocks for replacing defective blocks in the first portion. In one embodiment, the method includes reformatting, by a memory controller, the solid state drive to convert one or more blocks in the first portion into reserved blocks.

Abstract: Methods and apparatus relating to home agent data and memory management are described. In one embodiment, a scrubber logic corrects an error at a location in a memory corresponding to a target address by writing back the corrected version of data to the target location. In an embodiment, a map out logic maps out an index or way of a directory cache in response to a number of errors, corresponding to the directory cache, exceeding a threshold value. Other embodiments are also disclosed.