Data Formatting To Improve Error Detection Correction Capability Patents (Class 714/701)
  • Patent number: 11139918
    Abstract: Various embodiments provide an interleaving method, to improve error correction performance of a polar code. In these embodiments, a first bit sequence is obtained. The first bit sequence includes L number of bits, and L is a positive integer. The L number of bits are then written into an interleaving matrix according to a preset write rule. The interleaving matrix includes C rows and R number of columns. C and R are positive integers. The L number of bits can be read from the interleaving matrix according to a preset read rule to obtain a second bit sequence. The second bit sequence includes L number of bits; and sending the second bit sequence.
    Type: Grant
    Filed: March 8, 2020
    Date of Patent: October 5, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yue Zhou, Guijie Wang, Rong Li, Yinggang Du
  • Patent number: 11062743
    Abstract: A system and method for providing a configurable timing control of a memory system is provided. One system has a first interface to receive a DIMM clock and configuration information, a second interface to a first data bus, and a third interface to a second data bus. The system further has flip-flops, a multiplexer coupled to the flip-flops, a first control block for controlling to hold an input data within the flip-flops, and a second control block for controlling a timing of an output data from the flip-flops via the multiplexer with a programmable delay. The input data is received via the second interface. The programmable delay is received via the first interface. The output data is sent out with the timing delay via the third interface.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: July 13, 2021
    Assignee: Rambus, Inc.
    Inventors: Michael L. Takefman, Maher Amer, Claus Reitlingshoefer, Riccardo Badalone
  • Patent number: 11063693
    Abstract: A loss correction encoding device having an improved capability of loss correction using LDPC-CC includes a rearranging unit that rearranges information data contained in n information packets according to the constraint length Kmax and the encoding rate (q?1)/q of a check polynomial of the loss correction code used in a loss correction encoding unit. Specifically, the rearranging unit rearranges the information data in such a way that continuous Kmax×(q?1) pieces of information data after rearrangement are contained in different information packets. The rearranging unit distributes the information data to information blocks from n information packets, where n satisfies the formula Kmax×(q?1)?n.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: July 13, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Yutaka Murakami, Shutai Okamura
  • Patent number: 11063666
    Abstract: A communication device includes an interleaving unit that determines an interleaving length of transmit data to be transmitted through free-space optical communication, and interleaves the transmit data based on the determined interleaving length, and a shaping unit that shapes the interleaved transmit data so as to make the interleaving length detectable on a receiving side of the free-space optical communication.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: July 13, 2021
    Assignee: SONY CORPORATION
    Inventor: Shinji Ohta
  • Patent number: 11036709
    Abstract: In a general aspect, a method includes inserting a record in a partitioned fact table of a star schema data mart. Inserting the record can include determining a first hash value from a first dimension value of the record and determining a first set of candidate partitions from the first hash value. The method can further include determining a second hash value from a second dimension value of the record and determining a second set of candidate partitions from the first hash value. The method can further include comparing the first set of candidate partitions with the second set of candidate partitions to determine a common partition and inserting the record into the common partition.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: June 15, 2021
    Assignee: SAP SE
    Inventor: Christian Bensberg
  • Patent number: 11012591
    Abstract: A method implemented on a computing device including at least one processor and a storage for synchronizing video transmission with physical layer. The method includes determining a first time point corresponding to a frame header of a video frame, determining a second time point corresponding to a frame header of a physical layer frame based at least in part on the first time point, and starting transmitting the video frame at the second time point.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: May 18, 2021
    Assignee: SZ DJI TECHNOLOGY CO., LTD.
    Inventor: Xiaodong Wang
  • Patent number: 11005818
    Abstract: Some embodiments described herein relate managing communications between an origin and a destination using end-user and/or administrator configurable virtual private network(s) (VPN(s)). A first VPN that defines a first data path between an origin and a destination can be defined at a first time. A second VPN that defines a second, different data path between the origin and the destination can defined at a second time. Each packet sent across the first VPN and each packet sent across the second VPN can follow the same data path for that VPN, such each packet can be sent across the first VPN or the second VPN in the order it was received, and the transition between the first VPN and the second VPN can be “seamless,” and communications between the origin and the destination are not disrupted between the first time period and the second time period.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: May 11, 2021
    Assignee: NetAbstraction, Inc.
    Inventor: Ira A. Hunt, IV
  • Patent number: 10997175
    Abstract: A method for performing row qualification in database table retrieval and join operations. This method, referred to as bulk qualification, evaluates conditions on multiple rows in a database table at the same time, providing more efficient utilization of memory bandwidth and CPU throughput.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: May 4, 2021
    Assignee: Teradata US, Inc.
    Inventors: Bhashyam Ramesh, Tirupathi Prabhu Bellapukonda, Mohan Kumar KJ, Vamshi Krishna Vangapalli
  • Patent number: 10985914
    Abstract: A key generation device includes a generation circuit, a concealment processing unit, and a cryptography processing unit. The generation circuit generates a value dependent on hardware. When acquiring a concealed cryptographic key, the concealment processing unit generates first data by performing a mask process to the concealed cryptographic key by using the value generated by the generation circuit, generates second data by decoding the first data by a first error correction decoding method, and generates a cryptographic key by decoding the second data by a second error correction decoding method. When acquiring the concealed cryptographic key and a plain text or an encrypted text, the cryptography processing unit acquires the cryptographic key corresponding to the concealed cryptographic key from the concealment processing unit, and encrypts the plain text or decrypts the encrypted text by using the cryptographic key.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: April 20, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Yasuo Noguchi, Takeshi Shimoyama
  • Patent number: 10890540
    Abstract: A method including selecting a shaped feature from a set of shaped features, each shaped feature of the set of shaped features having a set of points on a perimeter of the shape of the shaped feature, creating a plurality of shape context descriptors for the selected shaped feature, wherein each shape context descriptor provides an indication of a location in a shape context descriptor framework of a first focus point of the set of points in relation to a second point of the set of points, and identifying a shaped feature from the set of shaped features having a same or similar shape as the selected shaped feature based on data from the plurality of shape context descriptors.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: January 12, 2021
    Assignee: ASML Netherlands B.V.
    Inventors: Adrianus Cornelis Matheus Koopman, Scott Anderson Middlebrooks, Willem Marie Julia Marcel Coene
  • Patent number: 10848224
    Abstract: A method and an apparatus for reporting channel state information (CSI) by a user equipment in a wireless communication system. According to the present invention, the UE receives configuration information related to reporting of the CSI from a base station, wherein the configuration information may include a threshold value related to a specific condition for receiving the CSI and the CSI may comprise a first part and a second part. A method and an apparatus may be provided in which the UE receives a first reference signal for channel measurement from the base station, measures a channel based on the first reference signal, and reports the CSI of the measured channel to the base station and some or all of the second part of the CSI is omitted.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: November 24, 2020
    Assignee: LG Electronics Inc.
    Inventors: Haewook Park, Kijun Kim, Jiwon Kang
  • Patent number: 10831596
    Abstract: A first tier of error correcting code operations on a data block may be performed. The first tier of error correcting code operations on the data block may be determined to be associated with an unsuccessful correction of an error of the data block. Responsive to determining that the first tier of error correcting code operations on the data block are associated with the unsuccessful correction of the error of the data block, a remix operation on the data block to change a logical to physical association of the data block from a first logical association to a second logical association may be performed.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: November 10, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Samuel E. Bradshaw
  • Patent number: 10790855
    Abstract: Field error correction coding is particularly suitable for applications in non-volatile flash memories. We describe a method for error correction encoding of data to be stored in a memory device, a corresponding method for decoding a codeword matrix resulting from the encoding method, a coding device, and a computer program for performing the methods on the coding device, using a new construction for high-rate generalized concatenated (GC) codes. The codes, which are well suited for error correction in flash memories for high reliability data storage, are constructed from inner nested binary Bose-Chaudhuri-Hocquenghem (BCH) codes and outer codes, preferably Reed-Solomon (RS) codes. For the inner codes extended BCH codes are used, where only single parity-check codes are applied in the first level of the GC code. This enables high-rate codes.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: September 29, 2020
    Assignee: HYPERSTONE GMBH
    Inventors: Juergen Freudenberger, Jens Spinner, Christoph Baumhof
  • Patent number: 10778253
    Abstract: An embodiment method includes: performing balancing processing on a data stream that includes a plurality of sub-data stream segments, and performing segment de-interleaving on a data stream obtained after the balancing processing. The method further includes separately performing forward error correction (FEC) decoding on each sub-data stream segment in a data stream obtained after the segment de-interleaving. The method further includes performing, according to a balancing termination state of each sub-data stream segment obtained after previous balancing processing, balancing processing on each sub-data stream segment obtained after the FEC decoding, and performing FEC decoding on the data stream obtained after balancing processing is performed on each sub-data stream segment. When it is determined that a preset iteration termination condition is met, the method includes outputting the data stream obtained after the FEC decoding.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: September 15, 2020
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Zhiyu Xiao, Ling Liu, Liangchuan Li
  • Patent number: 10769012
    Abstract: The present invention relates to a memory with error correction function, comprising a data array, an ECC array, a flag bit array, an ECC encoding module, an ECC decoding module, a flag bit generation module and a flag bit detection module; wherein: the flag bit generation module is configured, when data is being written, to generate a flag bit and an encode enable signal, the flag bit being stored in the flag bit array, and the encode enable signal being used to control the operation of the ECC encoding module; the ECC encoding module is configured to encode the data to be written according to the ECC algorithm preset therein so as to generate parity bits; the ECC array is configured to store the generated parity bits; the flag bit detection module is configured, when data is being read, to detect the flag bit and control the operation of the ECC decoding module; and the ECC decoding module is configured to detect and correct erroneous data using the parity bits from the ECC array and the data from the data
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: September 8, 2020
    Assignee: XI'AN UNIIC SEMICONDUCTORS CO., LTD.
    Inventor: Alessandro Minzoni
  • Patent number: 10749732
    Abstract: The present invention is directed to data communication. In certain embodiments, the present invention provides switching mechanism for choosing between redundant communication links. Data received from a first set of communication links are processed to have alignment markers removed, and first figure of merit value is determined based on the data without alignment markers. Similarly, a second figure of merit value is determined for the data received from the second set of communication links. A switch selects between the first set of communication links and the second set of communication links based on their respective figure of merit values. Alignment markers are inserted into the data transmitted through the selected set of data links. There are other embodiments as well.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: August 18, 2020
    Assignee: INPHI CORPORATION
    Inventors: Arash Farhoodfar, Jitendra Swarnkar, Michael Duckering, Andre Sczapanek, Scott Feller, Shaun Lytollis
  • Patent number: 10735136
    Abstract: Provided are a base station apparatus, a terminal apparatus and a communication method, capable of an efficient retransmission control of uplink data of which a resource for transmission is not discerned in grant-free multiple access. A terminal apparatus configured to communicate with a base station apparatus includes a transmitter configured to transmit an identifying signal indicating that the terminal apparatus itself transmits an uplink data channel and the uplink data channel. The uplink data channel includes an uplink data bit, a bit representing an identifier of the terminal apparatus, a first error detection bit generated from the uplink data bit, and a second error detection bit generated from the identifier of the terminal apparatus. The first error detection bit is scrambled using the identifier of the terminal apparatus, and the second error detection bit is scrambled using the identifying signal.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: August 4, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Takashi Yoshimoto, Jungo Goto, Osamu Nakamura, Yasuhiro Hamaguchi
  • Patent number: 10721020
    Abstract: A super-frame for transmission in an optical communications system comprises two or more data frames and a parity frame. All frames in the super-frame have been encoded in accordance with a first Forward Error Correction (FEC) scheme. The parity frame is computed over the two or more data frames (prior to or concurrently with or after encoding via the first FEC scheme) according to a second FEC scheme. At a receiver, the super-frame is decoded in accordance with the first FEC scheme to generate a set of FEC decoded frames in which residual errors are clustered, that is, are non-Poisson. The second FEC scheme, which is particularly suited or designed to correct the clustered non-Poisson residual errors, is used to correct the residual errors.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: July 21, 2020
    Assignee: Ciena Corporation
    Inventors: Kim B. Roberts, Amir K. Khandani
  • Patent number: 10707902
    Abstract: A permutation network designing method and a permutation circuit using the same are provided. The method includes: identifying a predetermined check matrix of the QC-LDPC decoder, wherein the check matrix comprises M×N sub-matrices, wherein each of the sub-matrices is a Z×Z matrix, wherein Z is a default dimension value of each of the sub-matrices; constructing a second permutation network of a permutation circuit by removing a target first permutation layer from a first permutation layer according to a shift type of the check matrix, wherein the amount of a plurality of second permutation layers and the amount of the second nodes of each of the second permutation layers are set according to the default dimension value; and disposing a plurality of selectors on the second nodes of the constructed second permutation network of the permutation circuit.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: July 7, 2020
    Assignee: Shenzhen EpoStar Electronics Limited CO.
    Inventor: Yu-Hua Hsiao
  • Patent number: 10700708
    Abstract: A permutation network designing method and a permutation circuit using the same are provided. The method includes: identifying a predetermined check matrix of the QC-LDPC decoder, wherein the check matrix comprises M×N sub-matrices, wherein each of the sub-matrices is a Z×Z matrix, wherein Z is a default dimension value of each of the sub-matrices; constructing a permutation network of a permutation circuit according to the default dimension value and a saving parameter, wherein the permutation network comprises a plurality of permutation layers arranged sequentially, and each of the permutation layers has the same amount of nodes, wherein the amount of the permutation layers and the amount of the nodes of each of the permutation layers are set according to the default dimension value and a saving parameter; and disposing a plurality of selectors on the nodes of the permutation network of the permutation circuit.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: June 30, 2020
    Assignee: Shenzhen EpoStar Electronics Limited CO.
    Inventors: Yu-Hua Hsiao, Heng-Lin Yen
  • Patent number: 10579561
    Abstract: A communication interface couples a transmission circuit with an interconnection network. The transmission circuit requests transmission of a predetermined amount of data. The communication interface receives data segments from the transmission circuit, stores the data segments in a memory, and verifies whether the memory contains the predetermined amount of data. When the memory contains the predetermined amount of data, the communication interface starts transmission of the data stored in the memory. Alternatively, when the memory contains an amount of data less than the predetermined amount of data, the communication interface determines a parameter that identifies the time that has elapsed since the transmission request or the first datum was received from the aforesaid transmission circuit, and verifies whether the time elapsed exceeds a time threshold. In the case where the time elapsed exceeds the time threshold, the communication interface starts transmission of the data stored in the memory.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: March 3, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Daniele Mangano, Mirko Dondini, Salvatore Pisasale
  • Patent number: 10516650
    Abstract: Some embodiments described herein relate managing communications between an origin and a destination using end-user and/or administrator configurable virtual private network(s) (VPN(s)). A first VPN that defines a first data path between an origin and a destination can be defined at a first time. A second VPN that defines a second, different data path between the origin and the destination can defined at a second time. Each packet sent across the first VPN and each packet sent across the second VPN can follow the same data path for that VPN, such each packet can be sent across the first VPN or the second VPN in the order it was received, and the transition between the first VPN and the second VPN can be “seamless,” and communications between the origin and the destination are not disrupted between the first time period and the second time period.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: December 24, 2019
    Assignee: NETABSTRACTION, INC.
    Inventor: Ira A. Hunt, IV
  • Patent number: 10504608
    Abstract: In one embodiment, linked-list interlineation of data in accordance with the present description includes inserting a subsequent set of data in a linked-list data structure within an initial data structure. The linked-list data structure includes a sequence of linked-list entries interspersed with the initial data of the initial data structure. To insert the subsequent data, a pattern of data within the initial data structure is replaced with data of the subsequent set of data in a sequence of linked-list entries of the linked-list data structure. Other aspects are described herein.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: December 10, 2019
    Assignee: INTEL IP CORPORATION
    Inventor: Jens H. Jensen
  • Patent number: 10484018
    Abstract: In one embodiment, a method includes writing data to a storage medium, via a write channel, by applying a partial reverse concatenated modulation code to the data prior to storing encoded data to the storage medium. The applying the partial reverse concatenated modulation code to the data includes application of a C2 encoding scheme to the data to produce C2-encoded data prior to application of one or more modulation encoding schemes to the C2-encoded data to produce modulated data, followed by application of a C1 encoding scheme to the modulated data subsequent to the application of the one or more modulation encoding schemes to produce the encoded data.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: November 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Roy D. Cideciyan, Robert A. Hutchins, Thomas Mittelholzer, Sedat Oelcer
  • Patent number: 10484017
    Abstract: A data processing apparatus and method with efficient decoding of an LDPC code under bit interleave processing is disclosed. In one example, a data processing apparatus includes a parallel demapping portion configured to obtain a second data stream by executing in parallel demapping processing corresponding to mapping on a transmission side for a first data stream as an object of processing. The apparatus also includes a bit interleave reverse processing portion configured to obtain a third data stream by executing in parallel bit interleave reverse processing corresponding to bit interleave on the transmission side for the second data stream, and an LDPC decoding portion configured to decode the third data stream which is inputted in parallel with a bit group as a unit. The present disclosure, for example, can be applied to a receiving apparatus for a digital broadcasting.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: November 19, 2019
    Assignee: Sony Corporation
    Inventor: Makiko Yamamoto
  • Patent number: 10447308
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: October 15, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Bo-Mi Lim, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • Patent number: 10439761
    Abstract: Embodiments of a method and a device are disclosed. In an embodiment, a method for performing physical layer operations in a point-to-point network is disclosed. The method involves receiving, from a link in the communications network, information in an operations, administration, and management (OAM) word, setting an interleaving level, L, in response to the information received in the OAM word, inserting an OAM word into a forward error correction (FEC) frame, the OAM word including the set interleaving level (L), and transmitting, onto the link in the communications network, the FEC frame, which includes the OAM word.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: October 8, 2019
    Assignee: NXP B.V.
    Inventor: Sujan Pandey
  • Patent number: 10372527
    Abstract: Techniques for encoding data are described herein. The method includes receiving a block payload at a physical layer to be transmitted via a data bus. The method includes establishing a block header comprising an arrangement of bits, the block header defining two block header types, wherein a hamming distance between block header types is at least four.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: August 6, 2019
    Assignee: Intel Corporation
    Inventors: Huimin Chen, Andrew Martwick, Howard Heck, Robert Dunstan, Dennis Bell, Abdul Hawk Ismail
  • Patent number: 10334081
    Abstract: An apparatus is provided. The apparatus comprises a processing system comprising: an ARINC 429 converter system; an Internet protocol (IP) suite; and an Ethernet driver; wherein the processing system is configured to be coupled to a communications management system and at least one IP radio; wherein the processing system converts data, from the communications management system, from an ARINC 429 protocol into a transport layer protocol, an IP and a Ethernet protocol; and wherein the processing system converts data, from the IP radio, from the Ethernet protocol, IP, and transport layer protocol to the ARINC 429 protocol.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: June 25, 2019
    Assignee: Honeywell International, Inc.
    Inventors: Yufeng Liu, Thomas D. Judd, Likun Zou, Michael L. Olive
  • Patent number: 10277279
    Abstract: A communication system that uses keyed modulation to encode fixed frequency communications on a variable frequency power transmission signal in which a single communication bit is represented by a plurality of modulations. To provide a fixed communication rate, the number of modulations associated with each bit is dynamic varying as a function of the ratio of the communication frequency to the carrier signal frequency. In one embodiment, the present invention provides dynamic phase-shift-keyed modulation in which communications are generated by toggling a load at a rate that is a fraction of the power transfer frequency. In another embodiment, the present invention provides communication by toggling a load in the communication transmitter at a rate that is phase locked and at a harmonic of the power transfer frequency. In yet another embodiment, the present invention provides frequency-shift-keyed modulation, including, for example, modulation at one of two different frequencies.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: April 30, 2019
    Assignee: PHILIPS IP VENTURES B.V.
    Inventors: Matthew J. Norconk, Joshua K. Schwannecke, Colin J. Moore, Joshua B. Taylor, Neil W. Kuyvenhoven, Dale R. Liff, Jason L. Amistadi, Robert D. Gruich, Arthur Kelley, Kenneth C. Armstrong
  • Patent number: 10270559
    Abstract: Various embodiments disclosed herein provide for a transmitter that can adjust the size of an information block or segment the information block based on a forward error correction (FEC) code optimum efficiency. Certain FEC codes are more efficient at encoding and decoding longer information blocks and if an information block is shorter than a predetermined length, the transmitter can pad the information block with a group of null bits to lengthen the information block to increase the performance of encoding and decoding the information block. In some embodiments, the transmitter can segment the information block into a set of segments, and if the last segment is below the predetermined length, the transmitter can pad the last segment.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: April 23, 2019
    Assignee: AT&T INTELLECTUAL PROPERTY I, L.P.
    Inventors: SaiRamesh Nammi, Xiaoyi Wang, Arunabha Ghosh
  • Patent number: 10254340
    Abstract: Embodiments are directed to a semiconductor wafer having on-wafer circuitry. The on-wafer circuitry includes functional circuitry and first drive circuitry communicatively coupled to the functional circuitry. The on-wafer circuitry further includes test-only circuitry communicatively coupled to the functional circuitry, along with second drive circuitry communicatively coupled to the test-only circuitry. The control circuitry is communicatively coupled to the second drive circuitry and the test-only circuitry, wherein the first drive circuitry is configured to drive the functional circuitry in a first manner, and wherein the control circuitry is configured to control the second drive circuitry to drive the test-only circuitry in a second manner that is independent of the first manner.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: April 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John B. DeForge, Terence B. Hook, Theresa A. Newton, Kirk D. Peterson
  • Patent number: 10218823
    Abstract: A node configured to support multi-service with Flexible Ethernet (FlexE) includes circuitry configured to receive a client signal, wherein the client signal is different from a FlexE client; and circuitry configured to map the client signal into a FlexE shim. A method, implemented in a node, for supporting multi-service with Flexible Ethernet (FlexE) includes receiving a client signal, wherein the client signal is different from a FlexE client; and mapping the client signal into a FlexE shim.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: February 26, 2019
    Assignee: Ciena Corporation
    Inventor: Sebastien Gareau
  • Patent number: 10200149
    Abstract: A super-frame for transmission in an optical communications system comprises two or more data frames and a parity frame. All frames in the super-frame have been encoded in accordance with a first Forward Error Correction (FEC) scheme. The parity frame is computed over the two or more data frames (prior to or concurrently with or after encoding via the first FEC scheme) according to a second FEC scheme. At a receiver, the super-frame is decoded in accordance with the first FEC scheme to generate a set of FEC decoded frames in which residual errors are clustered, that is, are non-Poisson. The second FEC scheme, which is particularly suited or designed to correct the clustered non-Poisson residual errors, is used to correct the residual errors.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: February 5, 2019
    Assignee: Ciena Corporation
    Inventors: Kim B. Roberts, Amir K. Khandani
  • Patent number: 10164664
    Abstract: A method for performing time and cell de-interleaving on an interleaved signal including a plurality of cells is provided. The method includes: providing a first memory for storing the cells, the first memory written and read each time in a unit of one cell group, the cell group including K cells, where K is a positive integer greater than 1; providing a second memory for storing the cells read from the first memory; reading the cells from the first memory, and writing the cells to the second memory according to a writing rule of a plurality of permutation rules, K consecutive cells written to the second memory being from the same cell group; and reading the cells from the second memory according to a reading rule of the permutation rules, to cause the cells read from the second memory to be complete with time de-interleaving and cell de-interleaving.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: December 25, 2018
    Assignee: MSTAR SEMICONDUCTOR, INC.
    Inventor: Chun-Chieh Wang
  • Patent number: 10162701
    Abstract: An apparatus having a microcontroller includes a processing unit, an internal communication bus assembly, a volatile memory, a non-volatile memory, a logic error management circuit, and two interface circuits. A first interface circuit couples the processing unit to the volatile memory via the internal communication bus assembly. A second interface circuit couples the processing unit to the non-volatile memory via the internal communication bus assembly. When the microcontroller is operating, the interface circuits are arranged to retrieve and evaluate requested data from their respective memory without intervention from the processing unit. In the event a failure is detected, the logic error management circuit is arranged to assert a stop signal. In some cases, detecting a failure includes comparing a check value stored in memory with a check value calculated from the data retrieved from memory.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: December 25, 2018
    Assignee: STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Vincent Onde, Dragos Davidescu
  • Patent number: 10122495
    Abstract: Techniques are disclosed relating to circuitry configured to interleave data, e.g., for use to process error correcting codes for wireless data transmission. In some embodiments an apparatus includes one or more circuit elements configured to receive input data samples, a plurality of polynomial coefficients, a start index, and information indicating a window size for non-sequential traversal of interleaver indices. The polynomial coefficients may include coefficients for at least a third-order polynomial. In some embodiments, the one or more circuit elements are further configured to generate interleaved bank and address information for writing the input data samples to the plurality of memory blocks, based on an order of the polynomial, a code block length, the start index, and the information indicating the window size. In some embodiments, the apparatus also includes output circuitry configured to provide interleaved data samples from the memory blocks.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: November 6, 2018
    Assignee: NATIONAL INSTRUMENTS CORPORATION
    Inventors: Matthias Henker, Tim Taubert, Clemens Michalke
  • Patent number: 10102064
    Abstract: A memory device includes one or more memory arrays and a quad bit error correction circuit. The quad bit error correction circuit may include a first layer error correction circuit and a second layer error correction circuit. The first layer error correction circuit may be configured to generate a Hamming correction bit vector, and the second layer error correction circuit may be configured to generate a Golay correction bit vector. The Hamming correction bit vector and the Golay correction bit vector may be used to identify up to four correctable bit errors in data to be stored in the one more memory arrays.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: October 16, 2018
    Assignee: Everspin Technologies, Inc.
    Inventor: Kurt Baty
  • Patent number: 10097205
    Abstract: In a transmission device, a determining unit determines, for use in transmission, an LDPC encoding method corresponding to occurrence conditions of external noise from a plurality of LDPC encoding methods each having the same code length and the same code rate and being defined by a different parity check matrix, and an encoding unit generates a codeword bit sequence by encoding transmission data using the LDPC encoding method determined by the determining unit.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: October 9, 2018
    Assignee: SUN PATENT TRUST
    Inventor: Shutai Okamura
  • Patent number: 10069516
    Abstract: A communication device includes a barrel shifter shifting an information sequence according to a code word number; an error correction coding circuit encoding the shifted information sequence to generate a code word; and a transmitter transmitting a frame with N rows and M columns in the order of the row numbers. One code word is disposed in a row of the frame. The row number of the frame corresponds to the code word number. When a code word number is N, the error correction coding circuit encodes an information sequence of a second size smaller than the first size and fixed data of a third size, which is the difference between the first size and the second size, and disposes them in a row of the frame such that the error correction parity follows the information sequence of the second size and the fixed data follows the error correction parity.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: September 4, 2018
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Yoshiaki Konishi
  • Patent number: 10031880
    Abstract: The application provides a network device, which includes: a main control board and a service board, where the main control board includes a processor and a switching chip, and the service board includes a physical layer component. The switching chip is connected to the physical layer component by using a system bus. The system bus consists of a SerDes link, and is configured to transmit service data and control information of a port of the physical layer component. The processor controls the port of the physical layer component by using the control information of the port of the physical layer component. The network device transmits the service data and the control information by using the system bus, so that the service board does not need to set a CPU processing the control information, thereby expanding an interface flexibly, and reducing device complexity and hardware costs.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: July 24, 2018
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Jianzhao Li, Lu Cao
  • Patent number: 9996755
    Abstract: A method and an image processing apparatus for image-based object feature description are provided. In the method, an object of interest in an input image is detected and a centroid and a direction angle of the object of interest are calculated. Next, a contour of the object of interest is recognized and a distance and a relative angle of each pixel on the contour to the centroid are calculated, in which the relative angle of each pixel is calibrated by using the direction angle. Then, a 360-degree range centered on the centroid is equally divided into multiple angle intervals and the pixels on the contour are separated into multiple groups according to a range covered by each angle interval. Afterwards, a maximum among the distances of the pixels in each group is obtained and used as a feature value of the group. Finally, the feature values of the groups are normalized and collected to form a feature vector that serves as a feature descriptor of the object of interest.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: June 12, 2018
    Assignee: TAMKANG UNIVERSITY
    Inventors: Chi-Yi Tsai, Hsien-Chen Liao
  • Patent number: 9961674
    Abstract: A method and a radio base station for interleaving control channel data to be transmitted in a telecommunications system are described. The method comprises grouping the control channel elements CCE1-CCEn into a first order of control channel symbol groups, adding symbol groups comprising dummy values or zeros to the first order of control channel symbol groups based on a number of available symbol group positions for the shared control channel, interleaving the first order of the control channel symbol groups resulting in an a second order, and mapping the second order of control channel symbol groups to the available control channel transmission resources.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: May 1, 2018
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Karl J. Molnar, Jung-Fu Cheng, Stefan Parkvall
  • Patent number: 9953003
    Abstract: A data processing system is disclosed that includes machines having an in-line accelerator and a general purpose instruction-based general purpose instruction-based processor. In one example, a machine comprises storage to store data and an Input/output (I/O) processing unit coupled to the storage. The I/O processing unit includes an in-line accelerator that is configured for in-line stream processing of distributed multi stage dataflow based computations. For a first stage of operations, the in-line accelerator is configured to read data from the storage, to perform computations on the data, and to shuffle a result of the computations to generate a first set of shuffled data. The in-line accelerator performs the first stage of operations with buffer less computations.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: April 24, 2018
    Assignee: BigStream Solutions, Inc.
    Inventor: Maysam Lavasani
  • Patent number: 9910623
    Abstract: Storage devices and components, including memory components (e.g., non-volatile memory) can be trained by executable code that facilitates and/or performs reads and/or write requests to one or more storage sub-modules of a storage component (e.g., memory configured on a memory channel) made up of multiple storage components (e.g., DIMMs). The executable code can also train multiple storage components at the same time and/or in parallel.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: March 6, 2018
    Assignee: Teradata US, Inc.
    Inventors: Liuxi Yang, Jeremy L. Branscome
  • Patent number: 9892479
    Abstract: A system for monitoring graphics processing units, including an image merge element; a database memory, operatively connected to the image merge element; and, a comparator element. The image merge element is configured to: i) receive visible image data from a graphics processing unit (GPU); ii) extract a symbol identifier; iii) receive a mask; and, iv) calculate a cyclic redundancy check (CRC) of a masked portion of the visible image data corresponding to the mask. The database memory is operatively connected to the image merge element. The database memory includes: a mask database including lookup tables of masks for defined areas of the visible image data indexed by the extracted symbol identifier; and, a CRC signature database including a table of valid CRCs for the image data indexed by the extracted symbol identifier.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: February 13, 2018
    Assignee: ROCKWELL COLLINS, INC
    Inventor: James S. Pruitt
  • Patent number: 9875156
    Abstract: A data storage device includes a set of latches, read/write circuitry, a memory, and an interleaver. The set of latches is configured to receive data. The read/write circuitry is coupled to the set of latches. The memory is coupled to the read/write circuitry. The interleaver is configured to interleave the data and to cause the read/write circuitry to program the interleaved data to the memory. The set of latches, the read/write circuitry, the memory, and the interleaver are integrated within a common die.
    Type: Grant
    Filed: October 1, 2015
    Date of Patent: January 23, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Eran Sharon, Ariel Navon, Alexander Tsang-Nam Chu, Wanfang Tsai, Idan Alrod
  • Patent number: 9787431
    Abstract: There are various drawbacks by using existing OTN (Optical Transport Network) frames for communication between OTN cards. Such drawbacks might for example include high latency, low robustness, and/or high coding rate. According to embodiments of the present disclosure, systems and methods are provided for modifying an OTN frame (or creating a new frame with data from the OTN frame) prior to transmission by an OTL (Optical channel Transport Lane) in order to address some or all of the foregoing drawbacks. Note that this embodiment can make use of existing hardware (e.g. hardware used for generating the OTN frame, and the OTL used for transmission).
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: October 10, 2017
    Assignee: INPHI CORPORATION
    Inventors: Juan-Carlos Calderon, Jean-Michel Caia, Arash Farhoodfar, Arun Zarabi
  • Patent number: 9715475
    Abstract: A data processing system is disclosed that includes machines having an in-line accelerator and a general purpose instruction-based general purpose instruction-based processor. In one example, a machine comprises storage to store data and an Input/output (I/O) processing unit coupled to the storage. The I/O processing unit includes an in-line accelerator that is configured for in-line stream processing of distributed multi stage dataflow based computations. For a first stage of operations, the in-line accelerator is configured to read data from the storage, to perform computations on the data, and to shuffle a result of the computations to generate a first set of shuffled data. The in-line accelerator performs the first stage of operations with buffer less computations.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: July 25, 2017
    Assignee: BIGSTREAM SOLUTIONS, INC.
    Inventor: Maysam Lavasani
  • Patent number: 9654147
    Abstract: A concatenated error correction device may be provided that includes: a first encoder which encodes a plurality of blocks arranged in a column direction and a row direction into a block-wise product code consisting of column codes and row codes by applying a first error correction code to the blocks in each of the column direction and the row direction; and a second encoder which receives K number of source symbols and applies a second error correction code to the source symbols, and then encodes into N number of symbols including N-K number of parity symbols. The N number of symbols form the plurality of blocks. K and N are natural numbers.
    Type: Grant
    Filed: November 27, 2014
    Date of Patent: May 16, 2017
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Jaekyun Moon, Geunyeong Yu