Data Formatting To Improve Error Detection Correction Capability Patents (Class 714/701)
  • Patent number: 11513894
    Abstract: Various implementations described herein relate to systems and methods for decoding data stored in a non-volatile storage device, including determining error candidates and determining whether at least one first error candidate from the error candidates is found based on two of the component codes agreeing on a same error candidate. In addition, whether at least one second error candidate is found based on two of the component codes agreeing on a same error candidate is determined in response to implementing a suggested correction at one of the error candidates. Errors in the data are corrected based on at least one of whether the at least one first error candidate is found or whether the at least one second error candidate is found.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: November 29, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Avi Steiner, Amir Nassie, Anat Rot, Ofir Kanter, Hanan Weingarten
  • Patent number: 11487628
    Abstract: Systems for rapidly transferring and, as needed, recovering large data sets and methods for making and using the same. In various embodiments, the system advantageously can allow data to be transferred in larger sizes, wherein data may be easily recovered from multiple regions and wherein latency is no longer an issue, among other things.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: November 1, 2022
    Assignee: R-Stor Inc.
    Inventors: John Edward Gerard Matze, Anthony P. Gaughan, Damian Kowalewski
  • Patent number: 11451245
    Abstract: Aspects of the disclosure relate to wireless communication devices configured to encode information blocks to produce code blocks and interleave the code blocks utilizing an interleaver including a plurality of rows and a plurality of columns. In some examples, the interleaver includes a right isosceles triangle-shaped matrix of rows and columns. In other examples, the interleaver includes a rectangle-shaped matrix of rows and columns.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: September 20, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Jian Li, Changlong Xu, Jing Jiang, Hao Xu, Jilei Hou
  • Patent number: 11431441
    Abstract: Systems, methods, and instrumentalities are disclosed for priority-based channel coding for control information. A wireless transmit/receive unit (WTRU) may sort control information associated with a first control information type into a first control information group and the control information associated with a second control information type into a second control information group, for example, based on respective priorities associated with the first and second control information types. The WTRU may group one or more bits of the first control information group into a first bit level control information group and a second bit level control information group based on priority. The WTRU may selectively apply a cyclic redundancy check (CRC) to the first control information group, the second control information group, the first bit level control information group, and/or the second bit level control information group.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: August 30, 2022
    Assignee: IDAC Holdings, Inc.
    Inventors: Kyle Jung-Lin Pan, Fengjun Xi, Chunxuan Ye
  • Patent number: 11412263
    Abstract: Arithmetic coders such as CABAC have high complexity. Some video coding systems limit the ratio of bins coded by the arithmetic coder to bits of encoded data. In order to do so, extra padding or stuffing data is added to the bitstream. Embodiments include ways order to reduce the overhead of such padding, embodiments include ways of processing a video bitstream without including the padding data. For example a video encoder or decoder may code a syntax element of the video bitstream for a unit of video data that indicates a number of padding bits and code the unit of video data without coding (encoding or decoding) the padding bits in the video bitstream.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: August 9, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Muhammed Zeyd Coban, Adarsh Krishnan Ramasubramonian, Vadim Seregin, Marta Karczewicz
  • Patent number: 11404136
    Abstract: Symbols interleaved among a set of codewords can provide an error correction/detection capability to a dual in-line memory module (DIMM) with memory chips having a comparatively larger bus width. Data corresponding to a set of multibit symbols and received from one or more memory devices can be interleaved/distributed with other bits of at least one codeword.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: August 2, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Amato, Marco Sforzin, Stephen S. Pawlowski
  • Patent number: 11374697
    Abstract: A feedback method, an apparatus, and a system, which relate to the field of communications technologies. The method includes: a terminal device receiving configuration information sent by a network device, where the configuration information is used to indicate K time sequence relationships, the K time sequence relationships are respectively used for HARQ feedback on K downlink frequency domain resources, and K is a positive integer greater than or equal to 2; and the terminal device sending HARQ feedback information to the network device, where a quantity of downlink control channel monitoring occasions corresponding to the HARQ feedback information is determined based on the K time sequence relationships. According to the foregoing solution, the network device and the terminal device have a unified understanding on the HARQ feedback information. In this way, system robustness is improved.
    Type: Grant
    Filed: July 7, 2020
    Date of Patent: June 28, 2022
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yibin Zhuo, Jinlin Peng
  • Patent number: 11368164
    Abstract: An interleaver for combining at least two incoming signals into an analog output signal includes at least a first signal path and a second signal path. Each signal path has: an input terminal, a first gain stage for multiplying a signal coming from the input terminal with a first gain (a) to obtain a first signal, a mixer and a second gain stage for multiplying a signal coming from the input terminal with a second gain (b) before or after mixing it with a clock signal to obtain a second signal, an adder for adding the first and second signal to obtain an output signal of the signal path wherein the first and second gain are different from zero. The interleaver comprises an adder for adding the output signals from the signal paths.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: June 21, 2022
    Assignees: UNIVERSITEIT GENT, IMEC VZW
    Inventors: Guy Torfs, Hannes Ramon, Xin Yin
  • Patent number: 11347407
    Abstract: Drive health information is collected for each one of the data storage drives in one or more RAID groups of data storage drives, and is used to calculate a faultiness level of each data storage drive in the RAID group(s). A suitable RAID level for configuration of at least one RAID group may be generated based on the faultiness levels of the data storage drives contained in the RAID group. A faultiness-balanced distribution of the data storage drives across multiple RAID groups may be generated based on the faultiness levels of individual data storage drives. The data storage drives may be automatically redistributed across the multiple RAID groups according to the faultiness-balanced distribution of the data storage drives.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: May 31, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Nickolay Dalmatov, Mikhail Danilov
  • Patent number: 11303304
    Abstract: A receiver is arranged for receiving a signal comprising an interleaved symbol stream. The receiver comprises a convolutional deinterleaver comprising a plurality of delay portions each of which is arranged to delay symbols from the symbol stream from an input to an output by a different amount, the delay portions being arranged in a sequence. An input selector is configured to input the symbols from the symbol stream to the delay portions so that successive symbols are input in accordance with the sequence of the delay portions. An output selector configured to read the symbols from the delay portions by successively selecting the symbols from the outputs of the delay portions in accordance with the sequence of the delay portions to form a deinterleaved symbol stream.
    Type: Grant
    Filed: November 23, 2018
    Date of Patent: April 12, 2022
    Assignee: SATURN LICENSING LLC
    Inventor: Matthew Paul Athol Taylor
  • Patent number: 11290620
    Abstract: A system includes a processor and a memory. The memory stores instructions executable by the processor to receive first and second media units with respective first and second time stamps that are assigned based on a first clock cycle time and a data transmission rate, and to assign an adjusted time stamp to the second media unit based on the first clock cycle time, a second clock cycle time, the first time stamp, and the data transmission rate.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: March 29, 2022
    Assignee: Sling Media Pvt. Ltd.
    Inventor: Amit Kumar
  • Patent number: 11277151
    Abstract: Aspects of the present disclosure relate to low density parity check (LDPC) coding utilizing LDPC base graphs. Two or more LDPC base graphs may be maintained that are associated with different ranges of overlapping information block lengths. A particular LDPC base graph may be selected for an information block based on the information block length of the information block. Additional metrics that may be considered when selecting the LDPC base graph may include the code rate utilized to encode the information block and/or the lift size applied to each LDPC base graph to produce the information block length of the information block.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: March 15, 2022
    Assignee: Qualcomm Incorporated
    Inventors: Joseph Binamira Soriaga, Gabi Sarkis, Shrinivas Kudekar, Thomas Richardson, Vincent Loncke
  • Patent number: 11249844
    Abstract: A memory system includes: an error correction code generation circuit suitable for generating an error correction code including one or more symbols for write data including a plurality of symbols, to output a codeword including the write data and the error correction code; a first data mapping circuit suitable for mapping the symbols of the codeword to a dataword; and a memory suitable for storing the dataword.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: February 15, 2022
    Assignee: SK hynix Inc.
    Inventors: Young-Ook Song, Hyun-Seok Kim
  • Patent number: 11249837
    Abstract: A flit-based packetization approach is used for transmitting information between electronic components. A protocol stack can generate transaction layer packets from information received from a transmitting device, assemble the transaction layer packets into one or more flits, and protect the flits with a flit-level cyclic redundancy check (CRC) scheme and a flit-level forward error correction or parallel-forward error correction (FEC) scheme. Flit-level FEC schemes can provide improved latencies and efficiencies over per-lane FEC schemes. To improve retry probability, flits can contain information indicating whether immediately preceding flits are null flits. Receivers can avoid sending a retry request for a corrupted flit if a seceding flit indicates the corrupted flit is a null fit. Parity flits can be used to protect groups of flits and correct single-flit errors.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: February 15, 2022
    Assignee: Intel Corporation
    Inventor: Debendra Das Sharma
  • Patent number: 11212753
    Abstract: A method is disclosed for a wireless communication node configured for operation in accordance with a listen-before-talk (LBT) procedure. The method comprises—for an upcoming transmission—performing channel sensing to determine an interference level experienced by the wireless communication node, determining a maximum transmission power level for the upcoming transmission responsive to the determined interference level, and selecting at least one of a coding rate and a modulation to be used for the upcoming transmission responsive to the determined maximum transmission power level. According to some embodiments, the method further comprises preparing a plurality of transmission packet variants before performing the channel sensing, wherein each transmission packet variant is associated with a respective transmission power level.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: December 28, 2021
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (publ)
    Inventor: Leif Wilhelmsson
  • Patent number: 11184031
    Abstract: The interleaver 104 interleaves first to Nth code words. The OFDM modulation circuit 105 converts the interleaved first to Nth code words into OFDM signals. The transmission RF circuit 106 transmits the OFDM signals. The number of data symbols included in the first code word is less than the number of data symbols included in the second code word. The interleaver 104 writes the first code word to the Nth code word in ascending order and starts reading from the second code word.
    Type: Grant
    Filed: April 10, 2018
    Date of Patent: November 23, 2021
    Assignee: Panasonic Intellectual Property Corporation Of America
    Inventors: Hiroyuki Motozuka, Takenori Sakamoto
  • Patent number: 11153132
    Abstract: A device including an equalizer that includes a first input configured to receive an input signal, a second input configured to receive a reference signal, and a third input configured to receive an adjustment signal. The equalizer also includes a first output configured to transmit a corrected signal, wherein the corrected signal is generated based on data outputs controlled via the input signal, the reference signal, and a clock signal, wherein the data outputs are modified based on the first adjustment signal, wherein corrected signal offsets inter-symbol interference on the input signal based on a data bit received at the first input prior to reception of the input signal.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: October 19, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Jennifer E. Taylor, Raghukiran Sreeramaneni
  • Patent number: 11139918
    Abstract: Various embodiments provide an interleaving method, to improve error correction performance of a polar code. In these embodiments, a first bit sequence is obtained. The first bit sequence includes L number of bits, and L is a positive integer. The L number of bits are then written into an interleaving matrix according to a preset write rule. The interleaving matrix includes C rows and R number of columns. C and R are positive integers. The L number of bits can be read from the interleaving matrix according to a preset read rule to obtain a second bit sequence. The second bit sequence includes L number of bits; and sending the second bit sequence.
    Type: Grant
    Filed: March 8, 2020
    Date of Patent: October 5, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yue Zhou, Guijie Wang, Rong Li, Yinggang Du
  • Patent number: 11062743
    Abstract: A system and method for providing a configurable timing control of a memory system is provided. One system has a first interface to receive a DIMM clock and configuration information, a second interface to a first data bus, and a third interface to a second data bus. The system further has flip-flops, a multiplexer coupled to the flip-flops, a first control block for controlling to hold an input data within the flip-flops, and a second control block for controlling a timing of an output data from the flip-flops via the multiplexer with a programmable delay. The input data is received via the second interface. The programmable delay is received via the first interface. The output data is sent out with the timing delay via the third interface.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: July 13, 2021
    Assignee: Rambus, Inc.
    Inventors: Michael L. Takefman, Maher Amer, Claus Reitlingshoefer, Riccardo Badalone
  • Patent number: 11063693
    Abstract: A loss correction encoding device having an improved capability of loss correction using LDPC-CC includes a rearranging unit that rearranges information data contained in n information packets according to the constraint length Kmax and the encoding rate (q?1)/q of a check polynomial of the loss correction code used in a loss correction encoding unit. Specifically, the rearranging unit rearranges the information data in such a way that continuous Kmax×(q?1) pieces of information data after rearrangement are contained in different information packets. The rearranging unit distributes the information data to information blocks from n information packets, where n satisfies the formula Kmax×(q?1)?n.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: July 13, 2021
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Yutaka Murakami, Shutai Okamura
  • Patent number: 11063666
    Abstract: A communication device includes an interleaving unit that determines an interleaving length of transmit data to be transmitted through free-space optical communication, and interleaves the transmit data based on the determined interleaving length, and a shaping unit that shapes the interleaved transmit data so as to make the interleaving length detectable on a receiving side of the free-space optical communication.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: July 13, 2021
    Assignee: SONY CORPORATION
    Inventor: Shinji Ohta
  • Patent number: 11036709
    Abstract: In a general aspect, a method includes inserting a record in a partitioned fact table of a star schema data mart. Inserting the record can include determining a first hash value from a first dimension value of the record and determining a first set of candidate partitions from the first hash value. The method can further include determining a second hash value from a second dimension value of the record and determining a second set of candidate partitions from the first hash value. The method can further include comparing the first set of candidate partitions with the second set of candidate partitions to determine a common partition and inserting the record into the common partition.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: June 15, 2021
    Assignee: SAP SE
    Inventor: Christian Bensberg
  • Patent number: 11012591
    Abstract: A method implemented on a computing device including at least one processor and a storage for synchronizing video transmission with physical layer. The method includes determining a first time point corresponding to a frame header of a video frame, determining a second time point corresponding to a frame header of a physical layer frame based at least in part on the first time point, and starting transmitting the video frame at the second time point.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: May 18, 2021
    Assignee: SZ DJI TECHNOLOGY CO., LTD.
    Inventor: Xiaodong Wang
  • Patent number: 11005818
    Abstract: Some embodiments described herein relate managing communications between an origin and a destination using end-user and/or administrator configurable virtual private network(s) (VPN(s)). A first VPN that defines a first data path between an origin and a destination can be defined at a first time. A second VPN that defines a second, different data path between the origin and the destination can defined at a second time. Each packet sent across the first VPN and each packet sent across the second VPN can follow the same data path for that VPN, such each packet can be sent across the first VPN or the second VPN in the order it was received, and the transition between the first VPN and the second VPN can be “seamless,” and communications between the origin and the destination are not disrupted between the first time period and the second time period.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: May 11, 2021
    Assignee: NetAbstraction, Inc.
    Inventor: Ira A. Hunt, IV
  • Patent number: 10997175
    Abstract: A method for performing row qualification in database table retrieval and join operations. This method, referred to as bulk qualification, evaluates conditions on multiple rows in a database table at the same time, providing more efficient utilization of memory bandwidth and CPU throughput.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: May 4, 2021
    Assignee: Teradata US, Inc.
    Inventors: Bhashyam Ramesh, Tirupathi Prabhu Bellapukonda, Mohan Kumar KJ, Vamshi Krishna Vangapalli
  • Patent number: 10985914
    Abstract: A key generation device includes a generation circuit, a concealment processing unit, and a cryptography processing unit. The generation circuit generates a value dependent on hardware. When acquiring a concealed cryptographic key, the concealment processing unit generates first data by performing a mask process to the concealed cryptographic key by using the value generated by the generation circuit, generates second data by decoding the first data by a first error correction decoding method, and generates a cryptographic key by decoding the second data by a second error correction decoding method. When acquiring the concealed cryptographic key and a plain text or an encrypted text, the cryptography processing unit acquires the cryptographic key corresponding to the concealed cryptographic key from the concealment processing unit, and encrypts the plain text or decrypts the encrypted text by using the cryptographic key.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: April 20, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Yasuo Noguchi, Takeshi Shimoyama
  • Patent number: 10890540
    Abstract: A method including selecting a shaped feature from a set of shaped features, each shaped feature of the set of shaped features having a set of points on a perimeter of the shape of the shaped feature, creating a plurality of shape context descriptors for the selected shaped feature, wherein each shape context descriptor provides an indication of a location in a shape context descriptor framework of a first focus point of the set of points in relation to a second point of the set of points, and identifying a shaped feature from the set of shaped features having a same or similar shape as the selected shaped feature based on data from the plurality of shape context descriptors.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: January 12, 2021
    Assignee: ASML Netherlands B.V.
    Inventors: Adrianus Cornelis Matheus Koopman, Scott Anderson Middlebrooks, Willem Marie Julia Marcel Coene
  • Patent number: 10848224
    Abstract: A method and an apparatus for reporting channel state information (CSI) by a user equipment in a wireless communication system. According to the present invention, the UE receives configuration information related to reporting of the CSI from a base station, wherein the configuration information may include a threshold value related to a specific condition for receiving the CSI and the CSI may comprise a first part and a second part. A method and an apparatus may be provided in which the UE receives a first reference signal for channel measurement from the base station, measures a channel based on the first reference signal, and reports the CSI of the measured channel to the base station and some or all of the second part of the CSI is omitted.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: November 24, 2020
    Assignee: LG Electronics Inc.
    Inventors: Haewook Park, Kijun Kim, Jiwon Kang
  • Patent number: 10831596
    Abstract: A first tier of error correcting code operations on a data block may be performed. The first tier of error correcting code operations on the data block may be determined to be associated with an unsuccessful correction of an error of the data block. Responsive to determining that the first tier of error correcting code operations on the data block are associated with the unsuccessful correction of the error of the data block, a remix operation on the data block to change a logical to physical association of the data block from a first logical association to a second logical association may be performed.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: November 10, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Samuel E. Bradshaw
  • Patent number: 10790855
    Abstract: Field error correction coding is particularly suitable for applications in non-volatile flash memories. We describe a method for error correction encoding of data to be stored in a memory device, a corresponding method for decoding a codeword matrix resulting from the encoding method, a coding device, and a computer program for performing the methods on the coding device, using a new construction for high-rate generalized concatenated (GC) codes. The codes, which are well suited for error correction in flash memories for high reliability data storage, are constructed from inner nested binary Bose-Chaudhuri-Hocquenghem (BCH) codes and outer codes, preferably Reed-Solomon (RS) codes. For the inner codes extended BCH codes are used, where only single parity-check codes are applied in the first level of the GC code. This enables high-rate codes.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: September 29, 2020
    Assignee: HYPERSTONE GMBH
    Inventors: Juergen Freudenberger, Jens Spinner, Christoph Baumhof
  • Patent number: 10778253
    Abstract: An embodiment method includes: performing balancing processing on a data stream that includes a plurality of sub-data stream segments, and performing segment de-interleaving on a data stream obtained after the balancing processing. The method further includes separately performing forward error correction (FEC) decoding on each sub-data stream segment in a data stream obtained after the segment de-interleaving. The method further includes performing, according to a balancing termination state of each sub-data stream segment obtained after previous balancing processing, balancing processing on each sub-data stream segment obtained after the FEC decoding, and performing FEC decoding on the data stream obtained after balancing processing is performed on each sub-data stream segment. When it is determined that a preset iteration termination condition is met, the method includes outputting the data stream obtained after the FEC decoding.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: September 15, 2020
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Zhiyu Xiao, Ling Liu, Liangchuan Li
  • Patent number: 10769012
    Abstract: The present invention relates to a memory with error correction function, comprising a data array, an ECC array, a flag bit array, an ECC encoding module, an ECC decoding module, a flag bit generation module and a flag bit detection module; wherein: the flag bit generation module is configured, when data is being written, to generate a flag bit and an encode enable signal, the flag bit being stored in the flag bit array, and the encode enable signal being used to control the operation of the ECC encoding module; the ECC encoding module is configured to encode the data to be written according to the ECC algorithm preset therein so as to generate parity bits; the ECC array is configured to store the generated parity bits; the flag bit detection module is configured, when data is being read, to detect the flag bit and control the operation of the ECC decoding module; and the ECC decoding module is configured to detect and correct erroneous data using the parity bits from the ECC array and the data from the data
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: September 8, 2020
    Assignee: XI'AN UNIIC SEMICONDUCTORS CO., LTD.
    Inventor: Alessandro Minzoni
  • Patent number: 10749732
    Abstract: The present invention is directed to data communication. In certain embodiments, the present invention provides switching mechanism for choosing between redundant communication links. Data received from a first set of communication links are processed to have alignment markers removed, and first figure of merit value is determined based on the data without alignment markers. Similarly, a second figure of merit value is determined for the data received from the second set of communication links. A switch selects between the first set of communication links and the second set of communication links based on their respective figure of merit values. Alignment markers are inserted into the data transmitted through the selected set of data links. There are other embodiments as well.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: August 18, 2020
    Assignee: INPHI CORPORATION
    Inventors: Arash Farhoodfar, Jitendra Swarnkar, Michael Duckering, Andre Sczapanek, Scott Feller, Shaun Lytollis
  • Patent number: 10735136
    Abstract: Provided are a base station apparatus, a terminal apparatus and a communication method, capable of an efficient retransmission control of uplink data of which a resource for transmission is not discerned in grant-free multiple access. A terminal apparatus configured to communicate with a base station apparatus includes a transmitter configured to transmit an identifying signal indicating that the terminal apparatus itself transmits an uplink data channel and the uplink data channel. The uplink data channel includes an uplink data bit, a bit representing an identifier of the terminal apparatus, a first error detection bit generated from the uplink data bit, and a second error detection bit generated from the identifier of the terminal apparatus. The first error detection bit is scrambled using the identifier of the terminal apparatus, and the second error detection bit is scrambled using the identifying signal.
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: August 4, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Takashi Yoshimoto, Jungo Goto, Osamu Nakamura, Yasuhiro Hamaguchi
  • Patent number: 10721020
    Abstract: A super-frame for transmission in an optical communications system comprises two or more data frames and a parity frame. All frames in the super-frame have been encoded in accordance with a first Forward Error Correction (FEC) scheme. The parity frame is computed over the two or more data frames (prior to or concurrently with or after encoding via the first FEC scheme) according to a second FEC scheme. At a receiver, the super-frame is decoded in accordance with the first FEC scheme to generate a set of FEC decoded frames in which residual errors are clustered, that is, are non-Poisson. The second FEC scheme, which is particularly suited or designed to correct the clustered non-Poisson residual errors, is used to correct the residual errors.
    Type: Grant
    Filed: February 4, 2019
    Date of Patent: July 21, 2020
    Assignee: Ciena Corporation
    Inventors: Kim B. Roberts, Amir K. Khandani
  • Patent number: 10707902
    Abstract: A permutation network designing method and a permutation circuit using the same are provided. The method includes: identifying a predetermined check matrix of the QC-LDPC decoder, wherein the check matrix comprises M×N sub-matrices, wherein each of the sub-matrices is a Z×Z matrix, wherein Z is a default dimension value of each of the sub-matrices; constructing a second permutation network of a permutation circuit by removing a target first permutation layer from a first permutation layer according to a shift type of the check matrix, wherein the amount of a plurality of second permutation layers and the amount of the second nodes of each of the second permutation layers are set according to the default dimension value; and disposing a plurality of selectors on the second nodes of the constructed second permutation network of the permutation circuit.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: July 7, 2020
    Assignee: Shenzhen EpoStar Electronics Limited CO.
    Inventor: Yu-Hua Hsiao
  • Patent number: 10700708
    Abstract: A permutation network designing method and a permutation circuit using the same are provided. The method includes: identifying a predetermined check matrix of the QC-LDPC decoder, wherein the check matrix comprises M×N sub-matrices, wherein each of the sub-matrices is a Z×Z matrix, wherein Z is a default dimension value of each of the sub-matrices; constructing a permutation network of a permutation circuit according to the default dimension value and a saving parameter, wherein the permutation network comprises a plurality of permutation layers arranged sequentially, and each of the permutation layers has the same amount of nodes, wherein the amount of the permutation layers and the amount of the nodes of each of the permutation layers are set according to the default dimension value and a saving parameter; and disposing a plurality of selectors on the nodes of the permutation network of the permutation circuit.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: June 30, 2020
    Assignee: Shenzhen EpoStar Electronics Limited CO.
    Inventors: Yu-Hua Hsiao, Heng-Lin Yen
  • Patent number: 10579561
    Abstract: A communication interface couples a transmission circuit with an interconnection network. The transmission circuit requests transmission of a predetermined amount of data. The communication interface receives data segments from the transmission circuit, stores the data segments in a memory, and verifies whether the memory contains the predetermined amount of data. When the memory contains the predetermined amount of data, the communication interface starts transmission of the data stored in the memory. Alternatively, when the memory contains an amount of data less than the predetermined amount of data, the communication interface determines a parameter that identifies the time that has elapsed since the transmission request or the first datum was received from the aforesaid transmission circuit, and verifies whether the time elapsed exceeds a time threshold. In the case where the time elapsed exceeds the time threshold, the communication interface starts transmission of the data stored in the memory.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: March 3, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Daniele Mangano, Mirko Dondini, Salvatore Pisasale
  • Patent number: 10516650
    Abstract: Some embodiments described herein relate managing communications between an origin and a destination using end-user and/or administrator configurable virtual private network(s) (VPN(s)). A first VPN that defines a first data path between an origin and a destination can be defined at a first time. A second VPN that defines a second, different data path between the origin and the destination can defined at a second time. Each packet sent across the first VPN and each packet sent across the second VPN can follow the same data path for that VPN, such each packet can be sent across the first VPN or the second VPN in the order it was received, and the transition between the first VPN and the second VPN can be “seamless,” and communications between the origin and the destination are not disrupted between the first time period and the second time period.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: December 24, 2019
    Assignee: NETABSTRACTION, INC.
    Inventor: Ira A. Hunt, IV
  • Patent number: 10504608
    Abstract: In one embodiment, linked-list interlineation of data in accordance with the present description includes inserting a subsequent set of data in a linked-list data structure within an initial data structure. The linked-list data structure includes a sequence of linked-list entries interspersed with the initial data of the initial data structure. To insert the subsequent data, a pattern of data within the initial data structure is replaced with data of the subsequent set of data in a sequence of linked-list entries of the linked-list data structure. Other aspects are described herein.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: December 10, 2019
    Assignee: INTEL IP CORPORATION
    Inventor: Jens H. Jensen
  • Patent number: 10484018
    Abstract: In one embodiment, a method includes writing data to a storage medium, via a write channel, by applying a partial reverse concatenated modulation code to the data prior to storing encoded data to the storage medium. The applying the partial reverse concatenated modulation code to the data includes application of a C2 encoding scheme to the data to produce C2-encoded data prior to application of one or more modulation encoding schemes to the C2-encoded data to produce modulated data, followed by application of a C1 encoding scheme to the modulated data subsequent to the application of the one or more modulation encoding schemes to produce the encoded data.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: November 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Roy D. Cideciyan, Robert A. Hutchins, Thomas Mittelholzer, Sedat Oelcer
  • Patent number: 10484017
    Abstract: A data processing apparatus and method with efficient decoding of an LDPC code under bit interleave processing is disclosed. In one example, a data processing apparatus includes a parallel demapping portion configured to obtain a second data stream by executing in parallel demapping processing corresponding to mapping on a transmission side for a first data stream as an object of processing. The apparatus also includes a bit interleave reverse processing portion configured to obtain a third data stream by executing in parallel bit interleave reverse processing corresponding to bit interleave on the transmission side for the second data stream, and an LDPC decoding portion configured to decode the third data stream which is inputted in parallel with a bit group as a unit. The present disclosure, for example, can be applied to a receiving apparatus for a digital broadcasting.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: November 19, 2019
    Assignee: Sony Corporation
    Inventor: Makiko Yamamoto
  • Patent number: 10447308
    Abstract: A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: October 15, 2019
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sung-Ik Park, Sun-Hyoung Kwon, Bo-Mi Lim, Jae-Young Lee, Heung-Mook Kim, Nam-Ho Hur
  • Patent number: 10439761
    Abstract: Embodiments of a method and a device are disclosed. In an embodiment, a method for performing physical layer operations in a point-to-point network is disclosed. The method involves receiving, from a link in the communications network, information in an operations, administration, and management (OAM) word, setting an interleaving level, L, in response to the information received in the OAM word, inserting an OAM word into a forward error correction (FEC) frame, the OAM word including the set interleaving level (L), and transmitting, onto the link in the communications network, the FEC frame, which includes the OAM word.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: October 8, 2019
    Assignee: NXP B.V.
    Inventor: Sujan Pandey
  • Patent number: 10372527
    Abstract: Techniques for encoding data are described herein. The method includes receiving a block payload at a physical layer to be transmitted via a data bus. The method includes establishing a block header comprising an arrangement of bits, the block header defining two block header types, wherein a hamming distance between block header types is at least four.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: August 6, 2019
    Assignee: Intel Corporation
    Inventors: Huimin Chen, Andrew Martwick, Howard Heck, Robert Dunstan, Dennis Bell, Abdul Hawk Ismail
  • Patent number: 10334081
    Abstract: An apparatus is provided. The apparatus comprises a processing system comprising: an ARINC 429 converter system; an Internet protocol (IP) suite; and an Ethernet driver; wherein the processing system is configured to be coupled to a communications management system and at least one IP radio; wherein the processing system converts data, from the communications management system, from an ARINC 429 protocol into a transport layer protocol, an IP and a Ethernet protocol; and wherein the processing system converts data, from the IP radio, from the Ethernet protocol, IP, and transport layer protocol to the ARINC 429 protocol.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: June 25, 2019
    Assignee: Honeywell International, Inc.
    Inventors: Yufeng Liu, Thomas D. Judd, Likun Zou, Michael L. Olive
  • Patent number: 10277279
    Abstract: A communication system that uses keyed modulation to encode fixed frequency communications on a variable frequency power transmission signal in which a single communication bit is represented by a plurality of modulations. To provide a fixed communication rate, the number of modulations associated with each bit is dynamic varying as a function of the ratio of the communication frequency to the carrier signal frequency. In one embodiment, the present invention provides dynamic phase-shift-keyed modulation in which communications are generated by toggling a load at a rate that is a fraction of the power transfer frequency. In another embodiment, the present invention provides communication by toggling a load in the communication transmitter at a rate that is phase locked and at a harmonic of the power transfer frequency. In yet another embodiment, the present invention provides frequency-shift-keyed modulation, including, for example, modulation at one of two different frequencies.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: April 30, 2019
    Assignee: PHILIPS IP VENTURES B.V.
    Inventors: Matthew J. Norconk, Joshua K. Schwannecke, Colin J. Moore, Joshua B. Taylor, Neil W. Kuyvenhoven, Dale R. Liff, Jason L. Amistadi, Robert D. Gruich, Arthur Kelley, Kenneth C. Armstrong
  • Patent number: 10270559
    Abstract: Various embodiments disclosed herein provide for a transmitter that can adjust the size of an information block or segment the information block based on a forward error correction (FEC) code optimum efficiency. Certain FEC codes are more efficient at encoding and decoding longer information blocks and if an information block is shorter than a predetermined length, the transmitter can pad the information block with a group of null bits to lengthen the information block to increase the performance of encoding and decoding the information block. In some embodiments, the transmitter can segment the information block into a set of segments, and if the last segment is below the predetermined length, the transmitter can pad the last segment.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: April 23, 2019
    Assignee: AT&T INTELLECTUAL PROPERTY I, L.P.
    Inventors: SaiRamesh Nammi, Xiaoyi Wang, Arunabha Ghosh
  • Patent number: 10254340
    Abstract: Embodiments are directed to a semiconductor wafer having on-wafer circuitry. The on-wafer circuitry includes functional circuitry and first drive circuitry communicatively coupled to the functional circuitry. The on-wafer circuitry further includes test-only circuitry communicatively coupled to the functional circuitry, along with second drive circuitry communicatively coupled to the test-only circuitry. The control circuitry is communicatively coupled to the second drive circuitry and the test-only circuitry, wherein the first drive circuitry is configured to drive the functional circuitry in a first manner, and wherein the control circuitry is configured to control the second drive circuitry to drive the test-only circuitry in a second manner that is independent of the first manner.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: April 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John B. DeForge, Terence B. Hook, Theresa A. Newton, Kirk D. Peterson
  • Patent number: 10218823
    Abstract: A node configured to support multi-service with Flexible Ethernet (FlexE) includes circuitry configured to receive a client signal, wherein the client signal is different from a FlexE client; and circuitry configured to map the client signal into a FlexE shim. A method, implemented in a node, for supporting multi-service with Flexible Ethernet (FlexE) includes receiving a client signal, wherein the client signal is different from a FlexE client; and mapping the client signal into a FlexE shim.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: February 26, 2019
    Assignee: Ciena Corporation
    Inventor: Sebastien Gareau