Data Formatting To Improve Error Detection Correction Capability Patents (Class 714/701)
  • Patent number: 8359498
    Abstract: A method of communicating a bitstream having a characteristic Hamming weight to a destination via a channel comprises determining the characteristic Hamming weight of the bitstream, inverting each bit in the bitstream if the characteristic Hamming weight of the bitstream is below a threshold value and developing an indication of whether the bits in the bitstream are inverted, delivering the bitstream and the indication of whether the bits in the bitstream are inverted to the destination via the channel, and inverting each bit in the bitstream at the destination if the indication indicates that the bits are inverted.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: January 22, 2013
    Assignee: Marvell International Ltd.
    Inventors: Pantas Sutardja, Toai Doan
  • Patent number: 8359499
    Abstract: A method and apparatus for deinterleaving in a communication system is disclosed. The method and apparatus deinterleave data units using a data deinterleaver; compressed deinterleave input symbol quality information (SQI) units using a compressed deinterleaver, wherein at least one of the input SQI units deinterleaved by the compressed deinterleaver corresponds to at least one of the plurality of data units deinterleaved by the data deinterleaver; and apply the deinterleaved SQI units to the corresponding deinterleaved data units.
    Type: Grant
    Filed: October 9, 2009
    Date of Patent: January 22, 2013
    Assignee: CSR Technology Inc.
    Inventors: Sriram Mudulodu, Ping Dong, Jordan Christopher Cookman, Tao Yu
  • Patent number: 8352834
    Abstract: Systems and methods for performing high-speed multi-channel forward error correction using external DDR SDRAM is provided. According to one exemplary aspect, an interleaver/deinterleaver performs both read and write accesses to the DDR SDRAM that are burst-oriented by hiding active and precharge cycles in order to achieve high data rate operations. The interleaver/deinterleaver accesses data in the DDR SDRAM as read blocks and write blocks. Each block includes two data sequences. Each data sequence further includes a predetermined number of data words to be interleaved/deinterleaved. The PRECHARGE and ACTIVE command for one data sequence is issued when a preceding data sequence is being processed. Data in one read/write data sequence has the same row address within the same bank of the DDR SDRAM.
    Type: Grant
    Filed: January 5, 2010
    Date of Patent: January 8, 2013
    Assignee: BroadLogic Network Technologies Inc.
    Inventors: Binfan Liu, Junyi Xu
  • Patent number: 8352843
    Abstract: An apparatus for coding a communication signal is provided. The apparatus includes an encoder configured to encode the communication signal, to increase the length of the communication signal, and a repetition coder configured to repetitively code part of the encoded communication signal, to utilize at least some of the increased length of the communication signal. The apparatus further includes an interleaver configured to interleave the repetitively coded communication signal. A method is also provided for coding a communication signal.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: January 8, 2013
    Assignee: Qualcomm Incorporated
    Inventors: Rabih Chrabieh, Koorosh Akhavan
  • Patent number: 8351537
    Abstract: Methods and communication systems are presented, in which impulse noise is monitored on a communication channel, and an interleaver depth is adjusted according to the monitored impulse noise without interrupting communication service.
    Type: Grant
    Filed: March 25, 2009
    Date of Patent: January 8, 2013
    Assignee: Infineon Technologies AG
    Inventor: Bernd Heise
  • Patent number: 8352808
    Abstract: A data storage device receives write data and includes a controller configured to determine a characteristic of the write data and provide a first control signal in response to the determined characteristic, a randomizer configured to selectively randomize or not randomize the write data in response to the first control signal to thereby generate randomized write data, and a data storage unit configured to store the randomized write data.
    Type: Grant
    Filed: October 5, 2009
    Date of Patent: January 8, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong June Kim, Jun Jin Kong, Jae Hong Kim, Kyoung Lae Cho
  • Patent number: 8347196
    Abstract: An error coding circuit comprises a non-systematic convolutional encoder for coding an input bit stream to produce two or more groups of parity bits, an interleaver circuit for interleaving parity bits within each group of parity bits, and a rate-matching circuit for outputting a selected number of the interleaved parity bits ordered by group to obtain a desired code rate.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: January 1, 2013
    Assignee: Telefonaktiebolaget L M Ericsson (Publ)
    Inventor: Jung-Fu Thomas Cheng
  • Patent number: 8321725
    Abstract: A method of interleaving blocks of indexed data of varying length is disclosed. The method includes the steps of: providing a set of basic Interleavers comprising a family of one or more permutations of the indexed data and having a variable length; selecting one of the basic Interleavers based upon a desired Interleaver length L; and adapting the selected basic Interleaver to produce an Interleaver having the desired Interleaver length L.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: November 27, 2012
    Assignee: The DIRECTV Group, Inc.
    Inventors: Mustafa Eroz, A. Roger Hammons, Jr., Feng-Wen Sun
  • Patent number: 8312356
    Abstract: Systems and methods are disclosed for processing data. In one exemplary implementation, there is provided a method of generating H output data from W data input streams produced from input data. Moreover, the method may include generating the H discrete output data components via application of the W data inputs to one or more transforming components or processes having specified mathematic operations and/or a generator matrix functionality, wherein the W data inputs are recoverable via a recovery process capable of reproducing the W data inputs from a subset (any W members) of the H output data streams. Further exemplary implementations may comprise a transformation process that includes producing an H-sized intermediary for each of the W inputs, combining the H-sized intermediaries into an H-sized result, and processing the H-sized result into the H output data structures, groups or streams.
    Type: Grant
    Filed: October 29, 2009
    Date of Patent: November 13, 2012
    Inventor: Robert E. Cousins
  • Patent number: 8300244
    Abstract: Systems and methods for automatic discovery of a networked raster image process (RIP) engine are described. In one aspect, a device determines that an entity is searching for one or more RIP engines. Responsive to such determining, the device notifies the entity of its RIP engine status.
    Type: Grant
    Filed: April 16, 2003
    Date of Patent: October 30, 2012
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Robert Douglas Christiansen
  • Patent number: 8289999
    Abstract: A method of communicating individual packets i of K bits includes permutation mapping of the packets, with each permuted packet being denoted by ?n(i), wherein ?n is a permutation on K letters that is unique for each packet transmission. Each permuted packet ?n(i) is modulated to provide a complex vector x(?n(i)) for each packet. The packets are transmitted over a AWGN channel so each individual packet i is received as a variable of the vector x(?n(i)) in a complex vector yn=x(?n(i))+vn, wherein n represents the sequential number of the transmission attempt for a particular packet and vn represents noise. This method enables the packets to be transmitted while using an improved ARQ routine that includes soft-combining decisions and a constant constellation with a constellation complexity greater than two bits/symbol to thereby significantly improve ARQ-routine performance over the current state of the art.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: October 16, 2012
    Assignee: L-3 Services, Inc.
    Inventor: James Covosso Francis
  • Patent number: 8284873
    Abstract: A wireless communication receiver includes a first signal processing block, a second signal processing block, and a de-interleaver. The first signal processing block is configured for receiving a wireless communication signal and processing the wireless communication signal to generate a first output. The de-interleaver is coupled between the first signal processing block and the second signal processing block, and includes a plurality of branches implemented for de-interleaving the first output to generate a second output. The de-interleaver starts outputting the second output to the second signal processing block for further signal processing before all buffers included in the branches are full, and informs the second signal processing block of data derived from one or more unfull buffers included in the branches.
    Type: Grant
    Filed: April 7, 2009
    Date of Patent: October 9, 2012
    Assignee: Mediatek Inc.
    Inventor: Shun-An Yang
  • Patent number: 8281061
    Abstract: Methods and apparatus for managing data storage in memory devices utilizing memory arrays of varying density memory cells. Data can be initially stored in lower density memory. Data can be further read, compacted, conditioned and written to higher density memory as background operations. Methods of data conditioning to improve data reliability during storage to higher density memory and methods for managing data across multiple memory arrays are also disclosed.
    Type: Grant
    Filed: March 31, 2008
    Date of Patent: October 2, 2012
    Assignee: Micron Technology, Inc.
    Inventors: William H. Radke, Vishal Sarin, Jung-Sheng Hoei
  • Patent number: 8276025
    Abstract: An embodiment is a method and apparatus to interleave data. A demultiplexer demultiplexes an input packet having N bits into L sub-packets on L branches. M flipping blocks flip M of the L sub-packets. M is smaller than L. L sub-interleavers interleave the (L-M) sub-packets and the M flipped sub-packets. A concatenator concatenates the interleaved sub-packets to form an output packet.
    Type: Grant
    Filed: June 4, 2009
    Date of Patent: September 25, 2012
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Kaveh Razazian, Amir Hosein Kamalizad, Maher Umari
  • Patent number: 8270356
    Abstract: A wireless communication system and a terminal providing a wireless communication service and to a method by which a base station and a terminal transmit and receive data in an evolved universal mobile telecommunications system (E-UMTS) evolved from universal mobile telecommunications system (UMTS) or a long term evolution (LTE) system, are disclosed. In transmitting RACH MSG 3 by a terminal to a base station, the terminal transmits the RACH MSG 3 by applying different cyclic redundancy checks (CRCs) according to types of data included in the RACH MSG 3, to thereby reduce overhead of a medium access control protocol data unit (MAC PDU) included in the RACH MSG 3.
    Type: Grant
    Filed: January 22, 2009
    Date of Patent: September 18, 2012
    Assignee: LG Electronics Inc.
    Inventors: Sung-Duck Chun, Seung-June Yi, Sung-Jun Park, Young-Dae Lee
  • Patent number: 8266480
    Abstract: A physical coding sublayer (PCS) transmitter circuit generates a plurality of encoded symbols according to a transmission standard. A symbol skewer skews the plurality of encoded symbols within a symbol clock time. A physical coding sublayer (PCS) receiver core circuit decodes a plurality of symbols based on encoding parameters. The symbols are transmitted using the encoding parameters according to a transmission standard. The received symbols are skewed within a symbol clock time by respective skew intervals. A PCS receiver encoder generator generates the encoding parameters.
    Type: Grant
    Filed: October 20, 2009
    Date of Patent: September 11, 2012
    Assignee: Broadcom Corporation
    Inventor: John L. Creigh
  • Patent number: 8266508
    Abstract: An error coding circuit comprises a non-systematic convolutional encoder for coding an input bit stream to produce two or more groups of parity bits, an interleaver circuit for interleaving parity bits within each group of parity bits, and a rate-matching circuit for outputting a selected number of the interleaved parity bits ordered by group to obtain a desired code rate.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: September 11, 2012
    Assignee: Telefonaktiebolaget L M Ericsson (Publ)
    Inventor: Jung-Fu Thomas Cheng
  • Patent number: 8239710
    Abstract: A wireless communication method implemented in a communication system may include receiving a data sequence to be permuted, and obtaining information associated with the data sequence to be permuted, the information containing at least a length of the data sequence and a sampling spacing for permuting the data sequence. The method may also include identifying a first portion of the data sequence having a first number of adjacent data items, and a second portion of the data sequence having a second number of adjacent data items. The method may also include accessing the first number of data items from the first portion at the sampling spacing, and placing the accessed first number of data items into a predetermined number of sub-blocks included within a permuted data sequence to be generated based on the received data sequence.
    Type: Grant
    Filed: July 15, 2009
    Date of Patent: August 7, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Chia-Lung Tsai, Yu-Tao Hsieh, Jen-Yuan Hsu, Pang-An Ting
  • Patent number: 8239736
    Abstract: The present invention provides a method for enhancing reliability of information transmission by (a) establishing a matrix based on the length of bits of valid information in frame time slots; and creating a new matrix by presetting Error Correction Coding (ECC) for rows and columns of said matrix; (b) adopting the 1st Interleaving method to re-allocate bits which have been processed twice by using said ECC in said new matrix, to both ends of said frame time slots; and (c) adopting the 2nd Interleaving method to re-allocate the remaining bits in said new matrix to the middle of said frame time slots. After processed like this, the anti-interfering ability of the bits at both ends of TDMA frame time slot can be significantly enhanced, and the bit-error rate is decreased most, and all redundancy bits of Hamming codes can be arrayed at both ends of TDMA frame time slot.
    Type: Grant
    Filed: August 11, 2008
    Date of Patent: August 7, 2012
    Assignee: Shenzhen HYT Science & Technology Co., Ltd.
    Inventor: Liangde Zheng
  • Patent number: 8234557
    Abstract: A transmission device in a communication system where a systematic code obtained by systematic encoding of information bits into which dummy bits are inserted and by deletion of the dummy bits from the results of the systematic encoding is transmitted. The transmission device inserts dummy bits into information bits based on an interleaving pattern of an interleaving portion in a turbo encoder; performs systematic encoding of the information bits into which the dummy bits are inserted, and then deletes the dummy bits from the results of the systematic encoding to generate a systematic code; and transmits the systematic code. By considering the interleaving pattern, original bit positions, which, after interleaving, exists within the ranges of stipulated numbers of bits at the beginning and at the end, are determined in advance, and the dummy bit insertion portion executes control so as not to insert dummy bits into the original bit positions.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: July 31, 2012
    Assignee: Fujitsu Limited
    Inventors: Shunji Miyazaki, Kazuhisa Obuchi, Tetsuya Yano
  • Patent number: 8225148
    Abstract: The disclosed technology provides systems and methods for encoding data based on a run-length-limited code and an error correction code to provide codewords. The codewords include RLL-encoded data that are produced based on the RLL code, and parity information that are produced based on the error correction code. The parity information is interleaved among the RLL-encoded data. In one embodiment, the codeword is produced by separately producing the RLL-encoded data and the parity information, and interleaving the parity information among the RLL-encoded data. In one embodiment, the codeword is produced by producing the RLL-encoded data, and using erasure decoding to compute the parity information.
    Type: Grant
    Filed: May 20, 2011
    Date of Patent: July 17, 2012
    Assignee: Marvell World Trade Ltd.
    Inventors: Heng Tang, Gregory Burd, Zining Wu, Panu Chaichanavong
  • Patent number: 8225147
    Abstract: Method and apparatus for writing scrambled multi-value data to a physical media and for reading scrambled multi-value data from a physical media, are disclosed. The physical media can be an optical disk. The scrambling can be performed by a multi-valued LFSR scrambler and the descrambling can be performed by a multi-valued LFSR descrambler. Further, the multi-valued data that is scrambled can include synchronization data and/or user data. Error correction coding can be used during the writing process and processing to correct for errors can be used during the reading process. Also, methods and apparatus for synchronizing multi-valued data written to and read from physical media are disclosed. Multi-value correlation methods and apparatus are also disclosed.
    Type: Grant
    Filed: April 12, 2010
    Date of Patent: July 17, 2012
    Assignee: Ternarylogic LLC
    Inventor: Peter Lablans
  • Patent number: 8219872
    Abstract: An extended deinterleaver the extended deinterleaver being responsive to at least one input signal, comprised of codewords, and operative to generate a deinterleaved output signal. The extended deinterleaver comprising a storage space organized into B number of appended storage branches, at least one appended storage branch having a storage branch and at least one element N, the received codewords being deinterleaved and buffered by the extended deinterleaver prior to being provided to the variable iteration decoder. Each appended storage branch further having a length that is extended by the length of N, N being at least one element, wherein as a codeword is provided to the variable iteration decoder, other codewords are provided to subsequent appended storage branches, and further wherein each appended storage branch, indexed by ‘b’, has a length of Lb+N, wherein Lb is the length of the storage branch prior to appending N.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: July 10, 2012
    Assignee: CSR Technology Inc.
    Inventors: Jordan Christopher Cookman, Tao Yu, Ping Dong, Junjie Qu
  • Patent number: 8212693
    Abstract: A method, medium, and apparatus hierarchically coding/decoding audio data, such as bit sliced arithmetic coding (BSAC), such that payloads of audio data and extension data can be grouped and interleaved according to priority so that some groups of the payloads are dropped, and the remainder of groups are transmitted. Therefore, extension data that is more important than a top layer of audio data, in terms of reproducing of original sounds, can be transmitted with priority.
    Type: Grant
    Filed: October 12, 2006
    Date of Patent: July 3, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Junghoe Kim, Eunmi Oh
  • Patent number: 8214696
    Abstract: An apparatus and method for transmitting a signal using a bit grouping method in a wireless communication system is disclosed. Interleaved subblocks are maintained, and output bit sequences are modulated in due order after bit grouping and bit selection. The bit grouping method is advantageous in that bit reliability is uniformly distributed.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: July 3, 2012
    Assignee: LG Electronics Inc.
    Inventors: Seung Hyun Kang, Suk Woo Lee
  • Patent number: 8205123
    Abstract: In exemplary embodiments, a skewed interleaving function for iterative code systems is described. The skewed interleaving function provides a skewed row and column memory partition and a layered structure for re-arranging data samples read from, for example, a first channel detector. An iterative decoder, such as an iterative decoder based on a low-density parity-check code (LDPC), might employ an element to de-skew the data from the interleaved memory partition before performing iterative decoding of the data, and then re-skew the information before passing decoded samples to the de-interleaver. The de-interleaver re-arranges the iterative decoded data samples in accordance with an inverse of the interleaver function before passing the decoded data samples to, for example, a second channel detector.
    Type: Grant
    Filed: December 4, 2008
    Date of Patent: June 19, 2012
    Assignee: LSI Corporation
    Inventors: Shaohua Yang, Changyou Xu, Weijun Tan, Ching-Fu Wu, Yuan Xing Lee
  • Patent number: 8199867
    Abstract: Described is an apparatus for suppressing spurious spectral lines in a frame based bit-serial data stream, in which frames include payload data and frame markers. The apparatus includes means (16) for randomizing first frame marker elements (START) in a first position within each frame and means (18) for correlating second frame marker elements (STOP) in a second position within each frame with the randomized first frame marker element.
    Type: Grant
    Filed: October 14, 2005
    Date of Patent: June 12, 2012
    Assignee: Telefonaktiebolaget L M Ericsson (Publ)
    Inventors: Bengt Erik Jonsson, Per Lars Paul Ingelhag
  • Patent number: 8201030
    Abstract: A method and apparatus for parallel structured Latin square interleaving in a communication system are provided. The method includes dividing input information bits into sub-blocks according to a parallel processing order, generating a first Latin square matrix or a second Latin square matrix by comparing the parallel processing order with a predetermined threshold, and interleaving by reading out the information bits divided into the sub-blocks according to the generated Latin square matrix.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: June 12, 2012
    Assignees: Samsung Electronics Co., Ltd., Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Seul-Ki Bae, Seung-Hee Han, Jong-Hyeuk Lee, Hong-Yeop Song, Dae-Son Kim, Joon-Sung Kim
  • Patent number: 8201265
    Abstract: A method is disclosed for generating a read error during standard DVD disc manufacturing. The method generates a read error in an error correction code (ECC) block including a specific error generation data pattern, when main data of 2,048 bytes is generated using the specific error generation data pattern according to a DVD standard. The error-pattern original data is inserted into the main data that is scrambling based on a DVD standard. The scrambled data is recorded in data sectors. The scrambled data including an error pattern which causes a read error is consecutively recorded in the data sectors included in the ECC blocks, in a process in which the data sectors are grouped based on 16 units to form the ECC blocks.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: June 12, 2012
    Assignee: SETTEC, Inc.
    Inventor: Heung-Chan Seung
  • Patent number: 8201031
    Abstract: A system, method and node for unambiguous encoding of Physical Downlink Control Channel (PDCCH) channels in a Long Term Evolution (LTE) telecommunications system to remove detection errors. The method includes the step of modifying a size of a circular buffer by excluding at least one coded bit from the circular buffer. The circular buffer collects interleaved bits from a PDCCH payload having a plurality of bits. The PDCCH payload is encoded with a convolutional code. The bits of the PDCCH payload are then interleaved. The interleaved bits are collected into the modified circular buffer. The bits are then selected from the modified circular buffer for transmission.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: June 12, 2012
    Assignee: Telefonaktiebolaget L M Ericsson (Publ)
    Inventor: Jung-Fu Cheng
  • Patent number: 8190975
    Abstract: Transforming portions of a message to a destination via a communication protocol. A message is received. It is detected whether the received message includes an encoded envelope. The encoded envelope includes a stack defining parameters including information for handling the received message in an original format. If the received message includes the encoded envelope, the defined parameters are transformed to coded parameters in a common format. The coded parameters express the same information for handling the received message in the communication protocol. The encoded envelope is encapsulated in the received message, and the received message in the common format is delivered to the destination. If the received message does not include an encoded envelope, coded parameters are generated in the common format for the received message by encoding addressing information from the received message. The received message having the coded parameters in the common format is delivered to the destination.
    Type: Grant
    Filed: February 22, 2011
    Date of Patent: May 29, 2012
    Assignee: Microsoft Corporation
    Inventors: Nicholas Alexander Allen, Erik Bo Christensen, Stephen Maine, Stephen James Millet, Kenneth David Wolf
  • Patent number: 8185785
    Abstract: A method for communication includes encoding data using at least one Error Correction Code (ECC) to generate first and second output data streams. The first output data stream is processed to generate a first output signal, which has a first acquisition time. The second output data stream is processed to generate a second output signal, which has a second acquisition time that is smaller than the first acquisition time. The first and second output signals are transmitted simultaneously over a communication channel.
    Type: Grant
    Filed: November 26, 2007
    Date of Patent: May 22, 2012
    Assignee: AT&T Intellectual Property I, L.P.
    Inventors: Doron Rainish, Ilan Saul Barak, Raz Shani
  • Patent number: 8181099
    Abstract: Disclosed is a transmission device in a communication system in which a systematic code obtained by systematic encoding of information bits into which dummy bits are inserted and by deleting the dummy bits from the results of the systematic encoding is transmitted and, on the receiving side, the dummy bits which had been deleted on the transmitting side are inserted into the received systematic code, and then decoding is performed. In this transmission device, a dummy bit insertion portion decides the size of the dummy bits to be inserted into the information bits based on a specified code rate or based on the physical channel transmission rate, and uniformly inserts dummy bits of this size into the information bits; a systematic code generation portion performs systematic encoding of the information bits into which the dummy bits are inserted, and deletes the dummy bits from the results of the systematic encoding to generate a systematic code, which is transmitted.
    Type: Grant
    Filed: February 11, 2008
    Date of Patent: May 15, 2012
    Assignee: Fujitsu Limited
    Inventors: Shunji Miyazaki, Kazuhisa Obuchi, Tetsuya Yano
  • Patent number: 8176402
    Abstract: A decoding apparatus includes a memory and a receiving unit and is adapted to decode data in units of codewords each including a parity part. The memory has a storage capacity capable of storing at least data with a length equal to the length of one codeword. The receiving unit receives, as received values, elements of a codeword in a bit-interleaved form, performs bit deinterleaving and parity permutating on the received values, and stores the resultant received values in the memory.
    Type: Grant
    Filed: April 25, 2008
    Date of Patent: May 8, 2012
    Assignee: Sony Corporation
    Inventors: Takashi Yokokawa, Yuichi Hirayama, Osamu Shinya, Satoshi Okada, Kazuhiro Oguchi
  • Patent number: 8171372
    Abstract: A method of feedback in a wireless transmit receive unit includes providing a precoding matrix index (PMI), error checking the (PMI) to produce an error check (EC) bit, coding the PMI and the EC bit and transmitting the coded PMI and EC bit.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: May 1, 2012
    Assignee: InterDigital Technology Corporation
    Inventor: Kyle Jung-Lin Pan
  • Patent number: 8156389
    Abstract: A pruned bit-reversal interleaver supports different packet sizes and variable code rates and provides good spreading and puncturing properties. To interleave data, a packet of input data of a first size is received. The packet is extended to a second size that is a power of two, e.g., by appending padding or properly generating write addresses. The extended packet is interleaved in accordance with a bit-reversal interleaver of the second size, which reorders the bits in the extended packet based on their indices. A packet of interleaved data is formed by pruning the output of the bit-reversal interleaver e.g., by removing the padding or properly generating read addresses. The pruned bit-reversal interleaver may be used in combination with various types of FEC codes such as a Turbo code, a convolutional code, or a low density parity check (LDPC) code.
    Type: Grant
    Filed: February 14, 2009
    Date of Patent: April 10, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Ravi Palanki, Aamod Khandekar
  • Patent number: 8156390
    Abstract: A pruned bit-reversal interleaver supports different packet sizes and variable code rates and provides good spreading and puncturing properties. To interleave data, a packet of input data of a first size is received. The packet is extended to a second size that is a power of two, e.g., by appending padding or properly generating write addresses. The extended packet is interleaved in accordance with a bit-reversal interleaver of the second size, which reorders the bits in the extended packet based on their indices. A packet of interleaved data is formed by pruning the output of the bit-reversal interleaver, e.g., by removing the padding or properly generating read addresses. The pruned bit-reversal interleaver may be used in combination with various types of FEC codes such as a Turbo code, a convolutional code, or a low density parity check (LDPC) code.
    Type: Grant
    Filed: June 23, 2009
    Date of Patent: April 10, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Ravi Palanki, Aamod Khandekar
  • Patent number: 8145973
    Abstract: In order to correctly perform error analysis, test, or the like, a 64B/66B converter of a PCS processing unit of a transmitter conforming to 10 GBASE-R PHY performs 64B/66B conversion on data on a block basis that is transmitted over four lanes, the block being formed of two columns. In the conversion, when a control signal inputted via a control signal input terminal indicates a normal operation mode, if an error code in a block to be converted is detected by an error detector, error expansion that replaces all 8 bytes of data in the block with an error code /E/ is performed. In contrast, when the control signal indicates an analysis mode, the error expansion is not performed even if an error code is detected by the error detector.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: March 27, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Tomofumi Iima
  • Patent number: 8140744
    Abstract: A method and a system is provided for increasing reliability of data stored in storage segments by increasing redundancy data and by permitting user data to fit around defective locations in the storage segment. User data is compressed and reserved for a portion of a storage segment having a data size corresponding to an uncompressed size of the user data. The compressed user data is written to the reserved portion of the storage segment and a pad byte pattern is written to any remaining portion of the reserved portion of the storage segment. The remaining portion of the reserved portion of the storage segment is designated as unused.
    Type: Grant
    Filed: July 1, 2004
    Date of Patent: March 20, 2012
    Assignee: Seagate Technology LLC
    Inventor: Mark Allen Gaertner
  • Patent number: 8140944
    Abstract: For transmission of a block of control information within a wireless network, the control information is interleaved to form an ordered set of control bits, wherein more important information bits of the control information are placed into a first portion of the ordered set of control bits, with less important information bits of the control information placed into a second portion of the ordered set of controls bits. The ordered set of control bits is encoded to form an encoded block of data. The encoded block of data is transmitted to a serving base station, wherein bits from the first portion of the ordered set of control bits will statistically have a lower bit error rate (BER) than bits from the second portion of the ordered set of control bits during transmission.
    Type: Grant
    Filed: January 22, 2009
    Date of Patent: March 20, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Runhua Chen, Zukang Shen, Eko Nugroho Onggosanusi
  • Patent number: 8132076
    Abstract: Circuit, method, and computer program for reordering data units of a data block in accordance with a first pre-determined function. The method includes, for each data unit of the data block—(i) generating an address corresponding to a memory location of a single-port memory module into which the data unit is to be stored, and (ii) storing the data unit in the memory location based on the address generated for the data unit. Each address is generated in accordance with the first pre-determined function, and each memory location of the single-port memory has a different delay associated with the memory location. The method further includes reading each data unit out of the single-port memory in accordance with the first pre-determined function, wherein data units of the data block are reordered based on each different delay associated with each memory location.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: March 6, 2012
    Assignee: Marvell International Ltd.
    Inventor: Peter Tze-Hwa Liu
  • Patent number: 8117507
    Abstract: Decompressing a matrix having a plurality of redundant matrix rows by reading selected matrix rows including at least all non-redundant matrix rows of the matrix from a memory and computing remaining matrix rows of the matrix from the read matrix rows, wherein several matrix rows are computed simultaneously. The read and the computed remaining matrix rows are provided as the decompressed matrix to an output matrix register.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: February 14, 2012
    Assignee: International Business Machines Corporation
    Inventor: Andreas Christian Doring
  • Patent number: 8112688
    Abstract: A data-transmission control method is implemented when transmitting data after dividing the data into a plurality of blocks and performing error correction when performing data transmission. The method includes obtaining additional information indicating a result of error correction process of received data and a result of data transmission (ACK/NACK) from a reception station, and deciding a data length of data to be retransmitted when NACK is obtained as the result of data transmission so that a rate of occurrence of transmission errors upon retransmission is minimized, based on a number of blocks in which error correction has failed indicated by the additional information.
    Type: Grant
    Filed: April 19, 2006
    Date of Patent: February 7, 2012
    Assignee: Mitsubishi Electric Corporation
    Inventor: Tetsuya Mishuku
  • Patent number: 8112680
    Abstract: A system, device and related method are used to communicate data via a plurality of data lanes including a selected data lane. In a first mode of operation, payload data and related supplemental data are communicated via the plurality of data lanes including the selected data lane. In a second mode of operation, only payload data is communicated via the plurality of data lanes, except the selected data lane.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: February 7, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hoe-Ju Chung, Jung-Bae Lee
  • Patent number: 8098549
    Abstract: An information recording medium is provided that includes a data area for recording user data and a defect management area for recording a defect list for managing N number of defect areas existing in the data area, where N is an integer satisfying N?0. The defect list includes two or more blocks, and further includes a header located at a fixed position in the defect list and N number of defect entries, located subsequent to the header, including position information on the respective positions of the N number of defect areas. An anchor is located subsequent to the defect entries, and the header includes first update times information representing the number of times that the defect list has been updated. The anchor includes second update times information representing the number of times that the defect list has been updated.
    Type: Grant
    Filed: October 30, 2009
    Date of Patent: January 17, 2012
    Assignee: Panasonic Corporation
    Inventors: Yoshihisa Takahashi, Motoshi Ito, Hiroshi Ueda
  • Patent number: 8095833
    Abstract: A transmission method includes generating a control information signal relating to control information of a data signal. A transmission frame is formed by repeating and discretely arranging the same control information signal. The data signal and the control information signal are transmitted using the transmission frame.
    Type: Grant
    Filed: August 27, 2008
    Date of Patent: January 10, 2012
    Assignee: Panasonic Corporation
    Inventors: Yutaka Murakami, Katsuaki Abe, Masayuki Orihashi, Akihiko Matsuoka
  • Patent number: 8091011
    Abstract: Certain aspects of a method and system for dynamically adjusting forward error correction (FEC) rate to adapt for time varying network impairments in video streaming applications over IP networks may be disclosed. At a server side of a client-server communication system, a rate of transmission of forward error correction (FEC) packets to one or more clients may be dynamically adjusted based on receiving at least one upstream FEC packet from a plurality of clients. The rate of transmission of the FEC packets to the plurality of clients may be increased when a rate of occurrence of lost data packets is above a particular threshold value. The upstream FEC packets may comprise an urgent packet requesting transmission of a particular FEC packet in order to recover one or more particular lost data packets.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: January 3, 2012
    Assignee: Broadcom Corporation
    Inventors: Yasantha Nirmal Rajakarunanayake, Marcus Kellerman
  • Patent number: 8078934
    Abstract: In a frame sync method, a receiver searches for the presence of an N-symbol long unique word pattern. For each possible frame sync detected, the receiver proceeds to demodulation and FEC processing. After each iteration of the FEC decoder, the detected unique word pattern is compared to the expected one and the frame sync is detected if the number of unique word errors has decreased.
    Type: Grant
    Filed: May 2, 2007
    Date of Patent: December 13, 2011
    Assignee: Inmarsat Limited
    Inventors: Paul R. Febvre, Panagiotis Fines
  • Patent number: 8077566
    Abstract: Various embodiments herein include one or more of systems, methods, software, and/or data structures to test and evaluate unformatted optical media such as optical tape and optical discs. Advantageously, testing and evaluation can be performed earlier in the manufacturing process of the optical media to locate defects and/or other problems or issues with the optical media that can be addressed before additional manufacturing steps are performed and possible wasted. The systems and methods include at least two optical pickup units (OPUs), a first of which may be dedicated to writing digital data and the second of which may be dedicated to scanning, locating, tracking and/or reading the written data (when the optical media is moving in a first direction) in one of a plurality of manners. Information (e.g.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: December 13, 2011
    Assignee: Oracle International Corporation
    Inventor: Faramarz Mahnad
  • Publication number: 20110289367
    Abstract: An error correction encoding device is provided that combines redundancy data with source data, said device including: at least three encoding stages and at least two permutation stages. Each encoding stage implements at least one set of three basic encoding modules, in which a first encoding stage receives said source data and a last encoding stage provides said redundancy data. Each encoding module implements a basic code and includes c inputs and c outputs, c being an integer. The permutation stages are inserted between two consecutive encoding stages and each permutation stage implements a c-cyclic permutation.
    Type: Application
    Filed: February 1, 2010
    Publication date: November 24, 2011
    Applicant: FRANCE TELECOM
    Inventor: Jean-Claude Carlach