Abstract: A computer implemented data processing method for recursively approximating a proper value for a target matrix includes the following steps of: determining whether the target matrix corresponds to a low complexity condition; if so, obtaining a first updated target matrix according to a first variance, relevant to a second iteration parameter, and a first iteration parameter, wherein the first and the second iteration parameters correspond to fixed values; if not, obtaining a second updated target matrix according to a second variance, relevant to a fourth iteration parameter, and a third iteration parameter, wherein the third and the fourth parameters are related to the target matrix.

Abstract: A framer interfacing between one or more data converters and a logic device is disclosed. The framer comprises a transport layer and a data link layer, and the framer is configured to frame one or more samples from the data converters to frames according to a serialized interface. In particular, the synthesis of the hardware for the framer is parameterizable, and within the synthesized hardware, one or more software configurations are possible. Instance parameters used in synthesizing the framer may include at least one of: the size of the input bus for providing one or more samples to the transport layer, the total number of bits per converter, and the number of lanes for the link. Furthermore, a transport layer test sequence generator for inserting a test sequence in the transport layer is disclosed.

Abstract: A Solid-State Disk (SSD) controller enables dynamic higher-level redundancy mode management with independent silicon elements to provide graceful degradation as non-volatile (e.g. flash) memory elements fail during operation of an SSD implemented by the controller. Higher-level error correction provides correction of lower-level uncorrectable errors. If a failure of one of the non-volatile memory elements is detected, then the higher-level error correction is dynamically transitioned from operating in a current mode to operating in a new mode. The transition includes one or more of reducing free space available on the SSD, rearranging data storage of the SSD, recovering/storing failed user data (if possible), and determining/storing revised higher-level error correction information. Operation then continues in the new mode. If another failure of the non-volatile memory elements is detected, then another transition is made to another new mode.

Abstract: A write or read method for use in a computer having multiple channels of memory includes writing or reading data to or from one channel in the memory, and simultaneously in parallel writing or reading an error correction code corresponding to the data to or from a different channel in the memory.

Abstract: In one embodiment, a system for providing header protection in magnetic tape recording is adapted to write a codeword interleave (CWI) set on a magnetic tape including a plurality of CWIs equal to a number of tracks, wherein a data set includes a plurality of CWI sets, provide a CWI set header for the CWI set, the CWI set header including a CWI header for each CWI in the CWI set, each CWI header including at least a CWI Designation (CWID) which indicates a location of the CWI within the data set, calculate or obtain CWID parity for all CWIDs in the CWI set header, the CWID parity including error correction coding (ECC) parity, and store the CWID parity to one or more fields which are repeated for each CWI header in the CWI set header without using reserved bits in the CWI set header to store the CWID parity.

Abstract: A communications system are provided that provides integrated encryption capabilities. In particular, a digital microwave system, terminal and method are provided in which the encryption functions are integrated into the digital microwave terminals. The digital microwave system may also be implemented with external encryption units.

Abstract: This disclosure relates to avoiding a hard error in memory during write time by shifting data to be programmed to memory to mask the hard error. In one implementation, a method of programming data to a memory array includes obtaining error data corresponding to a selected memory cell, shifting a data pattern such that a value to be stored by the selected memory cell matches a value associated with a hard error, and programming the shifted data pattern to memory array such that the value programmed to the selected memory cell matches the value associated with the hard error.

Abstract: A bit interleaving method involves applying a bit permutation process to a QC LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword, after the bit permutation process, into a plurality of constellation words each imade up of M bits, the codeword being divided into N/M sections, each constellation word being associated with one of the N/M sections, and the bit permutation process being performed such that each of the constellation words includes one bit from each of M different cyclic blocks associated with a given section.

Abstract: A system and method for modulation diversity uses interleaving. Code bits are placed into groups and are then shuffled within each group.

Abstract: In each sensor unit, when a sensor control unit cannot detect current flowing to an output side, its address is set to the same address as a sensor unit of the last stage. In an ECU, if the set address and characteristic information of each sensor unit are not stored in a memory unit when the set addresses and the characteristic information of all the sensor units are received by an ECU control unit, the received set addresses and the characteristic information are stored. A failure check unit checks received characteristic information received by the ECU control unit with characteristic information stored in the memory unit. If one characteristic information is in disagreement, a sensor unit having such characteristic information is determined to be failing. If plural characteristic information are in disagreement, a sensor unit having characteristic information and closest to the ECU is determined to be failing.

Abstract: Methods, systems, and computer readable media for test configuration optimized decoding of protocol messages in a network device test system are provided. One exemplary network equipment device test system includes a message blueprint data structure for storing blueprint data for messages to be decoded. The network equipment test device further includes a message decoder for decoding received messages by accessing the message blueprint data structure and matching information elements in the received messages with information elements in the message blueprint data structure. The network equipment test device further includes a message blueprint data structure configurator for receiving, as input, test configuration data, and for configuring the message blueprint data structure for optimized decoding of messages based on the test configuration data.

Abstract: A data quality analysis and management system includes a data quality testing module to perform data quality tests on received data and determine data quality statistics from the execution of the data quality tests. The system also includes a data quality analysis and management engine to determine data quality cost metrics including cost of setup, cost of execution, internal data cost, and external data cost, and calculate a cost of data quality from the data quality cost metrics, and a reporting module to generate a data quality scorecard including statistics determined from execution of the data quality tests by the data quality testing module and the cost of data quality determined by the data quality analysis and management engine.

Abstract: This disclosure relates to avoiding a hard error in memory during write time by shifting data to be programmed to memory to mask the hard error. In one implementation, a method of programming data to a memory array includes obtaining error data corresponding to a selected memory cell, shifting a data pattern such that a value to be stored by the selected memory cell matches a value associated with a hard error, and programming the shifted data pattern to memory array such that the value programmed to the selected memory cell matches the value associated with the hard error.

Abstract: A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system includes a computer processing unit, a memory module, a memory bus that connects the computer processing unit and the memory module, and a co-processing unit or input/output device, wherein the memory bus also connects the co-processing unit or input/output device to the computer processing unit.

Abstract: An image outputting apparatus includes a header production section for producing a header including header information formed from first and second frame information regarding whether pixel data included in a payload are of first and last lines of one frame, respectively, first line information regarding whether or not the pixel data included in the payload are valid, and second line information regarding a line number of a line formed from the pixel data included in the payload, and an error detection code for use for detection of an error of the header information. A packet production section produces a packet which includes, in the payload thereof, pixel data for one line which configure an image obtained by imaging by an imaging section and to which the header is added. An outputting section outputs the produced packet to an image processing apparatus.

Abstract: An electronic circuit includes a microcontroller processor (410), a peripheral (420) coupled with the processor, an endian circuit (470) coupled with the processor and the peripheral to selectively provide different endianess modes of operation, and a detection circuit (140) to detect a failure to select a given endianess, whereby inadvertent switch of endianess due to faults is avoided. Other circuits, devices, systems, methods of operation and processes of manufacture are also disclosed.

Abstract: The present disclosure provides an image outputting apparatus, including, an image pickup section, an error correction code calculation section adapted to calculate an error correction code using pixel data, which configure an image obtained by image pickup by the image pickup section, as an information word, and an outputting section adapted to output coded data, which are data of a codeword obtained by adding the error correction code to the pixel data, to an image processing apparatus provided in an apparatus in which the image outputting apparatus is provided.

Abstract: A method is provided for hierarchical coding of a digital audio signal comprising, for a current frame of the input signal: a core coding, delivering a scalar quantization index for each sample of the current frame and at least one enhancement coding delivering indices of scalar quantization for each coded sample of an enhancement signal. The enhancement coding comprises a step of obtaining a filter for shaping the coding noise used to determine a target signal and in that the indices of scalar quantization of said enhancement signal are determined by minimizing the error between a set of possible values of scalar quantization and said target signal. The coding method can also comprise a shaping of the coding noise for the core bitrate coding. A coder implementing the coding method is also provided.

Abstract: A quadratic permutation polynomial (QPP) interleaver is described for turbo coding and decoding. The QPP interleaver has the form: ?(n)=f1n?fnn2 mod K, where the QPP coefficients f1 and f2 are designed to provide good error performance for a given block length K.

Abstract: A method for controlling access operations of a flash memory includes: receiving first source data from a host; generating a plurality of first scrambled signals according to a plurality of pseudo random sequences and the first source data; obtaining a plurality of transmission powers of the first scrambled signals; and selecting a target scrambled signal from the first scrambled signals according to the transmission powers for storing to the flash memory. An associated flash memory device and an associated flash memory controller are also provided.

Abstract: A method for data storage includes storing data in a memory that includes one or more memory units, each memory unit including memory blocks. The stored data is compacted by copying at least a portion of the data from a first memory block to a second memory block, and subsequently erasing the first memory block. Upon detecting a failure in the second memory block after copying the portion of the data and before erasure of the first memory block, the portion of the data is recovered by reading the portion from the first memory block.

Abstract: Techniques for encoding data are described herein. The method includes receiving a block payload at a physical layer to be transmitted via a data bus. The method includes establishing a block header comprising an arrangement of bits, the block header defining two block header types, wherein a hamming distance between block header types is at least four.

Abstract: According to one embodiment, a memory system includes a non-volatile semiconductor memory that includes memory cells each storing 3 bits, a control unit that writes data to the non-volatile semiconductor memory, and an encoding unit that generates a first parity for user data stored in the first page, a second parity for user data stored in the second page, and a third parity for user data stored in the third page. The user data, the first parity, the third parity, and a portion of the second parity are written to the non-volatile semiconductor memory by a first data coding and a portion of the second parity and a portion of the third parity are written to the non-volatile semiconductor memory by second data coding in which the first page is 0 bit, the second page is 2 bits, and the third page is 1 bit.

Abstract: A method and apparatus for encoding channel quality indicator (CQI) and precoding control information (PCI) bits are disclosed. Each of the input bits, such as CQI bits and/or PCI bits, has a particular significance. The input bits are encoded with a linear block coding. The input bits are provided with an unequal error protection based on the significance of each input bit. The input bits may be duplicated based on the significance of each input bit and equal protection coding may be performed. A generator matrix for the encoding may be generated by elementary operation of conventional basis sequences to provide more protection to a most significant bit (MSB).

Abstract: This invention relates to a receiver circuit which comprises an equalizer (27) and an error decorrelator (25). The error decorrelator being configured for changing (501; 601, 602) the position of symbols. The invention further relates to a corresponding method. This invention finally relates to an interleaving or deinterleaving method which comprises selecting a first number of symbols (204; 302) within a stream of digital data (13; 28) thereby obtaining selected symbols. The method further comprises exchanging (601, 602) the position of at least half of said first number of symbols of said selected symbols with the position of other symbols from said selected symbols. The invention further relates to an interleaving or deinterleaving circuit.

Abstract: A method for error correction deciphering of a receive apparatus in a mobile communication system includes receiving a Packet Data Convergence Protocol (PDCP) packet. The method also includes, when error correction ciphering is set, acquiring a partial Hyper Frame Number (HFN) from the PDCP packet. The method further includes comparing the partial HFN and the receive apparatus's own lower HFN of a constant bit count. The method still further includes, if the partial HFN and the receive apparatus's own lower HFN of the constant bit count are different from each other, performing an HFN correction function.

Abstract: The present invention discloses a rate matching method and device. The method includes that: an information bit sequence is coded and interleaved to obtain a mother code codeword with a length NFB—Buffer; and bits are selected from the mother code codeword to generate a hybrid automatic repeat request (HARQ) subpacket for current transmission. By means of the present invention, the effect of covering the whole mother code area can be achieved as much as possible, and the performance of the HARQ multiple retransmission link can be enhanced.

Abstract: A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.

Abstract: An encoding apparatus derives a bit order based on a puncturing table that specifies different puncturing patterns for different transmission rates. The encoding apparatus then generates an error correcting code from an input information bit string and rearranges the error correcting code in the derived bit order. The error correcting code is punctured by taking a number of consecutive bits from the rearranged error correcting code. The number of bits taken varies depending on the transmission rate. The punctured error correcting code is output to a decoding apparatus, which realigns the code bits according to the transmission rate and the puncturing table, then uses the realigned error correcting code to correct errors in erroneous data. Rearrangement of the error correcting code makes the puncturing process more efficient by avoiding the need to decide whether to take or discard each bit individually.

Abstract: A method and apparatus for selecting interleaver sizes for turbo codes is provided herein. During operation information block of size K is received. An interleaver size K? is determined that is related to K?, where K? from a set of sizes; wherein the set of sizes comprise K?=ap×f, pmin?p?pmax; fmin?f?fmax, wherein a is an integer and f is a continuous integer between fmin and fmax, p takes integer values between pmin and pmax, a>1, pmax>pmin, pmin>1. The information block of size K is padded into an input block of size K? using filler bits, if needed. Encoding is performed using the original input block and the interleaved input block to obtain a codeword block using a turbo encoder. The codeword block is transmitted through the channel.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. Such data processing includes data shuffling.

Abstract: Methods and apparatus create a corruption mask from a sequence that is generated by an n-state sequence generator with n>2. A digital media stream containing n-state symbols is corrupted in accordance with the corruption mask. The corruption takes place by applying a one argument or a two argument n-state logic function. The corruption rate of the digital media stream is preferably less than 100% allowing it to be reviewed. Data related to the corruption mask and the corruption mask are transmitted to a processor based receiver, allowing the receiver to decorrupt the corrupted digital media stream and to display it in its uncorrupted state.

Abstract: A method of organizing on-chip data memory in an embedded system-on-chip platform whereon a deterministic application needs to meet a guaranteed constraint on its functional system behavior is disclosed. In one aspect, the method includes: a) dividing the deterministic application into blocks one of which corresponds to a part of a subtask of the application, the block receiving input data and/or generating output data and including internal intermediate data for transforming the input data into the output data, b) splitting the internal intermediate data into state and non-state data, and c) putting the non-state data and a part of the state data in a protected buffering module being part of the data memory and being provided with an error detection and correction module, so that they are available for mitigating the effect of faults on the functional system behavior on-line while meeting the at least one guaranteed constraint.

Abstract: The present disclosure relates to a method for interleaving a stream of input data blocks, the method comprising steps of: subdividing a block into sub-blocks of fixed size in number of data rows and data columns, the sub-blocks being distributed in the block in rows of sub-blocks and in columns of sub-blocks, transferring the data contained in the block into a first memory, while respecting the order of the data in the input stream, transferring the data contained in the block by row of sub-blocks, into a second memory in which the data of each sub-block is accessible from the address of the sub-block, transferring the data of each sub-block by column of sub-blocks, from the second memory into a third memory, by putting back the data of each sub-block in data rows and columns, and transferring the data by data column from the third memory into an output stream.

Abstract: A convolutional interleaver uses local memory of a first IC in combination with burst-type memory of a second IC. When a burst of data is read from memory of the second IC, one data value is provided to a data output and the remaining values are temporarily stored in local memory. After the memory of the second IC is initially filled, burst WRITE and burst READ operations provide efficient data transmission between the ICs.

Abstract: An aliasing module is defined and connected to receive a first bit stream to be transmitted over a data bus from a memory to an external controller of the memory. The aliasing module is defined and connected to alias the first bit stream as a second bit stream and transmit the second bit stream over the data bus in lieu of the first bit stream. A de-aliasing module is defined and connected to receive the second bit stream from the data bus at the external controller. The de-aliasing module is defined and connected to de-alias the received second bit stream back to the first bit stream and provide the first bit stream to the external controller for processing.

Abstract: A counter configuration operates in cooperation with a delay configuration such that the counter configuration counts an input interval based on a given clock speed and a given clock interval while the delay configuration provides an enhanced data output that is greater than what would otherwise be provided by the given clock speed. The counter configuration counts responsive to a selected edge in the clock interval. An apparatus in the form of a correction arrangement and an associated method are configured to monitor at least the delay configuration output for detecting a particular time relationship between an endpoint of the input interval and a nearest occurrence of the selected clock edge in the given clock signal that is indicative of at least a potential error in the enhanced data output and determining if the potential error is an actual error for subsequent use in correcting the enhanced data output.

Abstract: A system, method and node for unambiguous encoding of Physical Downlink Control Channel (PDCCH) channels in a Long Term Evolution (LTE) telecommunications system to remove detection errors. The method includes modifying a size of a circular buffer where the coded bits are collected to avoid repetition of the coded bits in consecutive subset of the control channel elements allocated to the PDCCH. The size of the circular buffer is selected so that it is not equal to the number of coded bits output from the encoder. Coded bits can be deleted from or added to the coded bit sequence depending on the size of the circular buffer.

Abstract: An encoding method generates a parity bit sequence by encoding an information sequence with feed-forward LDPC convolutional codes based on a plurality of parity check polynomials each having a coding rate of (n?1)/n, then performs an interleaving process and an accumulation process. The accumulation process is an exclusive OR operation performed on bits of the interleaved parity bit sequence and on bits of a delayed accumulated parity bit sequence. A coded sequence is then generated from the information sequence and the accumulated parity bit sequence.

Abstract: The present invention is directed to a recoverable Ethernet receiver. A joint decision feedback equalizer (DFE) and Trellis decoder is configured to decode a receiving signal to result in a received symbol, and configured to generate a check-idle value which is used to indicate an idle mode. A physical coding sublayer (PCS) block is configured to generate a seed value and a polarity characterization according to the received symbol, with the joint DFE and Trellis decoder generating the check-idle value according to the seed value and the polarity characterization.

Abstract: Methods and apparatus for managing data storage in memory devices utilizing memory arrays of varying density memory cells. Data can be initially stored in lower density memory. Data can be further read, compacted, conditioned and written to higher density memory as background operations. Methods of data conditioning to improve data reliability during storage to higher density memory and methods for managing data across multiple memory arrays are also disclosed.

Abstract: A data storage device includes a memory and a controller. The controller is configured to identify groups of bits that match any bit pattern in a first set of bit patterns. Each of the groups of bits includes a first bit of first data, a second bit of second data, and a third bit of third data to be stored at the memory. The controller is configured, in response to determining that a count of the identified groups exceeds a threshold, to change multiple bits of the first data. Changing the multiple bits of the first data reduces a number of the groups of bits that match any bit pattern in the first set of bit patterns.

Abstract: A memory system comprising a first memory, a control module, a test module, and a second memory. The first memory is configured to store pages of data to be tested. The control module is configured to store identifiers of the pages of data. The test module is configured to test the pages of data in the first memory. The second memory is configured to, while the pages of data stored in the first memory are being tested, store the identifiers of the pages of data and store the pages of data. The control module is further configured to, after the test module completes testing of the pages of data in the first memory, move the pages of data from the second memory to the first memory based on the identifiers of the pages of data.

Abstract: Systems, methods, and apparatus are provided for improving the iterative decoding performance of a decoder, for example, as used in a wireless communications receiver or in a data retrieval unit. A decoding technique may receive and process a set of channel samples using an iterative decoder. If the iterative decoder output indicates a decoding failure, noise samples may be combined with the received channel samples to create biased channel samples. Noise samples may be generated using a pseudo-random noise generator and/or by using signals already present in the communications receiver or data retrieval unit. The biased channel samples may be provided to the iterative decoder and the iterative decoder may re-run using the biased channel samples.

Abstract: A system for signal processing includes: a plurality of signal processing units associated with corresponding channels; a feedback channel for receiving a selected feedback signal through a selector of an output associated with each of the signal processing units; and a correlator connected to the feedback channel and having a receiving unit to receive the selected feedback signal, an error calculating unit to calculate an error based at least in part on the selected feedback signal, and a correction calculation unit to generate a correcting information based at least in part on the error. In some cases, the association between the signal processing units and the signal channels is configured based on a mode.

Abstract: Soft decision sections provisionally decide each modulated signal separated using an inverse matrix calculation of a channel fluctuation matrix at separation section. Signal point reduction sections reduce candidate signal points of a multiplexed modulated signal using the provisional decision results. Soft decision sections make a correct decision using the reduced candidate signal points and obtain received data of each modulated signal. This allows received data RA, RB with a good error rate characteristic to be obtained with a relatively small number of calculations without reducing data transmission efficiency.

Abstract: A multimedia information receiving apparatus receives multimedia information which is transmitted by a broadcast system and receives multimedia information which is simultaneously transmitted by another transmission system such as IP communications, and generates one received information by selecting elements having a few errors from elements of demodulated broadcast system information and elements of demodulated other transmission system information and then arranging the selected elements.

Abstract: A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system includes a computer processing unit, a memory module, a memory bus that connects the computer processing unit and the memory module, and a co-processing unit or input/output device, wherein the memory bus also connects the co-processing unit or input/output device to the computer processing unit.

Abstract: A method of feedback in a wireless transmit receive unit includes providing a precoding matrix index (PMI), error checking the (PMI) to produce an error check (EC) bit, coding the PMI and the EC bit and transmitting the coded PMI and EC bit.

Abstract: The inventive concept enables backward-compatible extension of existing interleaver-based transmission systems to the effect that in addition to an existing logical transport channel, which is interleaved using a standardized interleaver profile, further logical transport channels may be transmitted via the same physical transmission channel. In this context, the first transport channel obviously is reduced in terms of data rate, so that the additional transport channels may actually obtain a transmission capacity that is needed accordingly. Interleaver profiles of the further logical transport channels are derived, to this end, from the interleaver profile of the first transport channel.