Abstract: A modem configured to couple to a communication medium for establishing a communication channel thereon. The modem includes an interleaver component configurable as to interleaver parameters ‘I, D’ corresponding to block length and depth respectively. An interleaver memory buffers the communication channel. An interleaver controller controls writing to and reading from the memory of successive data elements of the communication channel with a quantity ‘I’ pairs of write and read pointers. Each pair or write and read pointers identifies memory locations corresponding with an input and output respectively of an associated one of ‘I’ virtual first-in-first-out (‘v-FIFO’) buffers in the memory. Control of the pointers required to read out the stored data elements in interleaved fashion is limited to shifting all pointers uniformly by one address block in each interleaver block cycle, which simplifies pointer management.

Abstract: A MIMO transmitter including an interleaving system for parsing encoded bits to a plurality of spatial streams and a plurality of interleavers to interleave bits for spatial streams such that at least a first spatial stream uses a first stream interleaver that interleaves with a pattern distinct from a second stream interleaver interleaving for a second spatial stream.

Abstract: A method of generating interleaver addresses in a circuit for decoding data is disclosed. The method comprises the steps of receiving a data stream having a plurality of data blocks, each block having N bits; dividing each data block of the plurality of data blocks into m windows, each window comprising N/m bits; and calculating an interleaver address for each window as a function of modulo N/m. A circuit for generating an interleaver address in a circuit for decoding data is also disclosed.

Abstract: According to one aspect of the invention, a method of interleaving data for enabling data coding in a communication network is disclosed, the method including storing parameters required to output address sequences for a matrix, receiving a block size associated with a block of data at a circuit for interleaving data, outputting parameters associated with the stored parameters based upon the block size, and producing an address sequence using the parameters. A circuit for interleaving data for data coding in a communication network is also disclosed. The circuit includes a lookup table storing parameters required to output address sequences for a matrix. A search coupled to the lookup table receives a clock size associated with a matrix and outputs parameters based upon the block size. A computation circuit coupled to receive the parameters outputs an address sequence using the parameters.

Abstract: Methods for changing a depth of interleaver devices and de-interleaver devices are provided, whereby a change in the depth is possible while transmitting or receiving operations are in progress. For this, delays of delaying devices are enlarged or reduced, additional data values being inserted to guarantee smooth flowing data transmission.

Abstract: One embodiment of the invention relates to a network communication device. The network communication device includes a network interface configured to receive an initial data stream. The network communication device also includes an interleaving redundancy encoder that comprises a memory unit arranged in N columns and D rows. The interleaving redundancy encoder is configured to calculate at least one redundancy byte based on a series of equally spaced, non-consecutive bytes in the initial data stream, where a number of bytes between equally spaced bytes is approximately equal to D?1. Other systems and methods are also disclosed.

Abstract: A method and device for interleaving the (N+1) input data and for allocating the corresponding memory comprises the steps of allocating a mth buffer section equals to (m×Dm+Pm) memory address for buffering the mth data of the N+1 input data, where m is a nonnegative integer from 0, 1 to N, Dm is the delay of the mth data, and Pm is a nature number representing a predetermined number of memory address for extra buffering the mth data; assigning an empty memory address in the mth buffer section to buffer the mth data; accessing the mth data from where the mth data buffered after buffering the (N+1) data, and outputting the (N+1) data in a (m×Dm) delay sequence. The present invention allocates the memory address effectively, so applying the present invention economizes the use of the memory request.

Abstract: Embodiments of the present invention provide techniques for generating MTR codes with ECC without the use of a second MTR code, while still satisfying the specified constraint.

Abstract: An apparatus and a method for deinterleaving using an inner memory and an outer memory. The apparatus includes data receiving apparatus of a mobile equipment in a mobile communication system including the mobile equipment and a base station for transmitting data to the mobile equipment through a radio channel. The apparatus includes a deinterleaving unit having a deinterleaver and an outer memory separately located with the deinterleaver. The deinterleaver stores address information including an address of the outer memory and values corresponding to the address of the outer memory in an inner memory. The outer memory stores the data to be deinterleaved, and a decoder for decoding the deinterleaved data.

Abstract: An interleaving method to which time-first-mapping is applied for a plurality of channel-coded and rate-matched code blocks considering a modulation scheme in a mobile communication system is provided. The interleaving method includes determining sizes of a horizontal area and a vertical area of an interleaver memory, selecting a defined number of adjacent coded symbols in a same code block according to a modulation scheme, generating modulation groups in a vertical direction, sequentially writing the modulation groups in the horizontal area on a row-by-row basis, and sequentially reading the symbols written in the interleaver memory on a column-by-column basis.

Abstract: An apparatus and method interleaving symbols coded by a turbo encoder in a communication system that uses the turbo encoder for encoding transmission information into coded systematic symbols and at least one parity symbol pair, and maps the coded symbols using a second or higher modulation order before transmission. An interleaver controller performs a control operation of cyclic-shifting the systematic symbols among the symbols coded by the turbo encoder depending on a size of a physical packet to be transmitted, the number of transmission slots, and the modulation order, using an equation of (K×c+k)mod R, and cyclic-shifting redundancy symbols constituting the remaining size of the coded symbols to be transmitted, using an equation of floor{(K×c+k)/D}mod R. An interleaver cyclic-shifts input symbols under the control of the interleaver controller.

Abstract: An apparatus, system and method in which a plurality of interleavers are utilized with the outputs of the interleavers being combined to generate a single combined output are provided. In a preferred embodiment, at least two of the plurality of interleavers are of a different type. For example, in one exemplary embodiment, a first interleaver is an S-random interleaver with a second interleaver being one of an algebraic, convolutional, helical, pseudo random, or other type of interleaver. Combinational logic receives the output from each of the plurality of interleavers and combines the outputs to generate one combined output having a permuted order. By combining the outputs from a plurality of interleavers, a greater amount of randomness in the input data may be obtained as opposed to that of the known single interleaver systems.

Abstract: The present invention provides methods for generating self-inverting turbo code interleavers having high separation and high dispersion characteristics. Methods are provided for deterministically generating self-inverting turbo code interleavers from a specification for an existing non-self-inverting interleaver. Methods are also provided for randomly generating self-inverting turbo code interleavers. The present invention also provides methods and apparatus for encoding digital data and communicating the digital data using self-inverting turbo code interleavers/de-interleavers.

Abstract: The present invention provides methods for generating self-inverting turbo code interleavers having high separation and high dispersion characteristics. Methods are provided for deterministically generating self-inverting turbo code interleavers from a specification for an existing non-self-inverting interleaver. Methods are also provided for randomly generating self-inverting turbo code interleavers. The present invention also provides methods and apparatus for encoding digital data and communicating the digital data using self-inverting turbo code interleavers/de-interleavers.

Abstract: A method, system and apparatus for detecting soft errors in non-dataflow circuits. In a preferred embodiment, input is received at a latch system. The latch system consists of two pairs of latches. The second pair of latches is parallel to the first pair of latches. Both pairs of latches capture the input. However, the second pair of latches captures the input later in time relative to the first pair of latches latch. The captured input is then transferred from the first latch in each pair of latches to the second latch in each pair of latches. A comparison is made of the input in the two second latches. If the input captured in the two second latches is not the same, then a message is sent to a recovery unit.

Abstract: The present invention provides methods for generating self-inverting turbo code interleavers having high separation and high dispersion characteristics. Methods are provided for deterministically generating self-inverting turbo code interleavers from a specification for an existing non-self-inverting interleaver. Methods are also provided for randomly generating self-inverting turbo code interleavers. The present invention also provides methods and apparatus for encoding digital data and communicating the digital data using self-inverting turbo code interleavers/de-interleavers.

Abstract: A method for de-interleaving S2 received sequences of interleaved received data samples respectively issued from S2 physical channels and to be associated with S1 output transport channels is provided. The S2 received sequences have been delivered, before transmission by a two-stage multi-interleaving device, from S1 initial sequences of ordered data samples respectively associated to S1 initial transport channels. The two-stage multi-interleaving device includes a first stage including S1 interleaving blocks respectively associated to the S1 initial transport channels, a second stage including S2 interleaving blocks respectively associated to the S2 physical channels, and an inter-stage of predetermined data-routing functions connected between the first and second stages.

Abstract: A binary error-correction coding method that produces certain codewords such that a collection of all valid codewords is a resulting error-correction code that can have large minimum distance. The method's assignment of codewords enables them to be represented as particular paths through a single trellis with branches labeled with permuted information symbols and permuted parity symbols in addition to conventional sequential information and parity symbols. Not all paths through trellis represent valid codewords. The resulting code is linear so real-time encoding can be implemented with a large generator matrix. Also an iterative method of error-correction decoding that is based on a single trellis with branches labeled with both permuted and sequential information and parity symbols, despite not all paths in the trellis corresponding to valid codewords.

Abstract: Disclosed herein is a method and system for interleaving and deinterleaving of data bits in wireless data communications. Interleaving is performed as a single stage parallel operation using a single standard memory block. The disclosed method and system is capable of implementing different interleaving techniques, individually, or as a combination thereof. The disclosed system comprises a plurality of multiplexers, a standard memory block, read and write buses, control block, and a lookup table. The contents of the lookup table are generated based on an interleaving function. The data bits from the input bus and bits from the read bus of the memory are inputted to the plurality of multiplexers. Based on the lookup table's contents the multiplexers are switched to parallelly permute the input data bits and read bits from the read bus. The permuted data bits are in an interleaved sequence.

Abstract: Methodology, systems and media associated with selectively allocating memory are described. One exemplary method embodiment comprises receiving a quality data that identifies the quality of one or more allocatable subsets of a memory and selectively allocating a subset of memory from the allocatable memory to an application based, at least in part, on memory quality as identified in the quality data.

Abstract: A memory device (memory module) having one or a plurality of memory chips is disclosed. By including in a memory chip an error generation part to generate an error, an error is generated in a specific area of a memory in accordance with an address specification, thereby confirmation of an ECC function is facilitated. The error generation part includes an error code generation part that generates an error code. The memory chip is configured by one or a plurality of memory matrixes.

Abstract: A method and apparatus for encoding and decoding data is described herein. During operation, data enters a convolutional encoder (101). The encoder encodes the information bits from the data at encoding rate (1/R0) to produce data symbols vectors P0, P1, . . . , PR0. Vectors P1, . . . , PR0 are each interleaved separately to form vectors P0?, P1?, . . . , PR0?. A multiplexer (105) multiplexes P0?, P1?, . . . , PR0? to produce vector Q. The multiplexed interleaved symbols Q are input into symbol adder/remover (107) where appropriate symbols are added or removed to match an over-the-channel transmission rate. Finally, vector Q? is transmitted via over-the-channel transmission.

Abstract: A memory controller optimizes execution of a read/modify/write command by breaking the RMW command into separate and unique read and write commands that do not need to be executed together, but just need to be executed in the proper sequence. The most preferred embodiments use a separate RMW queue in the controller in conjunction with the read queue and write queue. In other embodiments, the controller places the read and write portions of the RMW into the read and write queue, but where the write queue has a dependency indicator associated with the RMW write command in the write queue to insure the controller maintains the proper execution sequence. The embodiments allow the memory controller to translate RMW commands into read and write commands with the proper sequence of execution to preserve data coherency.

Abstract: In a memory system, an ECC circuit is not inserted on a data path for data writing/reading. The ECC process is performed during the cycle of normal data reading/writing process, in such timing that it does not conflict with the data reading/writing process in order not to cause a substantial delay in the data writing/reading process. Specifically, the ECC process is performed during the cycle of burst transfer in which a plurality of data are successively input to or output from a shift register. Since no access is made to the memory cell array during the burst transfer cycle, the ECC process does not cause a delay in the reading/writing process.

Abstract: A system and method is provided for interleaving data in a communication device. The system includes a memory that stores blocks of data to be interleaved. A write module is configured to receive a burst of data and write blocks of data from the burst into the memory. The write module is configured to provide control information, including a rolling burst counter and a burst profile bank identifier for each block. If interleaving is activated, the control information includes information pertaining to how the read module should interleave the block. If interleaving is not activated, the control information includes the byte length size of the burst. A read module reads blocks of data from memory in either an interleaved fashion or a non-interleaved fashion in accordance with the control information.

Abstract: A method (500) is provided for operating an interleaver circuit 120 having N shift lines (2201-220N). Each shift line has a line input node, a line output node, and one or more bit storage elements (240). The method includes: storing don't-care bits in each bit storage element (520); isolating the line output nodes from an interleaver output node (520); receiving a stream of data bits at an interleaver input node (530); and sequentially connecting the interleaver input node to respective line input nodes to shift the stream of data bits into the bit storage elements of corresponding shift lines in an interleaved fashion (530). A don't-care bit is shifted out of each of the bit storage elements in corresponding shift lines as each data bit is shifted in. A last don't-care bit is shifted out of respective bit storage elements in the shift lines during N consecutively-received data bits.

Abstract: An interleaver and method of interleaving operate on data represented in a sequence of symbols to produce an interleaved sequence of symbols. The interleaver performs intra-block and inter-block permutations on the sequence of symbols. An encoder and method of encoding operate on data represented in a source sequence of symbols. The source sequence of symbols is encoded into a first sequence of codewords and interleaved using intra-block and inter-block permutations to produce a sequence of interleaved symbols. The sequence of interleaved symbols is encoded into a second sequence of codewords. A decoder and method of decoding operate on data represented in a sequence of received symbols. The sequence of received symbols comprises a formatted copy of the source sequence of symbols and the first and the second sequence of codewords.

Abstract: Data stored in non-volatile storage is decoded using iterative probabilistic decoding. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding sensed states of a set of non-volatile storage element. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. Soft data bits are read from the memory if the decoding fails to converge. Initial reliability metric values are provided after receiving the hard read results and at each phase of the soft bit operation(s). In one embodiment, a second soft bit is read from the memory using multiple subsets of soft bit compare levels. While reading at the second subset of compare levels, decoding can be performed based on the first subset data.

Abstract: There are provided a plurality of bridge circuits which convert the test data information from a common test bus connected to a plurality of memories of different access data widths and address decode logics to the inherent access data widths of each memory and also convert the test address information from the common test bus to the inherent bit format of each memory to supply the result to the corresponding memory. The test address information is supplied in parallel from the common test bus to a plurality of memories to realize the parallel tests. Accordingly, the test data information can be supplied in parallel to a plurality of memories of different data widths and the address scan direction in the respective memories for the test address information can be uniformed to the particular direction depending on the inherent bit format. Thereby, the memory test efficiency by the match pattern for a plurality of on-chip memories can be improved.

Abstract: A memory test circuit is provided, comprising: an output data selector configured to receive the plurality of read data bits and output a fraction of the plurality of read data bits as a plurality of fractional data bits; and a control circuit configured to select a set of bit positions in the plurality of read data bits whose corresponding values will form the plurality of fractional data bits, wherein the selected set of bit positions is selectable from a plurality of possible sets of bit positions, each actual bit position in the plurality of read data bits being contained in at least one of the possible sets of bit positions, and wherein a fractional length of the plurality of fractional data bits is smaller than a full length of the plurality of read data bits.

Abstract: The invention relates to a semi-conductor component test procedure, and a semiconductor component test device (10b), which comprise: a device (43) for generating pseudo-random address values to be applied to corresponding address inputs of a semi-conductor component (2b), in particular a memory component, to be tested.

Abstract: The invention relates to a semi-conductor component test procedure, as well as to a semi-conductor component test device with a shift register, which comprises several memory devices from which pseudo-random values (BLA, COL, ROW) to be used for testing a semi-conductor component are able to be tapped and emitted at corresponding outputs of the semi-conductor component test device, whereby the shift register comprises at least one further memory device, from which a further pseudo-random value (VAR) is able to be tapped and whereby a device is provided, with which the further pseudo-random value (VAR) can selectively, if needed, be emitted at at least one corresponding further output of the semi-conductor component test device.

Abstract: A memory address generating apparatus comprising an address converting circuit, after setting a first setting region storing substitution source data and a second setting region storing substitution destination data that are a substitution target of the substitution source data in an address space provided by the memory, if a specified address specified by the processor as the access destination to the memory is included between a first beginning address and an end address of the first setting region, changing the specified address to a substitution destination address generated by adding a difference between the specified address and the first beginning address to a second beginning address of the second setting region.

Abstract: A method for creating a high efficiency, error minimizing code is provided. In addition, an apparatus having a high efficiency, error minimizing code is provided. In particular, the present invention provides a high efficiency, error minimizing code for use in connection with systems having a communication channel in which identifiable dominant errors occur, and that is used to transmit data that may be usefully applied in the system even though the received signal is not exactly equal to the original signal. Furthermore, the present invention provides a code that may be used to constrain the effects of dominant errors in a communication channel.

Abstract: Methods and systems for in-place updating original content of an original version stored in a non-volatile storage device and for yielding updated content of an updated version. Some of the described embodiments illustrate the possibilities for reduction in storage operations, storage blocks, and/or update package size. Some of the described embodiments include the storage of error recovery result(s) such as XOR result(s) which enable the recovery of data in case of an interruption of the update process. In some of the described embodiments, there is re-usage of a buffer protecting content which is required in the update process.

Abstract: An interleaver has an input multiplexer that receives a data sequence at an interleaver input and that separates the data sequence into multiple data sub-blocks. The interleaver has a linear feedback shift register that generates an input address sequence. The interleaver has adder circuits that generate output address sequences associated with each data sub-block. The interleaver has memory that stores the data sub-blocks at addresses controlled by the input address sequence. The memory reproduces each data sub-block in an interleaved sequence controlled by the associated output address sequence. The interleaver has an output multiplexer that assembles the interleaved sequences to provide an interleaver output.

Abstract: An interleaver/de-interleaver that may be used for multiple interleaving algorithms and look up tables (LUTs) of one or more interleaving standards. In at least some embodiments, the interleaver/de-interleaver may comprise an initial value selector, offset selector, and a pruning adjuster coupled to a combining block. The interleaver/de-interleaver may further comprise a boundary regulator coupled to the combining block, wherein the boundary regulator is configurable to modify an output of the combining block according to one or more pre-determined rules. The interleaver/de-interleaver may further comprise a controller coupled to, at least, the initial value selector, the offset value selector, and the offset adjuster, whereby the interleaver/de-interleaver may be used to interleave or de-interleave a block of data in accordance with a plurality of interleaving algorithms.

Abstract: There is provided an address generation apparatus for one of an interleaver and a deinterleaver in a Wideband Code Division Multiple Access (W-CDMA) system. The apparatus includes an address pair generator for generating an address pair (n, P(n)) in real-time for one of an interleaver operation and a deinterleaver operation that includes inter-row permutation and intra-row permutation. The address pair (n, P(n)) is generated such that, for the interleaving operation, data to be interleaved are read out from the at least one memory device using the P(n) and interleaved data are written into the at least one memory device using the n. Further, the address pair (n, P(n)) is generated such that, for the deinterleaving operation, data to be deinterleaved are read out from the at least one memory device using the n and deinterleaved data are written into the at least one memory device using the P(n).

Abstract: An error correction code system, e.g. of a magnetic tape drive, applies error correction redundancy to data, separates it, or interleaves it, and records it into separate groups. An error correction encoder applies an outer error correction code to one of the separate groups of information, forming one set of rows of information and outer ECC information. An error correction encoder applies an outer error correction code to another separate group of information, forming another set of rows of information and outer ECC information. A data organizer interleaves the one set of rows of information and outer ECC information with the another set of rows of information and outer ECC information for recording on tracks of a recording media in an interleaved pattern of one set of rows of information and outer ECC information with another set of rows of information and outer ECC information.

Abstract: An interleaving apparatus and method for an OFDM transmitter are provided. The interleaving apparatus comprises a memory unit, a memory write/read control unit, a memory access address generation unit, and a second permutation and output selection unit. The memory unit includes a plurality of memory banks, which are capable of being independently controlled so that data can be written or read in/from the memory banks, each having memory cells arranged in an N×M matrix structure. The memory write/read control unit generates control signals to write/read data in/from the memory unit. The memory access address generation unit generates a memory access address used to write/read data in/from the memory unit in response to the memory write/read control signals. The second permutation and output selection unit rearranges the positions of data bits output from the memory unit and outputs the position-rearranged data bits.

Abstract: An interleaving/deinterleaving method and apparatus may interleave/deinterleave first data to produce second data so that the arrangement of data elements of the second data is different from that of the first data. To accomplish this, word data that are part of the first data are read from a data storage section and a data element to be processed is selected from the word data for output. The operations of reading word data and selecting data elements of the word data to output are repeated, and a sequence of data elements to be processed at the time of repetition is determined in accordance with the arrangement of the data elements of the second data.

Abstract: The invention relates to the processor for performing convolution interleaving/de-interleaving on data symbols on plural original data symbols and convolution de-interleaving on the convolution interleaved data symbols. The processor for performing convolution interleaving on data symbol comprises a memory, an original address generator, and a storage address generator which generates an original address. The storage address generator generates the storage address of each of the stored plural data symbols in the memory according to the original address and a first predetermined sequence, and each of the convolution interleaved data symbols is stored in the memory according to the storage address; furthermore, all stored data symbols in the memory are configured into a circular structure.

Abstract: The present invention relates to a storage device which receives input of data of arbitrary data length, stores the data, and outputs the stored data in order of input. It provides a storage device capable of unloading data of arbitrary data length from data areas quickly. The storage device is equipped with a start position pointer which additionally stores the write position before the change each time a write position memorized by a write pointer is changed due to data input. When areas are freed, new read positions are determined based on saved write positions and the number of data items to be unloaded.

Abstract: One embodiment of the present invention provides a system that selects bases to form a regression model for cache performance. During operation, the system receives empirical data for a cache rate. The system also receives derivative constraints for the cache rate. Next, the system obtains candidate bases that satisfy the derivative constraints. For each of these candidate bases, the system: (1) computes an aggregate error E incurred using the candidate basis over the empirical data; (2) computes an instability measure I of an extrapolation fit for using the candidate basis over an extrapolation region; and then (3) computes a selection criterion F for the candidate basis, wherein F is a function of E and I. Finally, the system minimizes the selection criterion F across the candidate bases to select the basis used for the regression model.

Abstract: A processor on which a software-based interleaver is run performs interleaver generation, which is split into two parts to reduce the overhead time of interleaver changing. First, preprocessing prepares seed variables, requiring a small memory. Second, on-the-fly address generation generates interleaved addresses through simple adding and subtracting operations using the seed variables.

Abstract: A method, adapted to a 3GPP turbo coder, for interleaving a plurality of data of a data frame and a circuit thereof is provided. The present invention computes a value of Row Parameter according to the size of the data frame, computes an index for a table according to the value of Row Parameter, and searches for a value of Column Parameter, a value of Prime Parameter and a value of Primitive Parameter from the table.

Abstract: A data read-out circuit is provided with a sense amplifier circuit and a selector. The sense amplifier circuit senses a stored data stored in a memory cell array by using a plurality of reference levels to generate a plurality of read data, respectively. Thus, the sense amplifier circuit outputs the plurality of read data with regard to the stored data. The selector selects a data corresponding to any one of the plurality of read data based on a control signal and outputs the selected data as an output data.

Abstract: A memory controller optimizes execution of a read/modify/write command by breaking the RMW command into separate and unique read and write commands that do not need to be executed together, but just need to be executed in the proper sequence. The most preferred embodiments use a separate RMW queue in the controller in conjunction with the read queue and write queue. In other embodiments, the controller places the read and write portions of the RMW into the read and write queue, but where the write queue has a dependency indicator associated with the RMW write command in the write queue to insure the controller maintains the proper execution sequence. The embodiments allow the memory controller to translate RMW commands into read and write commands with the proper sequence of execution to preserve data coherency.

Abstract: This invention uniquely partitions the pBIST ROM for storing program and data information. The pBIST unit selectively loads both the algorithm and data, the algorithm only or the data only for each test set stored in the pBIST ROM into read/write registers. These registers are memory mapped readable/writable. A configuration register has an algorithm bit and a data bit which determines whether the corresponding algorithm or data is loaded from the pBIST ROM. The pBIST unit includes another configuration register having one bit corresponding to each possible test set stored in the pBIST ROM. The pBIST unit runs a test set if the corresponding bit in the configuration register has a first digital state.

Abstract: An evaluation system includes a storage unit, a microcomputer for outputting a read address to the storage unit and executing reading, and an error generator for generating an error signal based on a mode signal and the read address that are transmitted between the storage unit and the microcomputer and outputting the error signal. The microcomputer determines read data received from the storage unit as an error regardless of the read data when the error signal indicates an error in the read data.