Abstract: The present invention provides asymmetric digital subscriber line (ADSL) modems including a discrete multitone (DMT) modem module. The DMT modem module includes a digital signal processor (DSP) configured to process control signals for initializing the ADSL modem during installation associated with a host device and transmit the processed control signals to a host controller of the host device.

Abstract: An interleaver includes two random access memories for storing data and an addressing device (100) linked to respective address inputs of the two memories. The addressing device is designed to transmit, at each instant of a clock, a cue for read access to one of the two memories and a cue for write access to the other of the two memories, so that, at each instant, a data item is written to or read from each memory.

Abstract: A method and apparatus for decoding a frame of interleaved information bits in a communication system, where the decoding of the frame of interleaved information bits may begin before all of the bits in the frame are received. The frame of interleaved information bits has a frame start time and a frame end time. The frame also includes a first fractional segment that has a start time that is the same as the frame start time and an end time that is before the frame end time. Prior to transmission of the frame of interleaved information bits to a decoding site, all bits in the frame are encoded at a code rate R to provide encoded bits, and the encoded bits are positioned in the interleaved frame in accordance with an interleaving pattern that stores bits having a code rate R1 within a first fractional segment of the interleaved frame.

Abstract: Methods and apparatus for generating and performing digital communications using a randomized generatable interleaver. In accordance with one exemplary embodiment of the invention, a pseudo random interleaver of size n*m with excellent randomness and spread properties may be generated from a set of seed values. The interleaver of size N=n*m is defined by dividing the N possible address in the interleaver (0-N?1) into n subsets. The subsets are preferably generatable from a single value within the subset either using an algorithm or a memory based lookup table. The set of n seeds comprises one value selected from each subset. An improved communication system incorporating the aforementioned interleaver and using turbo codes or other concatenated coding systems is also disclosed.

Abstract: A block interleaving/de-interleaving method and address generator thereof. The block interleaver segments the coded symbols into blocks according to a predetermined column value (C). The interleaver reads the coded symbols of each block by jumping according to the corresponding values (T0:TC-1) of a sequence matching table and the column value, and writes the values in sequence. The block de-interleaver reads the coded symbols sequentially, and re-assembles the coded symbols in the original order according to the same column value (C) and sequence matching table as the interleaver.

Abstract: A method is provided for testing the entire memory address range of memory in a computer system having a Cpu supporting 32-bit or 36-bit memory addressing. If the CPU supports 36-bit addressing a page directory is created containing entries that support accessing the memory according to a maximum page size supported by the processor. If the processor supports 32-bit memory addressing, a page directory and one or more page tables are created for accessing the memory according to a maximum page size supported by the processor. Once the page directory and page tables have been created, they are utilized to access and test a portion of the memory. The page directory and page tables are then dynamically modified to allow access to other portions of the memory.

Abstract: A Dynamic Storage Subsystem Morphing (DSSM) mechanism (40) is connected to a plurality of storage subsystem resources, which reserve some storage area each non-donor ECU (12), ready for a “slot-down/up” access by a respective non-donor ECU having a storage subsystem (24) breakdown. The slot-down process enables the use of a high physical address range by the non-donor processor provided with addressing capabilities sufficient only for addressing lower ranges.

Abstract: Each signal generating circuit for generating a CS signal, an address signal, a data signal or an R/W signal of a memory to be tested, and a test setting control circuit for generating a control data of these signal generating circuits are provided. The signal generating circuits and the test setting control circuit have shift registers, and a control data and a test data are serially input to these shift registers from external terminals.

Abstract: A system and method for interleaving data in a wireless transmitter wherein bits from the input data stream are sent to downstream processing without being stored in memory. According to a first example embodiment of the present invention, a first radio frame of data from an input code block is sent downstream, and the remaining radio frames from the code block are stored in the memory buffer. The first interleaving pattern can be applied, for example, as data is written to or read from the memory buffer. The stored radio frames are then read out as needed by the downstream processing. According to a second example embodiment of the present invention, further savings in memory can be achieved by discarding bits that are not currently needed for processing then recalculating them at a later time. A first radio frame of data from an input code block is sent downstream without being stored in the memory buffer.

Abstract: An apparatus and a method for performing a bit de-collection according to a hybrid automatic retransmission request are disclosed. The apparatus includes a column counter for increasing one column every four bits and outputting a position of a current column in response to received bit sequences; a state detector for outputting state information of the current column by means of an output value of the column counter, a parameter denoting a number of rows to which systematic bits have been assigned, and a parameter denoting a number of columns to which the systematic bits have been assigned; and address generators for generating write addresses required for performing a write operation and read addresses required for performing a read operation according to the state information output from the state detector.

Abstract: A P-BRO interleaver and a method for optimizing parameters according to an interleaver size for the P-BRO interleaver. The P-BRO interleaver sequentially, by columns, arranges an input data stream of size N in a matrix having 2m rows and (J?1) columns, and R rows in a Jth column, P-BRO interleaves the arranged data, and reads the interleaved data by rows.

Abstract: In a method and system for cycling through addresses of a memory device, a respective bit pattern comprised of a predetermined number of bits is generated for each address. The respective bit pattern for each of the addresses is cycled through with a transition of less than the predetermined number of bits for sequencing to each subsequent address. For example, the respective bit pattern for each of the addresses is cycled through in a gray code sequence. By limiting the number of transitions in the address bits, charge gain failure of a flash memory device is minimized and even may be eliminated.

Abstract: A method and apparatus is provided which reduces the equipment and time requirements for hard disk drive performance testing during manufacturing. This invention executes self-contained performance testing code that resides within the drive's manufacturing firmware, rather than relying on external testers. The invention involves exercising the drive's enqueue, dequeue, and command execution firmware, as well as the physical process of reading and writing data by simulating the host interface in code. The invention enqueues commands that typify the desired workload, allows a command ordering algorithm to sort the commands for execution, and allows the drive side code to execute the commands just as if an external host interface were attached. The invention is advantageous because the performance testing can be done by only applying power to the drive. The present invention also lends itself to performance tuning that can be done in manufacturing, to reduce drive-to-drive performance variations.

Abstract: There are provided a plurality of bridge circuits which convert the test data information from a common test bus connected to a plurality of memories of different access data widths and address decode logics to the inherent access data widths of each memory and also convert the test address information from the common test bus to the inherent bit format of each memory to supply the result to the corresponding memory. The test address information is supplied in parallel from the common test bus to a plurality of memories to realize the parallel tests. Accordingly, the test data information can be supplied in parallel to a plurality of memories of different data widths and the address scan direction in the respective memories for the test address information can be uniformed to the particular direction depending on the inherent bit format. Thereby, the memory test efficiency by the match pattern for a plurality of on-chip memories can be improved.

Abstract: An interleaving order generator for a turbo encoder/decoder prevents bottlenecks incurred when temporarily storing a generated interleaving pattern. An interleaving order generator, an interleaver, a turbo encoder, and a turbo decoder realizes a minimum parameter transfer to reduce bottlenecks in the interface, even when the data rate is varied and the interleave length is frequently changed. The interleaving order generator enables a sufficient data transfer rate for providing multi-media services.

Abstract: An interleaver is disclosed for a turbo encoder in an UMTS. The interleaver includes a register for updating and registering a plurality of parameters for setting an operating condition of the interleaver; a controller for generating a control signal for controlling an operation of the system by receiving the operating condition from the register; an address calculator for generating a finally interleaved address using an inter-row permutation pattern T(j), an intra-row permutation pattern increment arrangement value incr(j) and an intra-row permutation basic sequence s(i), provided from the register according to the control signal generated by the controller; and a data storage for sequentially storing data input to the turbo encoder and outputting data corresponding to the address generated by the address calculator.

Abstract: Systems (1) with interleavers (2) for interleaving data units and with de-interleavers (3) for de-interleaving data units, are made more efficient and less complex by storing data units in the form of stacks in the memories (29,39) of said interleavers (2) and said de-interleavers (3), by calculating stack positions for data units to be (de)interleaved, and by adapting stacks through shifting before the interleaving or after the de-interleaving. Such a system (1) does not require more than [(N?1)(D?1)]/2 memory elements, the theoretical memory size for the block length N and the interleaving depth D. Said data units are stored at subsequent positions, with said data units at said subsequent positions being adapted through shifting before the interleaving or after the de-interleaving to further subsequent positions. An interleaver (2) comprises a calculator (21), a shifter (23) and an inserter (24). A de-interleaver (3) comprises a calculator (31), an extracter (34) and a shifter (33).

Abstract: A P-BRO interleaver and a method for optimizing parameters according to an interleaver size for the P-BRO interleaver. The P-BRO interleaver sequentially, by columns, arranges an input data stream of size N in a matrix having 2m rows and (J?1) columns, and R rows in a Jth column, P-BRO interleaves the arranged data, and reads the interleaved data by rows.

Abstract: The present invention provides methods for generating self-inverting turbo code interleavers having high separation and high dispersion characteristics. Methods are provided for deterministically generating self-inverting turbo code interleavers from a specification for an existing non-self-inverting interleaver. Methods are also provided for randomly generating self-inverting turbo code interleavers. The present invention also provides methods and apparatus for encoding digital data and communicating the digital data using self-inverting turbo code interleavers/de-interleavers.

Abstract: Method and system for testing a memory array having a non-uniform binary address space. The test system includes a test engine for generating addresses for the memory array and for generating and applying data patterns to the memory array. The test engine has an address generator including a series combination of a linear register and a binary counter for generating the non-uniform address.

Abstract: A turbo encoder includes a memory for temporarily storing an incoming data sequence and an interleaved address generator (IAG) designed to generate a sequence of addresses corresponding to the interleaved data sequence. The IAG performs calculations based on the length of the incoming data sequence and is able to generate a first interleaved address by (or before) the time the incoming data sequence has completely shifted into the memory. As a result, the encoder begins to output encoded data substantially as soon as the corresponding incoming data have been received, thus substantially reducing the processing delay. In addition, each interleaved address can be generated on the fly as needed during data output. As a result, the entire set of interleaved addresses does not need to be stored, thus reducing the memory requirements for the encoder.

Abstract: A deinterleaver for performing high-speed multi-channel forward error correction using external SDRAM is provided. According to one exemplary aspect, the deinterleaver performs both read and write accesses to the SDRAM that are burst-oriented by hiding active and precharge cycles in order to achieve high data rate operations. The data bus length of the SDRAM is designed to be twice the deinterleaving symbol size thereby allowing bandwidth to be increased. The deinterleaver accesses data in the SDRAM as read blocks and write blocks. Each block includes a predetermined number of data words to be interleaved/deinterleaved. The ACTIVE command for one block is issued when a preceding block is being processed. Data in one read/write block has the same row address within the same bank of the SDRAM.

Abstract: An interleaver (11b) for filling an interleaver matrix (51) used in interleaving a packet of bits for transmission as symbols via a wireless communication channel in a wireless communication system (11 12) including a modulator (11c), the interleaver (11b) having a number of rows (or columns, depending on whether bits are pulled column-wise or row-wise for encoding as symbols by the modulator) that is not divisible by the number of bits in a symbol, but having at least as many bits as in a packet, and so having, unavoidably, more elements than there are bits in a packet.

Abstract: A memory-efficient convolutional interleaver/deinterleaver with a memory array, a write commutator, and a read commutator wherein the commutators perform their respective write and read operations relative to a preselected memory cell after a predetermined delay. The delay is chosen using a modulo-based technique, such that an efficient implementation of a Ramsey Type-II interleaver is realized.

Abstract: Efficient address generation for interleaver and de-interleaver. The present invention performs interleaving and de-interleaving, at opposite ends of a communication channel, by employing an efficient address generation scheme that is adaptable across a wide variety of applications and platforms. The present invention is particularly applicable to communication channels that exhibit a degree of bursty type noise. By employing interleaving and de-interleaving at the opposite ends of the communication channel, the present invention is able to offer a degree of protection against data corruption that may be caused within the communication channel. The present invention allows convolutional interleaving and de-interleaving operation on a code word by code word basis. The present invention provides for very efficient address generation for RAM based convolutional interleaving and de-interleaving.

Abstract: In a method for deinterleaving a data signal interleaved in blocks in accordance with a prescribed interleaving specification, deinterleaving target addresses are calculated for a first prescribed segment of the data symbols to be deinterleaved, and are stored in a target address memory. The relevant segment of the data symbols is then deinterleaved by using the calculated target addresses. Subsequently, these two steps are repeated until the entire data block has been segmentally deinterleaved.

Abstract: In an apparatus such as a turbo decoding apparatus in which it is necessary to carry out interleave operation and deinterleave operation, there are provided a memory unit (5) and a memory control unit (12) capable of changing data writing order and data reading order with respect to the memory unit (5) depending on whether data is to be interleaved or deinterleaved. With this arrangement, the single unit of memory (5) can function as an interleaver and a deinterleaver, thereby reducing the size and cost the device.

Abstract: A method for managing page-based data storage media such as flash media, a system that uses that method, and a computer-readable storage medium bearing code for implementing the method. New data are written to the storage medium in a manner that precludes corruption of old data if the writing of the new data is interrupted. Specifically, risk zones are defined, by identifying, for each page, the other pages whose data are put at risk of corruption if writing to the page is interrupted. A page, that otherwise would be the target of a write operation, is not written if any of the pages in its risk zone contain data that could be corrupted if the write operation is interrupted.

Abstract: A signal record reproduction device 1 of the invention comprises a microcomputer 12 and a memory 17. A series of data blocks are divided into a plurality of items of element data. The element data is interleaved and stored to the memory 17. A memory incorporated in the microcomputer 12 stores a table and a function expression for deriving address data representing an address to store each element data in memory regions positioned sufficiently apart one another in address space.

Abstract: A method and apparatus is provided for efficient processing of signal in a communication system. The processing of the signal for transmission may include encoding a block of data at an encoding rate 1/R. The encoding produces R number of data symbols for every data bit in the block of data. A block of RAM (299, 600) is partitioned into a plurality of blocks of RAM to allow reading simultaneously data symbols from the plurality of blocks of RAM to produce an in-phase and a quad-phase data symbols simultaneously. At least two scramblers (306 and 307) are used for simultaneously scrambling the in-phase and quad-phase data symbols. A Walsh covering/summing block (700) followed by the scramblers provides efficient Walsh covering and summing of signals for a combined transmission from the communication system.

Abstract: A memory optimized system and method for data interleaving/de-interleaving are disclosed. A data interleaver/de-interleaver may be implemented with a memory device and an improved data interleaver/de-interleaver. The improved data interleaver/de-interleaver may be implemented with a controller, a first array, and a second array. The first array identifies a maximum depth value for each of a plurality of memory segments responsive to both a block data length and the desired interleaving/de-interleaving depth. The second array comprises an index associated with each of the plurality of memory segments that may be used to derive write and read addresses.

Abstract: A method and apparatus for encoding multiple bits in parallel wherein outputs are generated recursively. During each clock cycle, the encoder processes multiple bits and generates outputs consistent with those generated sequentially over multiple clock cycles in a conventional convolutional encoder. In one embodiment, input data is stored in multiple memory storage units, which are then each uniquely addressed to provide data to parallel encoders.

Abstract: In an interleaver for use in a turbo decoder, a deinterleaver, or an interleaver for use in a turbo encoder, an offset is set based on previously determined thresholds in accordance with symbol numbers generated by a counter. A symbol numbers inputted immediately before generating an address is corrected with the set offset, and the corrected symbol number is converted to generate an interleave read address.

Abstract: A method for interleaving data frames transmitted via a modem pool, each of the data frames including a plurality of codewords having a predefined level of error correction, including assigning the data frames to corresponding modem timeframes, where codeword symbols in each of the data frames are assigned to time slots in the modems in the corresponding timeframes such that the level of error correction is sufficient to correct error/loss caused to any of the symbols given a predefined level of modem loss/malfunction, and moving any of the codeword symbols assigned to one of the timeframes to another of the timeframes such that the level of error correction is sufficient to correct error/loss caused to any of the symbols given a predefined level of cross-modem error burst while preserving the level of error correction sufficient to correct error/loss caused to any of the symbols given the level of modem loss/malfunction.

Abstract: Disclosed is a device and method such that data of size S is stored in a memory of size K, a two-dimensional matrix with R rows and C columns, and interleaving indexes I are generated according to a predetermined interleaving rule to randomly output the data from the memory. If a first index I is greater than data size S, a second index is generated and output prior to outputting invalid data stored in the memory at the location of the first index.

Abstract: An interleaver that implements the LCS turbo interleaver algorithm utilized by the CDMA2000 standard is described. The interleaver includes a first computation unit for receiving an input address and computing a first sequential interleaved address during a first clock cycle in response thereto. A second computation unit is included for receiving an input address and computing a second sequential interleaved address during the first clock cycle in response thereto. The interleaver further includes a comparator for determining whether the first or the second sequential interleaved address is invalid and generating a signal in response thereto. The output of the comparator provides a control signal to a switch which selects the first or the second sequential interleaved address as an output interleaved address for the first clock cycle. The interleaver is further designed to move in a forward direction or a reverse direction.

Abstract: An interleaver for interleaving a set of K ordered elements is disclosed herein. The disclosed interleaver can be expressed as a single permutation that corresponds to two local dithering operations and a global permutation operation. The single permutation can be represented as a small collection of short vectors, and can be calculated recursively, allowing the interleaver to be both stored and implemented using a smaller amount of memory than conventionally possible.

Abstract: A communication system 100 employs turbo encoding having a turbo interleaver 106 that interleaves input data 101 efficiently with little use of system resources. The turbo interleaver 106 reads address locations of the data bits into an interleaver matrix array 206 row by row and interleaves the address locations by bit reversal of the row indexes with accompanying permutation of the corresponding address locations in the rows of the matrix 206, bit reversal of the column indexes with accompanying permutation of the corresponding address locations in the columns of the matrix 206 and shifting the address locations within each row a predetermined number of column locations based on the particular row number.

Abstract: Memory may be partitioned into ever-sliding FIFOs. Each of the FIFOs may be stacked end-to-end in memory with the oldest data at the base offset and the newest at the end (or vice-virsa). Each symbol, the pointer may be incremented (modulo the set size) by an appropriate amount (typically J more than for the previous symbol). After each set, the pointers may be incremented by J more than the previous increment and the process starts over, wrapping around the memory if the end of the memory is reached. After a preset number of symbols, the process may restart from an increment of J. Alternatively, the pointers may be decremented rather than incremented. Thus, the newest symbol cannibalizes the memory position vacated by the oldest symbol in the current FIFO, causing the FIFOs to “slide”, providing for a very efficient and reliable use of memory for error-correcting code interleaving.

Abstract: A memory mapping method for mapping a data array into a memory. The memory mapping method provides the two-directional access in the data array. The memory mapping method first equally divides each row of the data array into some basic units based on the number of the columns of the data array. Next, a predetermined number of adjacent basic units in the same column are arranged into a basic memory block. Finally, the basic memory blocks are mapped into the memory.

Abstract: A convolutional interleaver includes an interleaver memory partitioned into a plurality of circular buffers, wherein each of the circular buffers has associated write pointers and read pointers, and wherein the interleaver is configured to selectively read symbols from an input vector and store the input symbols in the interleaver memory in accordance with the write pointers, and to selectively read symbols from the interleaver memory to form an output vector in accordance with the read pointers. In one aspect, symbols are written to the interleaver prior to reading; in another, the position of the write pointer corresponds to the position of the read pointer within the circular buffer, and symbols are read from said interleaver memory prior to writing. In another aspect, a de-interleaver applies the concepts and algorithms described above in an inverse manner.

Abstract: A system (10) implements user programmable addressing modes in response to control information contained within an input address. Encoded control information stored in a plurality of user programmed address permutation control registers (70-72) is used to determine what bit values are used to replace predetermined bits of the input address to selectively create a corresponding permutated address. Since no modification to a processor's pipeline is required, various permutation addressing modes may be user-defined and implemented using either a general-purpose processor or a specialized processor.

Abstract: A computer system includes instruction fetch circuitry for dispatching fetched instructions to a pipelined execution unit, data memory access circuitry and emulator circuitry for use in debug operations, said emulator circuitry including error indicating circuitry to indicate an error in a data memory access operation, snoop circuitry for snooping memory access operation in said data memory access circuitry, synchronising means for synchronising snooped data memory access addresses with respective program counts for the instructions associated with said access addresses, memory mapped storage circuitry responsive to a data memory access error to indicate the data memory address associated with the error, whereby the emulator circuitry may use the data memory address in a subsequent operation to obtain from the synchronising means the specific program count associated with the memory access operation in which the error occurred.

Abstract: A method and apparatus is provided for interleaving and de-interleaving frame symbols using a single memory buffer. Input frame symbols are read out in an interleaved sequence (or de-interleaved sequence) on a symbol by symbol basis. Frame symbols following the input frame symbols are written into memory locations from where the input frame symbols were read.

Abstract: An address generator for generating addresses in a prescribed order in the case of writing/reading data to/from a predetermined storage unit includes a first address data generator for generating a plurality of first address data which have predetermined address intervals, a second address data generator for generating a plurality of second address data representing sequentially shifted positions of the first address data one row by one row within address intervals, and an adder for generating addresses that have predetermined intervals by adding the second address data to the first address data.

Abstract: The invention is directed to techniques that include an error detection code (e.g., a CRC code) and cleared bytes (e.g., zeroes) with data (e.g., CKD data). The use of cleared bytes with CKD data enables detection of corrupt CKD data by simply generating a CRC code based on an entire data block and comparing that generated CRC code with an initial CRC code appended to the CKD data within that data block. One arrangement of the invention is directed to a data storage system that includes a circuit having a memory pipeline that receives a stream of data elements, and provides a series of byte groups that includes the stream of data elements, an error detection code and a set of cleared bytes to a set of storage devices. Each of the series of byte groups provided by the memory pipeline has a same byte width. The inclusion of the error detection code and the set of cleared bytes enables consistent alignment of each byte group in the series.

Abstract: Memory about 4 Gbytes is tested using a DOS diagnostics program that remaps memory to a 32-bit addresses. In some embodiments, memory above 3 Gbytes is tested in 1 Gbyte blocks until the end of memory is reached using a physical address extension that extends addresses from 32 bits to 36 bits. Testing is done concurrently by all processors.

Abstract: A device for generating L addresses, which are smaller in number than 2m×Ng virtual addresses, for reading data from an interleaver memory in which L data bits are stored, the device including: Ng PN generators each including m memories; an address generator for adding an offset value to the input data size to provide a virtual address having a size of a multiple of 2m, and generating addresses other than addresses corresponding to the offset value in address generation areas using the address generation areas having the size of 2m; and means for reading the input data from the interleaver memory using the addresses generated from the address generation areas.

Abstract: A method for improving data accuracy and data flow of a disc servo system to read data on a disk. First of all, a read mode of the disc servo system is determined. If the read mode is an audio/video play mode, a first read procedure to read the data on the disk is executed. If the read mode is a document read mode, a second read procedure to read the data on the disk is executed. The second read procedure is different from the first read procedure. Finally, the data is output to further processes.

Abstract: A method and apparatus is provided for efficient processing of signal in a communication system. The processing of the signal for transmission may include encoding a block of data at an encoding rate 1/R. The encoding produces R number of data symbols for every data bit in the block of data. A block of RAM (299, 600) is partitioned into a plurality of blocks of RAM to allow reading simultaneously data symbols from the plurality of blocks of RAM to produce an in-phase and a quad-phase data symbols simultaneously. At least two scramblers (306 and 307) are used for simultaneously scrambling the in-phase and quad-phase data symbols. A Walsh covering/summing block 700 provides efficient Walsh covering and summing of signals for a combined transmission from the communication system.