Abstract: A method for testing the data strobe window (DQS) and data valid window (tDV) of a memory device (e.g., a DDR-type memory device) using the window strobe of a testing system.

Abstract: A code error correcting circuit interleaves original data comprising a sequence of bit data having a length of p bits by arranging the bit data of the original data into a hypothetical matrix of I rows and J columns and then selecting the bit data positioned on the ith row along an order of the jth column. The circuit is provided with a memory unit having a plurality of memory areas each having a length of 2n bits; and a controller for storing the original data to be interleaved into the memory areas respectively. The bit data, which are indicated by a bit select data, stored in the memory unit are sequentially outputted along an order of the ith row and the jth column in the hypothetical matrix as the interleaved original data.

Abstract: A memory-efficient convolutional interleaver/deinterleaver with a memory array, a write commutator, and a read commutator wherein the commutators perform their respective write and read operations relative to a preselected memory cell after a predetermined delay. The delay is chosen using a modulo-based technique, such that an efficient implementation of a Ramsey Type-II interleaver is realized.

Abstract: A method for interleaving input data having a size other than a multiple of 2m (m>1) is disclosed. The method comprises sequentially storing input data in a memory; adding an offset value to the input data size to provide a virtual address having a size of 2m where (m>1); defining a plurality of address generation areas each having a size of 2m m where (m>1), and generating random addresses in the address generation areas; and reading the input data from the memory using the random addresses generated from the address generation areas.

Abstract: A multiple coding apparatus comprises a first encoder for encoding a plurality of input sequences in parallel so as to generate a plurality of output coded sequences in parallel while adding an error-correcting bit sequence to each of the plurality of input sequences. An interleaving circuit interleaves the plurality of output coded sequences applied thereto in parallel from the first encoder without having to use any memory. The interleaving circuit permutes the plurality of input sequences on a bit-by-bit or symbol-by-symbol basis so as to generate a plurality of interleaved coded sequences in parallel. A second encoder then encodes the plurality of interleaved coded sequences applied thereto in parallel from the interleaving circuit so as to generate a plurality of output coded sequences in parallel while adding an error-correcting bit sequence to each of the plurality of interleaved coded sequences.

Abstract: Methods and apparatuses are disclosed for creating a parameterized interleaver/de-interleaver megafunction for use in an electronic design, where the interleaver/de-interleaver megafunction requires specific setting of at least one variable parameter value. The method includes presenting a user with the opportunity to specify an adjustable parameter value for at least one interleaver/de-interleaver parameter. The specified parameter value then is received and a suitable interleaver and/or de-interleaver system is generated.

Abstract: A block interleaver is provided using a relatively small register file and a larger random access memory (RAM). In one embodiment, the size of the RAM is larger than the size of the register file by at least one order of magnitude. As a result, the register file consumes significantly less power than the RAM for similar operations. The register file receives a stream of sequential data values and stores the data values in a column order. The data values are then read from the register file in a row order. The data values read from the register file in a row order are then written to the RAM in a row order. The data values are then read from the RAM in a row order, thereby creating an interleaved data stream. In a particular embodiment, the data values are written to the RAM in a staggered row order and read from the RAM in a sequential row order. All accesses to the RAM are performed using the full width of the RAM, such that no unnecessary power is used to access the RAM.

Abstract: A bandwidth disparity often exists between the front side bus bandwidth and the memory interface bandwidth. The invention effectively increases the bandwidth of a memory interface bandwidth for increasing central processing unit performance. In one aspect, data is buffered by a memory controller hub and compressed by dropping data elements if repetitious data elements appear in a data stream. The dropped data elements are indicated by tagging a previous data element for later recovery. In another aspect, tagging is provided by modifying error correction code bits of the tagged data element or by modifying the data elements. In another aspect, dropped data elements are detected by identification of an error correction code, the dropped data elements reinserted into the data stream, and the data buffered before being presented to a front side bus.

Abstract: An address generator and an address generating method are described. In the address generator, a first counter counts a plurality of clock pulses, generates a first group count, which indicates one of the group addresses of an interleaver block, at each clock pulse, and generates a carry after counting a predetermined number of clock pulses. A second counter receives the carry from the first counter, counts the plurality of carries, and generates a position count indicating one of the position addresses in each group. If the group count is one of the unavailable group count values representative of unavailable groups, or the group count is one of partially unavailable group count values representative of groups having both available and unavailable position addresses and the first position count is one of unavailable position count values representative of unavailable position addresses, a controller controls the first and second counters not to output the first group count and the first position count.

Abstract: A flexible built-in self-test (BIST) circuit is incorporated into an integrated circuit (IC) for testing one or random access memories or other memories embedded in an integrated circuit regardless of the number, size or test requirements of the memories. Input data from a controller that may be conveniently partitioned among components internal and external to the IC, supplies data to the BIST circuit indicating the size of the embedded memories to be tested and selecting from among several modes of BIST operation.

Abstract: A code word includes a first group of data bits and includes code bits that represent a second group of data bits. One embodiment of the code word has a minimum probability of bit transitions among its bits. Another embodiment of the code word includes a parity bit. Unlike conventional codes, a code that includes such a code word can have both a high efficiency and small error propagation. Additionally, by including fewer bit transitions, a sequence of such code words causes less read noise, and thus causes fewer read errors as compared to sequences of known code words. Moreover, the code word can include a parity bit to allow improved error detection as compared to known error-detection techniques. Therefore, such a code word can significantly increase the effective write and read speeds of a disk drive.

Abstract: A method and system are provided for improving efficiency of storing and accessing data blocks for systems that are limited to small size, host accessible data blocks, such as having a maximum size of 512 bytes, by allowing larger size subsystem data blocks to be created from the smaller size logical data blocks. A host command is analyzed to determine whether the host accessible logical data block aligns with the larger subsystem block. If so, the larger block(s) is(are) sent to the host. If the command does not align, the larger block is processed into a plurality of segments so that the addressed data block(s) can be aligned, and any error correction coding verified. The present invention allows a subsystem to store and manage efficiently sized blocks of data while still supporting a host's need to access smaller, single architecturally defined addressable blocks.

Abstract: A method and apparatus is provided for interleaving and de-interleaving frame symbols using a single memory buffer. Input frame symbols are read out in an interleaved sequence (or de-interleaved sequence) on a symbol by symbol basis. Frame symbols following the input frame symbols are written into memory locations from where the input frame symbols were read.

Abstract: An interleaving method including the step of (1) receiving a data sequence having a plurality of blocks, each having a length based on a prime number P; (2) generating sequence permutation data by performing a given operation on elements of a Galois field of a characteristic P; (3) permuting results of the given operation, so that sequence permutation data are generated; and (4) permuting a sequence of data of the data sequence in accordance with the sequence permutation data.

Abstract: A multi-bit-per-cell memory reduces the effect of defects and data errors by scrambling data bits before writing data. The scrambling prevents storage of consecutive bits in the same memory cell. When a memory cell is defective or produces an error, the bits read from the memory cell do not create consecutive bit errors that would be noticeable or uncorrectable. An error or a defect in a multi-bit memory cell causes at most scattered bit errors. Scramblers in multi-bit-per-cell memories can include 1) hardwired lines crossing between an input port and an output port, 2) programmable wiring options, 3) a linear buffer where reads from the buffer use addresses with swapped bits, or 4) a buffer array that switches between incrementing a row address first and incrementing a column address first when accessing memory cells in the buffer array.

Abstract: A decoding circuit used to correct an error in a digital signal comprises: an input unit for entering coded digital signals ID in parallel in accordance with the number of interleaved codes; a processor including an error locator polynomial calculator and an error value polynomial calculator for processing data obtained serially from the interleaved codes that are received by the input unit; and an output unit for correcting errors by employing the output data that are received from the processor and the digital signals ID, and for outputting in parallel the obtained digital signals OD, for which an error has been corrected by a linear calculation on a Galois field, in accordance with the number of interleaved codes.

Abstract: Memory address generation apparatus 12 generates memory addresses, multiplier 15 reads from memory 14 storing row transposition patterns of a matrix a row transposition pattern value corresponding to the row number outputfrom row counter 11 and calculates an address offset value by multiplying the transposition pattern value of the read row by the number of columns of the matrix, adder 16 reads from memory 13 storing row transposition patterns of the matrix a column transposition pattern value corresponding to the memory address generated by the memory address generation apparatus and generates an interleave address by adding up the transposition pattern value of the read column and the address offset value.

Abstract: A method and system for efficiently implementing an error correction code scheme. In one embodiment of the present invention, a system comprises a processor configured to process frames of data. Each frame of data may be associated with a frame control block. The processor comprises a first queue configured to store one or more frame control blocks associated with one or more frames of data. The processor further comprises a second queue configured to store one or more frame control blocks not associated with a frame of data. The one or more frame control blocks associated with one or more frames of data in the first queue comprise a bit for storing a parity bit. The one or more frame control blocks in the second queue comprise a plurality of bits for storing a code of an error correction code scheme.

Abstract: A method encodes an input data block with a block encoder. The block encoder is capable of processing consecutive coding blocks whose size has an upper limit which is smaller than the size of the input data block. The method comprises: determining the length of the input data block before encoding any of its data with the block encoder; dividing the input data block to a plurality of segments wherein all segments are of substantially equal size and no segment is larger than the upper limit; and processing each segment with the block encoder. If the last segment is shorter than the remaining segments, fill bits can be added to the last segment such that its length equals that of the remaining segments.

Abstract: A method for creating a high efficiency, error minimizing code is provided. In addition, an apparatus having a high efficiency, error minimizing code is provided. In particular, the present invention provides a high efficiency, error minimizing code for use in connection with systems having a communication channel in which identifiable dominant errors occur, and that is used to transmit data that may be usefully applied in the system even though the received signal is not exactly equal to the original signal. Furthermore, the present invention provides a code that may be used to constrain the effects of dominant errors in a communication channel.

Abstract: A method and a system for performing memory-based convolutional interleaving are disclosed. According to the disclosed method, delay lines (DL) are paired with one another within rows of a memory, where the pairing is effected so that the sum of the delay of the paired delay lines is constant over the rows. Both in transmission and in receipt of the interleaved data packets, one or more data packets are read from the oldest location of one of the paired delay lines, with one or more data packets from a received vector being written into this delay line; this reading and writing is repeated for each of the rows of the memory, advancing in a first direction. The process of reading and writing is then repeated for the other delay line in each of the rows of the memory, advancing in the opposite direction. The pairing of the delay lines (DL) in each row of the memory permits efficient implementation of convolutional interleaving, with a minimum of overhead processing required.

Abstract: A method of interleaving blocks of indexed data of varying length is disclosed. The method includes the steps of: providing a set of basic Interleavers comprising a family of one or more permutations of the indexed data and having a variable length; selecting one of the basic Interleavers based upon a desired Interleaver length L; and adapting the selected basic Interleaver to produce an Interleaver having the desired Interleaver length L.

Abstract: There are provided a digital signal forming method, a disc recording medium for high density recording and a method of reproducing a digital signal for encoding of the error correction code of the related art and improving the error correction capability without any requirement in change of the number of codes.

Abstract: The required RAM capacity is reduced by dividing an interleaving RAM in a baseband modulator into a plurality of areas and having the read side and the write side use some common areas on a time-sharing basis.

Abstract: An interleaver that implements the LCS turbo interleaver algorithm utilized by the CDMA2000 standard is described. The interleaver includes a first computation unit for receiving an input address and computing a first sequential interleaved address during a first clock cycle in response thereto. A second computation unit is included for receiving an input address and computing a second sequential interleaved address during the first clock cycle in response thereto. The interleaver further includes a comparator for determining whether the first or the second sequential interleaved address is invalid and generating a signal in response thereto. The output of the comparator provides a control signal to a switch which selects the first or the second sequential interleaved address as an output interleaved address for the first clock cycle. The interleaver is further designed to move in a forward direction or a reverse direction.

Abstract: A communication system 100 employs turbo encoding having a turbo interleaver 106 that interleaves input data 101 efficiently with little use of system resources. The turbo interleaver 106 reads address locations of the data bits into an interleaver matrix array 206 row by row and interleaves the address locations by bit reversal of the row indexes with accompanying permutation of the corresponding address locations in the rows of the matrix 206, bit reversal of the column indexes with accompanying permutation of the corresponding address locations in the columns of the matrix 206 and shifting the address locations within each row a predetermined number of column locations based on the particular row number.

Abstract: The present invention is a novel and improved technique for performing coding with particular application to turbo, or iterative, coding techniques. In accordance with one embodiment of the invention, interleaving is performed by generating the address of a memory using a PN state generator. Data is written into a memory in sequential order, and then read out using addresses specified by the PN state generator. To deinterleave, the interleaved data is written into a memory using addresses specified by the PN state generator, and then read out in sequential order. A set of PN state generators that provide excellent coding performance is provided.

Abstract: A method is provided for secured transfer of an N-byte data element from a first memory containing the data element to a second memory through a data bus that is connected between the first memory -and the second memory. According to the method, a transfer rule is defined with at least one parameter whose value is chosen at random before each transfer of the data element. The N-byte data element is transferred byte-by-byte through the data bus in accordance with the transfer rule, with each byte transiting once and only once through the data bus. In a preferred method, the transfer rule is a permutation of the bytes of the N-byte data element. Also provided is a programmable circuit having a random number generator that supplies at least one parameter of a data transfer rule.

Abstract: A magnetic recording and/or reproducing apparatus in which the decoding error rate is to be lowered through realization of the high-performance encoding and the high efficiently decoding. To this end, a magnetic recording and/or reproducing apparatus 50 includes, in its recording system, an error correction coder 51 for error correction encoding input data, an interleaver 52 for interleaving data supplied from the error correction coder 51 for re-arraying the data sequence, a modulation encoder 53 for modulation encoding the data from the interleaver 52 in a predetermined fashion and an interleaver 54 for interleaving the data from the modulation encoder 53 for re-arraying the data sequence.

Abstract: A novel and improved method and apparatus for address generation in an interleaver is provided. In accordance with one embodiment of the invention, an address is generated using a random address fragment and a bit reversed address fragment. The bit reversed address fragment is selected by first generating two consecutive candidate bit reversed fragments. The second bit reversed address fragment is selected when the first bit reversed address fragment generates an address that is greater than a maximum address. The address generator allows address generation for interleaver and deinterleaver frame sizes of N, where N is not an integer power of two, without any cycle penalty.

Abstract: The present invention is a novel and improved technique for performing coding with particular application to turbo, or iterative, coding techniques. In accordance with one embodiment of the invention, interleaving is performed by generating the address of a memory using a PN state generator. Data is written into a memory in sequential order, and then read out using addresses specified by the PN state generator. To deinterleave, the interleaved data is written into a memory using addresses specified by the PN state generator, and then read out in sequential order. A set of PN state generators that provide excellent coding performance is provided.

Abstract: A circuit and method for producing defect tolerant high density memory cells at a low cost is disclosed. Rather than using redundant memory cells to salvage a memory circuit having non-functional memory cells, an address mapping circuit is used to remap addresses for non-functional memory cells into addresses for functional memory cells. Specifically, if the memory array of a memory circuit includes non-functional memory cells, an address mapping scheme is selected to reduce the effective size of the memory circuit so only functional memory cells are addressed. Because redundant memory cells are not included in the memory circuit, the semiconductor area and the cost of the memory circuit is reduced.

Abstract: The invention concerns a method and devices for the detection of errors, in particular transmission errors, in data streams and/or data packets. In order to better detect systematic errors in particular, the error detection function according to the invention is variable. The detection function is varied on the basis of the time and/or the data themselves, for example by assigning an individual variation value to each index (packet index), effectively varying the data themselves. The invention is particularly suitable for application to compressed data streams.

Abstract: A method for interleaving data frames, forward error correcting device and modulator including such a device, wherein each data frame to be interleaved is divided into a plurality of codewords, each containing the same amount of data bytes. An overhead extension is added to the codewords and additionally, the extended codewords are applied to an interleave buffer (IB) to be written in matrix-shaped structure of memory cells included in the interleave buffer (IB). This matrix-shaped structure is filled column by column in such a way that each codeword occupies another column. Data bytes are read out of the matrix-shaped structure row by row as a result of which the data frames are interleaved.

Abstract: The method described is distinguished in that overwriting return addresses stored for later use and/or using incorrectly stored or overwritten return addresses as a return address are prevented. This further prevents deliberate manipulation of program execution of software programs.

Abstract: A memory addressing scheme suitable for use for either interleaving or de-interleaving data bytes of, e.g., a broadcast digital television (DTV) data stream. A number of memory branches are configured in a random access memory (RAM), wherein at least some of the branches have different numbers of memory locations for reading out and for storing data bytes, thus defining memory branches of different lengths in the RAM. A start address is determined for each of the memory branches in the RAM, corresponding to a first memory location of each branch. An offset value is determined for each memory branch, to be added to the start address for the branch for addressing a memory location of the branch. If an offset value does not exceed the length of a corresponding branch, an address corresponding to the sum of the branch start address and the offset value is generated for addressing a successive memory location of the branch, and the offset value for the branch is incremented by one.

Abstract: A fault-tolerant computer architecture is described wherein the effect of hardware faults is diminished. The architecture employs a main data bus having a plurality of interface slots for interconnecting conventional computer sub-systems. The number and type of sub-systems may vary considerably, however, a central processor sub-system which encompasses the inventive elements of the invention is always included. The central processor sub-system employs a plurality of central processing modules operating in parallel in a substantially synchronized manner. One of the central processing modules operates as a master central processing module, and is the only module capable of reading data from and writing data to the main data bus. The master central processing module is initially chosen arbitrarily from among the central processing modules.

Abstract: A scheme for error control on AAL in ATM networks capable of realizing a reliable communication with a high throughput and a low latency. On AAL, the segmented data are sequentially written into each column of a matrix shaped data region in an interleaver, while variably setting a last column of the data region in the interleaver. Then, an error control code for the data up to the last column in each row of the data region in the interleaver is obtained and written into a corresponding location within a matrix shaped error control code region in the interleaver. The contents of each column of the data region and the error control code region in the interleaver are then read out, and a prescribed header/trailer is attached to a prescribed number of columns of the data and/or the error control codes read out from the interleaver to form a data unit.

Abstract: A convolutional interleaver for interleaving a data stream composed of N number of data with predetermined interleaving level B to randomize the data stream for an error correction, comprising: an input buffer; a memory; an address generating unit; an output buffer; and a controller, and a method for generating an address of the memory are disclosed. In the method for generating an address of the memory, a basic memory of which the number of vertical end is B-1 and horizontal length is (B-1).times.M cell is transformed to an intermediate memory of which the number of vertical end is B-1 and horizontal length is (B/2).times.M cell, and a physical address for accessing the intermediate memory is generated.

Abstract: An apparatus deinterleaves decoded symbols and outputs the deinterleaved symbols in an appropriate form for external devices. In order to achieve the deinterleaving and outputting processes, the apparatus sequentially stores the decoded symbols in response to enable signals and produces output data of P bits based on the stored decoded symbols by using two memory groups which alternately perform the storing and the producing processes. The operations of the two memory groups are controlled by an input control block and an output control block. The input control block produces the enable signals to control the two memory groups to thereby sequentially store the decoded symbols to the two memory groups. The output control block selects one of outputs provided from the two memory groups and provides the selected output as the output data of P bits.

Abstract: In an (de)-interleaver (201) for J long subsequences (640-646) of data units (612), FIFOs are mapped into a memory (245) in such a way that locations (240) needed for one FIFO are moving through the memory (245). A generator (208) modulo increments only a single pointer (p, 230) which activates memory locations (240-p). Thereby, increments .DELTA.j correspond to FIFO sizes. For some p, (de)-interleaver (201) reads (25) a data unit (612) from a location (240) and than writes a new data unit (612) into that location (240), thus saving set-up times to establish a pointer. Also, the (de)-interleaver (201) needs only a number of memory locations K=(D-1 ) corresponding to a (D-1) interleaving depth. The (de)-interleaver (201) as part of a system (200) is fully programmable and can transfer data in two directions. Also, (de-) interleaving parameters (D-1) and J can be reconfigured during data transmission.

Abstract: An electrically rewritable nonvolatile semiconductor memory device made in accordance with a preferred embodiment of this invention, includes CAM data setting means for storing CAM data electrically written therein, wherein the CAM data is received from an external source; address fixing means for fixing a signal level of a portion of an internal address corresponding to an external address input from an external source based on the CAM data set in the CAM data setting means; and address switch means for switching a corresponding relationship between a portion of the external address input from an external source and a portion of the internal address based on the CAM data set in the CAM data setting means.

Abstract: Apparatus that realizes a substantial advantage by employing implied interleaving to create a systematic interleaver, that can result in a superior block error rate compared to the current data interleaving techniques in which uncorrected error bursts are distributed by the deinterleaver. The disclosed principles lead to a embodiments that essentially eliminate transmitter memory regardless of the interleaving approach employed. By way of example, block interleaving (regular or random), convolutional interleaving (regular and random) and product interleaving approaches are described. In implied interleaving, all incoming data is treated as if it is pre-interleaved and transmitted directly to its destination without alteration to its sequence, and essentially without delay.

Abstract: The invention relates to a multi-level storage device including: at least a first plurality of cells storing an identical first number (greater than one) of binary data, and at least a corresponding for second plurality of cells for storing a second number of error check and correcting words equal to said first number, said words being respectively associated with sets of binary data, each including at least one binary data for each cell in said first plurality. In this way, many of the known error correction algorithms can be applied to obtain comparable results to those provided by binary memories. In addition, where multi-level cells are used for storing the error check and correcting words, the device dimension requirements can also be comparable.

Abstract: A data interleaving system (20) provides flexibility by performing the interleaving function in a high level controller (32) and a separate low level controller (34). The high level controller (32) receives commands to operate on a codeword basis, in which a codeword is made up of a plurality of symbols which are grouped into a programmable number of frames. The low level controller (34) operates under the direction of the high level controller (32) on a symbol-by-symbol basis. By separating the codeword level tasks from the symbol level tasks, the data interleaving system (20) is able to accommodate various ratios of the number of frames per codeword without significant complexity. An analogous data de-interleaving system (220) includes a high level controller (232) and a low level controller (234).