Testing Of Error-check System Patents (Class 714/703)
  • Patent number: 11069421
    Abstract: Error detection circuitry is configured to receive raw read data from a memory, perform error detection in accordance with a single-bit error correction and double-bit error detection (SECDEC) error-correction code (ECC) on the raw read data, and provide a single bit correction indicator in response to performing the SECDEC ECC on the raw read data. Error correction circuitry is configured to provide corrected read data corresponding to the raw read data based at least on the single bit correction indicator. ECC checking circuitry is configured to generate a wrong operation indicator based at least on a parity of the raw read data, a parity of the corrected read data, and the single bit correction indicator, wherein the ECC checking circuitry is configured to assert the wrong operation indicator when at least one of the error detection circuitry or the error correction circuitry is not operating correctly.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: July 20, 2021
    Assignee: NXP USA, Inc.
    Inventors: Jehoda Refaeli, Nancy Hing-Che Amedeo, Quyen Pho
  • Patent number: 11048602
    Abstract: An electronic device includes a syndrome decoder, an error insertion control circuit, and a failure detection circuit. The syndrome decoder generates an error insertion code from a write syndrome generated based on a write pulse. The error insertion control circuit inserts an error into an internal codeword according to the error insertion code based on a read pulse. The failure detection circuit compares the write syndrome with a read syndrome generated from the internal codeword to generate a failure detection signal.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: June 29, 2021
    Assignee: SK hynix Inc.
    Inventor: Jae In Lee
  • Patent number: 11044183
    Abstract: A network interface device, said network interface device has a data transmission path configured to receive data for transmission. The data for transmission is to be sent over a network by the network interface device. A monitor is configured to monitor the data transmission path to determine if an underrun condition is associated with the data transmission path. If so, an indication is included in the transmitted data packet.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: June 22, 2021
    Assignee: XILINX, INC.
    Inventors: Steven L. Pope, David J. Riddoch, Derek Roberts
  • Patent number: 10917326
    Abstract: According to one method for debugging test traffic generation, the method occurs at a test system implemented using at least one processor and at least one memory. The method includes generating test traffic, wherein generating the test traffic includes receiving routing information from a system under test (SUT) via at least one routing protocol, determining traffic header data using the routing information, and storing resolution processing path information indicating how the traffic header data was determined; and displaying, using a display, test traffic data, wherein displaying the test traffic data includes displaying at least some of the resolution processing path information for at least some of the traffic header data.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: February 9, 2021
    Inventors: Noah Steven Gintis, Alina Crina Balan, Vinod Joseph
  • Patent number: 10915082
    Abstract: To provide a microcontroller that suppresses increase of power consumption during debugging, a microcontroller according to the present invention includes a first signal processing circuit, a second signal processing circuit that performs signal processing in the same manner as the first signal processing circuit, a comparing circuit that compares a processing result of the first signal processing circuit and a processing result of the second signal processing circuit with each other, and outputs an error signal when an error is detected, a suppressing signal input unit that receives a suppressing signal for suppressing an operation of the second signal processing circuit and an operation of the comparing circuit, a suppressing circuit that receives the suppressing signal from the suppressing signal input unit and suppresses the operation of the second signal processing circuit and the operation of the comparing circuit, and a pseudo error signal output circuit that outputs a pseudo error signal in place of t
    Type: Grant
    Filed: July 29, 2018
    Date of Patent: February 9, 2021
    Assignee: Renesas Electronics Corporation
    Inventors: Takuro Nishikawa, Masaki Fujigaya
  • Patent number: 10910082
    Abstract: Apparatus comprises memory circuitry having a plurality of addressable memory entries storing respective data items and associated error protection codes; memory error protection circuitry to generate the error protection code for a data item stored to the memory circuitry, the error protection code for a given data item stored to the memory circuitry depending upon at least the given data item and a memory address defining a memory entry to which the given data item is stored, and to perform a check operation to check for consistency between a retrieved data item, the memory address defining a memory entry from which the given data item is retrieved and the error protection code associated with the retrieved data item; memory built-in self-test circuitry to test the memory and memory error protection circuitry; and access circuitry to provide an indirect access path between the memory built-in self-test circuitry a memory which accesses the memory circuitry via the memory error protection circuitry and a dir
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: February 2, 2021
    Assignee: Arm Limited
    Inventors: Alan Jeremy Becker, Loïc Pierron
  • Patent number: 10909013
    Abstract: A TTCN-based test system for testing test-cases is provided. The test system includes a test executable which includes a compiled TTCN code. A simulated device under test (DUT) includes a pre-recorded log-file which describes at least partially the behavior of the simulated DUT. A test runtime interface is provided between the test executable and the simulated DUT. A test computer (PC) is configured to perform the testing by executing the compiled TTCN code and by exchanging via the test runtime interface protocol messages with the simulated DUT during the execution of the compiled TTCN code. A TTCN-based test method for testing test-cases and a non-transitory computer-readable recording medium is also provided.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: February 2, 2021
    Assignee: ROHDE & SCHWARZ GMBH & CO. KG
    Inventor: Michael Eichhorn
  • Patent number: 10855412
    Abstract: A method of operating a semiconductor memory device can include receiving data, from a memory controller, at an Error Correction Code (ECC) engine included in the semiconductor memory device, the data including at least one predetermined error. Predetermined parity can be received at the ECC engine, where the predetermined parity is configured to correspond to the data without the at least one predetermined error. A determination can be made whether a number of errors in the data is correctable by the ECC engine using the data including the at least one predetermined error and the predetermined parity.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: December 1, 2020
    Inventors: Hoi-Ju Chung, Sang-Uhn Cha, Hyun-Joong Kim
  • Patent number: 10840897
    Abstract: A sine to square wave converter circuit receives a sine wave signal and supplies a first square wave signal having a first frequency. A 2× clock multiplier circuit multiplies the first square wave signal and supplies a second square wave signal with a second frequency that is twice the first frequency. A first storage element that is clocked by the second square wave signal stores a delayed version of the first square wave signal and supplies an even-odd signal. A second storage element that is clocked by the second square wave signal receives the even-odd signal and supplies an odd-even signal. A duty cycle correction circuit adjusts the threshold of the sine to square wave converter based on a difference in duty pulse widths between the even-odd signal and the odd-even signal.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: November 17, 2020
    Assignee: Silicon Laboratories Inc.
    Inventors: Aslamali A. Rafi, Srisai Rao Seethamraju, Russell Croman
  • Patent number: 10706950
    Abstract: Systems and methods disclosed herein provide for improved testing of memory error correction code (“ECC”) logic with memory built-in self-test (“MBIST”). Embodiments provide for a masking element to inject one or more faults into the ECC logic during at least one of a manufacturing test (“MFGT”) and a power-on-self-test (“POST”), wherein, based on the injected faults, it can be determined if the ECC logic contains any errors.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: July 7, 2020
    Inventors: Patrick Gallagher, Steven Lee Gregor
  • Patent number: 10698764
    Abstract: A semiconductor device includes a read data generation circuit and a syndrome generation circuit. The read data generation circuit generates first read data from first output data and a first output parity which are generated during a first read operation. In addition, the read data generation circuit generates second read data from second output data and a second output parity which are generated during a second read operation. The syndrome generation circuit generates a syndrome signal from the first read data and the second read data. The syndrome generation circuit generates the syndrome signal so that column vectors of a first half matrix corresponding to the first read data are symmetric to column vectors of a second half matrix corresponding to the second read data.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: June 30, 2020
    Assignee: SK hynix Inc.
    Inventors: Chang Hyun Kim, Yong Mi Kim
  • Patent number: 10664856
    Abstract: Techniques and systems for beacon triggered code redemption are disclosed. Such a technique can include causing a mobile device to listen for beacon messages broadcast by a beacon device over a short-range communication link; receiving a beacon message from the beacon device; and exchanging information with a content provider to retrieve a redemption code associated with the beacon message. A beacon message can include a beacon identifier and an activity parameter specifying a code redemption action. The beacon identifier can be associated with an event that will occur, is occurring, or has occurred in the vicinity of the beacon device. The technique can further include displaying on a screen of the mobile device, a notification in regard to redeeming the redemption code configured for redeeming content associated with the event.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: May 26, 2020
    Assignee: Apple Inc.
    Inventors: Gregory S. Robbin, Oliver Krevet, Jeremy C. Norberg, Claes S. Nygren
  • Patent number: 10613836
    Abstract: A method and system for improving an operation of an automated IT system is provided. The method includes identifying pre-tested software applications associated with requirements of processes executed by a hardware device with respect to an IT system. A list of available software applications associated with required features is generated and each feature is defined such that the currently available software applications are configured to provide and execute the required features. Evaluation code is executed and a resulting a list of validated software applications is generated. A list of short listed software applications and identification software code enabling an automated encoder learning process are generated. A software operational solution is identified and modification code is generated and executed resulting in improved operation of the validated software applications and the hardware device.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: April 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Harish Bharti, Rajesh K. Saxena, Balakrishnan Sreenivasan
  • Patent number: 10599514
    Abstract: Error correction code (ECC) hardware includes write generation (Gen) ECC logic and a check ECC block coupled to an ECC output of a memory circuit with read Gen ECC logic coupled to an XOR circuit that outputs a syndrome signal to a syndrome decode block coupled to a single bit error correction block. A first MUX receives the write data is in series with an input to the write Gen ECC logic or a second MUX receives the read data from the memory circuit in series with an input of the read Gen ECC logic A cross-coupling connector couples the read data from the memory circuit to a second input of the first MUX or for coupling the write data to a second input of the second MUX. An ECC bit comparator compares an output of the write Gen ECC logic to the read Gen ECC logic output.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: March 24, 2020
    Inventors: Saket Jalan, Indu Prathapan, Abishek Ganapati Karkisaval
  • Patent number: 10599518
    Abstract: Data memory protection is provided for a signal processing system such as a radar system in which the data memory is protected with a common set of parity bits rather than requiring a set of parity bits for each memory word as in Error Correction Coded (ECC) memories. The common set of parity bits may be updated as memory words in the data memory are accessed as part of signal processing of one or more digital signals. The memory protection ensures that in the absence of memory errors the common parity bits are zero at the end of processing the digital signals as long as each word in the data memory that is used for storing the signal processing data is written and read an equal number of times.
    Type: Grant
    Filed: December 31, 2015
    Date of Patent: March 24, 2020
    Inventors: Sandeep Rao, Karthik Ramasubramanian, Brian Paul Ginsburg
  • Patent number: 10572343
    Abstract: A memory device is configured to provide internal or on-die ECC (error checking and correction or error correction coding). In such a system, the code matrix can be managed as four quadrants of (N/4) bits, with two adjacent quadrants in an (N/2)-bit segment or portion. The N codes of the matrix correspond to the N bits of a data word to be protected by the ECC. The code matrix includes M codes corresponding to the M ECC check bits. The memory device includes internal ECC circuitry to perform ECC in the DRAM device with the ECC bits and code matrix in response to a request to access the data word. The codes in a quadrant steer an aliased bit to a quadrant other than an adjacent quadrant.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: February 25, 2020
    Assignee: Intel Corporation
    Inventors: John B. Halbert, Kjersten E. Criss
  • Patent number: 10521290
    Abstract: A solid state comprising: memory cells programmable with threshold voltages, each one associated with a respective bit pattern and variable over the memory cells thereby defining a respective threshold voltage distribution. Each pair of adjacent bit patterns can be discriminated by a respective first reference voltage between the threshold voltages associated with the pair of adjacent bit patterns, and a controller for storing LLR tables; for each bit pattern combination comprising first, second and third bit patterns respectively associated with the first reference voltage, a second reference voltage higher than the first reference voltage, and a third reference voltage lower than the first reference voltage, each LLR table has an error information when that bit pattern combination is associated with respective threshold voltages that, based on the threshold voltage distributions, are inconsistent with each other, or a LLR value otherwise.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: December 31, 2019
    Assignee: Memterex SRL
    Inventor: Sabrina Barbato
  • Patent number: 10444281
    Abstract: A microcontroller includes a data memory configured to store test signal data. The microcontroller further includes a signal generator configured to process the test signal data in order to provide at least one test signal. The microcontroller also includes a circuit under test configured to process the test signal. The test signal data includes at least one pattern snippet and an associated pattern descriptor. The pattern snippet includes data concerning a content of a part of the test signal. The associated pattern descriptor includes data concerning a pattern formed by the pattern snippet within the test signal.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: October 15, 2019
    Assignee: Infineon Technologies AG
    Inventors: Jayakrishna Guddeti, Deepa Chandran, Shivaprasad Sadashivaiah
  • Patent number: 10402302
    Abstract: An example method of reproducing a test case in a continuous integration environment includes detecting a test failure in a continuous integration environment. The continuous integration environment includes a plurality of stages for running a test on an application. The method also includes in response to detecting the failure, generating a snapshot while the test is running. The snapshot specifies a stage of the plurality of stages and a state of the application at which the failure occurred. The method further includes uploading the snapshot to a repository. At a later point in time, the snapshot may be restored to a computing device.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: September 3, 2019
    Assignee: Red Hat Israel, Ltd.
    Inventors: Oded Ramraz, Boaz Shuster
  • Patent number: 10365327
    Abstract: Techniques facilitating determination and correction of physical circuit event related errors of a hardware design are provided. A system can comprise a memory that stores computer executable components and a processor that executes computer executable components stored in the memory. The computer executable components can comprise a simulation component that injects a fault into a latch and a combination of logic of an emulated hardware design. The fault can be a biased fault injection that can mimic an error caused by a physical circuit event error vulnerability. The computer executable components can also comprise an observation component that determines one or more paths of the emulated hardware design that are vulnerable to physical circuit event related errors based on the biased fault injection.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: July 30, 2019
    Inventors: Pradip Bose, Alper Buyuktosunoglu, Schuyler Eldridge, Karthik V. Swaminathan, Yazhou Zu
  • Patent number: 10289486
    Abstract: Apparatuses and methods for parity generations in error-correcting code (ECC) memory to reduce chip areas and test time in imaging system are disclosed herein. Memory tests are needed to catch hard failures and soft errors. Random and nondestructive errors are soft errors and are undesirable. Soft errors can be detected and corrected by the disclosed ECC which is based on Hamming code. Before data are written into memory, the first parity generator based on the disclosed ECC generates the first parity by calculating the data. The first parity and data are stored into the ECC memory as a composite word. When the previously stored word is fetched from the ECC memory, the second parity generator based on the disclosed ECC is used to generate the second parity. A comparison between the first and second parity leads to a disclosed error mask, which is used to correct a single bit error if the error only happens to a single bit of the fetched data.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: May 14, 2019
    Assignee: OmniVision Technologies, Inc.
    Inventors: Hoon Ryu, Jong-Sik Na, TaeHyung Jung
  • Patent number: 10270471
    Abstract: A memory system having an error correction codes (ECC) self-checking function is disclosed. The memory system includes: an ECC encoder, used to convert input information bits into a codeword; a memory, coupled to the ECC encoder, the memory being used to store the codeword; and an ECC decoder, coupled to the memory and the ECC encoder, the ECC decoder being used to generate a syndrome of the codeword; wherein when the memory system is operated in an on-line self-checking mode and the codeword is fed into the memory from the ECC encoder, the codeword is as well fed into the ECC decoder from the ECC encoder to generate the syndrome.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: April 23, 2019
    Inventor: Shih-Lien Linus Lu
  • Patent number: 10164737
    Abstract: A sensor system is configured to communicate at least partially protected sensor data over a communication interface. The sensor system includes a sensor element and a communication interface communicatively coupled to the sensor element. The sensor element is configured to provide sensor data in the digital domain. The communication interface is configured to generate a data package for transmission over the communication interface from the sensor data. The data package includes a data grouping comprising one or more nibbles related to the sensor data. The data package further includes a nibble indicia based on at least a portion of selected nibbles within the data grouping.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: December 25, 2018
    Assignee: Infineon Technologies AG
    Inventors: Dirk Hammerschmidt, Wolfgang Scherr
  • Patent number: 10108512
    Abstract: Embodiments are generally directed to validation of memory on-die error correction code. An embodiment of a memory device includes one or more memory arrays for the storage of data; control logic to control operation of the memory device; and ECC (error correction code) logic, including ECC correction logic to correct data and ECC generation logic to generate ECC code bits and store the ECC bits in the one or more memory arrays. In a validation mode to validate operation of the ECC logic, the control logic is to allow generation of ECC code bits for a first test value and disable generation of ECC code bits for a second test value.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: October 23, 2018
    Assignee: Intel Corporation
    Inventors: John B. Halbert, Kuljit S. Bains
  • Patent number: 9966146
    Abstract: According to one embodiment, a controller groups a plurality of memory cells in each of the pages into a plurality of groups. The plurality of groups includes a first group and a second group. In a case of reading data from a first page, The controller performs first reading. The first reading includes reading data from the first page by using a first operation parameter for the first group. The controller performs second reading. The second reading includes reading data from the first page by using a second operation parameter for the second group. The controller merges first read data and second read data, and return the merged data as read data read from the first page. The first read data is acquired by the first reading. The second read data is acquired by the second reading.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: May 8, 2018
    Inventors: Daiki Watanabe, Hiroshi Sukegawa, Hiroshi Yao, Tokumasa Hara, Naomi Takeda
  • Patent number: 9817980
    Abstract: Exemplary systems, methods and computer-accessible mediums for encrypting at least one integrated circuit (IC) can include determining, using an interference graph, at least one location for a proposed insertion of at least one gate in or at the at least one IC, and inserting the gate(s) into the IC(s) at the location(s). The interference graph can be constructed based at least in part on an effect of the location(s) on at least one further location of the IC(s).
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: November 14, 2017
    Assignee: New York University
    Inventors: Jeyavijayan Rajendran, Youngok Pino, Ozgur Sinanoglu, Ramesh Karri
  • Patent number: 9646105
    Abstract: Hashing complexity is reduced by exploiting a hashing matrix structure that permits a corresponding hashing function to be implemented such that an output vector of bits is produced in response to an input vector of bits without combining every bit in the input vector with every bit in any row of the hashing matrix.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: May 9, 2017
    Inventors: Hun-Seok Kim, Patrick Bosshart
  • Patent number: 9632894
    Abstract: The present invention relates to an apparatus for computing an error rate comprising: a first circuit interface being connected to a first sub-circuit receiving data and computing output data through a predetermined computation process; a second circuit interface and being connected to a first test circuit receiving the same data, which is inputted to the first sub-circuit, and computing output data through the predetermined computation process; an error injecting part injecting an error to the first test circuit; an error detecting part comparing output data of the first sub-circuit to output data of the first test circuit; and an error rate computing part computing input node error probability of the first sub-circuit by statistic processing of the compared result. The apparatus and method for computing error rate of the present invention is able to shorten the time required to obtain error probability, compared to the direct simulation of the full circuit.
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: April 25, 2017
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jin-Ho Han, Young-Su Kwon, Kyung-Jin Byun
  • Patent number: 9614788
    Abstract: Methods and systems for operating a packet switch that communicates packets with error indication, including the steps of: receiving a packet comprising an error detection field; utilizing the error detection field to identify an error in the packet; marking the occurrence of the error in an error propagation field in the packet; updating the value of the error detection field; and forwarding the modified packet, with the updated value of the error detection field and the error propagation field, according to information carried in the packet.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: April 4, 2017
    Assignee: Valens Semiconductor Ltd.
    Inventors: Eyran Lida, Nadav Banet, Aviv Salamon
  • Patent number: 9583216
    Abstract: A system implementing an MBIST device is disclosed. The system includes an ECC-protected memory and the MBIST device for self-test of the memory. The MBIST device includes a first access port communicatively connected to the memory via a first path, the first path excluding the ECC logic associated with the embedded memory, and a second access port communicatively connected to the memory via a second path, the second path including the ECC logic associated with the memory. The device is configured to test the memory, in a first mode of operation, via the first path and, in a second mode of operation, via the second path. One advantage of such system includes re-using, with little additional die area, of MBIST logic already required for manufacturing test of the product (first mode of operation) for system or application level tests that may be carried out by customers (second mode of operation).
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: February 28, 2017
    Assignee: ANALOG DEVICES, INC.
    Inventors: Eric C. Jones, Andrew J. Allan
  • Patent number: 9553768
    Abstract: A determination is made regarding whether a firewall will block a network packet. The network packet indicates a set of one or more characteristics. A test packet is generated that indicates the set of characteristics. The test packet is sent to the firewall without using a network. A test result is received from the firewall. The test result is stored.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: January 24, 2017
    Assignee: Illumio, Inc.
    Inventors: Jerry B. Scott, Daniel R. Cook, Paul J. Kirner
  • Patent number: 9553608
    Abstract: A data storage device includes a nonvolatile memory and a controller having a decoder. The nonvolatile memory is operatively coupled to the controller. The nonvolatile memory is configured to store a set of bits. The decoder is configured to receive the set of bits from the memory. The decoder is further configured to perform a decoding operation using the set of bits based on a parity check matrix. The parity check matrix includes a block row. The block row has a first non-zero sub-matrix and a second non-zero sub-matrix that is separated from the first non-zero sub-matrix within the block row by at least a threshold number of null sub-matrices of the block row.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: January 24, 2017
    Inventors: Zongwang Li, Manuel Antonio D'Abreu
  • Patent number: 9505406
    Abstract: It divides the network communication protocol for the communication between automobile into a software protocol layer (L1), a signal protocol layer and a physical protocol layer wherein the software protocol layer is used for checking coding and decoding the data required to be sent and received by a system, and the signal protocol layer is used for performing combined coding of data package signals and basic light signal on data packages produced by the software protocol layer according to the protocol agreement, and the physical protocol layer is used for converting digital signals and light signals mutually. A device comprises a light receiving apparatus arranged at the head of the automobile and a light emitting device, which collects the operating status information of automobile, performs information exchange with surrounding automobiles through digital information, arranged at the tail of the automobile.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: November 29, 2016
    Inventors: Shengyan Zhou, Jinlong Ao, Jingquan Li, Yuan Zhang
  • Patent number: 9442833
    Abstract: Enrolling a device identity is disclosed. A determination is made as to whether one or more areas of a storage device has a sufficient number of faults. If an insufficient number of faults is present, additional faults are generated. Verifying a device identity is also disclosed. A fingerprint based on the presence of one or more permanent faults in a storage device is received. The received fingerprint is compared with one or more stored fingerprints to determine an identity of the device.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: September 13, 2016
    Assignee: QUALCOMM Incorporated
    Inventor: Karl-Anders R. Johansson
  • Patent number: 9329231
    Abstract: The present disclosure describes a novel method and apparatus of using the JTAG TAP's TMS and TCK terminals as a general purpose serial Input/Output (I/O) bus. According to the present disclosure, the TAP's TMS terminal is used as a clock signal and the TCK terminal is used as a bidirectional data signal to allow serial communication to occur between; (1) an IC and an external controller, (2) between a first and second IC, or (3) between a first and second core circuit within an IC.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: May 3, 2016
    Inventor: Lee D. Whetsel
  • Patent number: 9286933
    Abstract: Systems, methods, devices, circuits for data processing, and more particularly to data processing including operational marginalization capability. In one case a data processing system is disclosed that includes a loop detector circuit and a sample based noise injection circuit. The loop detector circuit applies a loop detection algorithm to a data input to yield a loop detected output, and the sample based noise injection circuit generates a noise component based at least in part on the loop detected output.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: March 15, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: George Mathew, Haotian Zhang, Haitao Xia, Bruce Wilson
  • Patent number: 9208043
    Abstract: A method, non-transitory computer readable medium, and apparatus for performing fault injection and verification on an integrated circuit are disclosed. For example, the method generates a mask file for one or more modules of a hierarchical design, wherein the mask file identifies one or more essential bits, receives a selection of one of the one or more modules as a selected module for the fault injection and the verification to be applied, performs the fault injection on at least one essential bit of the selected module based upon the mask file for the selected module, and performs the verification on the selected module.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 8, 2015
    Assignee: XILINX, INC.
    Inventors: Chen W. Tseng, Restu I. Ismail, Robert Le
  • Patent number: 9170904
    Abstract: A system for injecting I/O faults into a closed system, for example, the injection of link level I/O faults, involves the use of a simulated computing environment. In an embodiment, the system provides for fault injection using an emulated IBM System z environment and including the use of FICON and/or other suitable communication channel protocols. The emulated System z environment may include a simulated z/OS and/or emulated System z hardware and software components.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: October 27, 2015
    Assignee: EMC Corporation
    Inventors: Douglas E. LeCrone, Jeffrey L. Jones, Paul A. Linstead, Denis J. Burt, Bruce A. Pocock
  • Patent number: 9003244
    Abstract: A method of performing a dynamic built-in self-test (BIST). The method includes performing a first test of a circuit on a semiconductor chip. The first test includes a first switch factor. The circuit during the first test is monitored with one or more sensors. A first sensor value of one or more sensors monitoring the circuit is determined. It is also determined whether the first sensor value is within a range of a programmable constant. A second switch factor is determined in response to determining that the first sensor value outside the range of the programmable constant.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: April 7, 2015
    Assignee: International Business Machines Corporation
    Inventors: Steven M. Douskey, Ryan A. Fitch, Michael J. Hamilton, Amanda R. Kaufer
  • Publication number: 20150074473
    Abstract: A pseudo-error generating device of an embodiment includes error injection information including a header section and a data section, a storage section configured to store the error injection information, and at least one error injecting circuit, connected to a test target circuit through a predetermined path, configured to inject a pseudo-error to the predetermined path. The header section includes a port specifying one of the at least one error injecting circuit, and an address specifying the data section. The data section includes an injection condition and error injection data for injecting the pseudo-error. The error injecting circuit injects the pseudo-error to the predetermined path based on the injection condition and the error injection data.
    Type: Application
    Filed: January 31, 2014
    Publication date: March 12, 2015
    Inventor: Tsutomu UNESAKI
  • Patent number: 8930794
    Abstract: The present inventions are related to systems and methods for validating retry features in LDPC decoders and in systems incorporating LDPC decoders. For example, a data processing circuit is disclosed that includes a low density parity check decoder and is operable to correct errors in a data set. The data processing circuit includes at least one retry feature operable to assist in correcting the errors that are not corrected without the at least one retry feature. A retry validation circuit in the data processing circuit is operable to inject errors in the data set to trigger the at least one retry feature.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: January 6, 2015
    Assignee: LSI Corporation
    Inventors: Yang Han, Shaohua Yang
  • Publication number: 20150006981
    Abstract: A storage system includes a channel detector, an LDPC decoder, and an erasure block. The channel detector is configured to receive data corresponding to data read from a storage and output an LLR signal. The LDPC decoder is configured to receive the LLR signal and output a feedback signal to the channel detector. The erasure block is configured to erase at a portion of at least one of the LLR signal and the feedback signal. A method for testing includes generating an error rate function corresponding to an erasure pattern. The function is a function of a number of LDPC iterations. The method includes determining testing parameters at least in part based on the error rate function, wherein the testing parameters comprise a testing number of LDPC iterations, a passing error rate, and the erasure pattern. The method includes testing storage devices using the testing parameters.
    Type: Application
    Filed: June 6, 2014
    Publication date: January 1, 2015
    Inventors: Yu Kou, Lingqi Zeng, Jason Bellorado, Marcus Marrow
  • Patent number: 8875104
    Abstract: A method, system and computer program product for efficiently developing software and supporting creation of source code so as to develop software that meets the requirements. A plurality of test cases defining a plurality of respective tests to be executed to check the conformity of the software to the requirements are used. In a test execution step, one or more specific test cases selected from the plurality of test cases are executed or the specific test cases are caused to be executed. Furthermore, a test result of a test case executed or caused to be executed in the test case execution step is added to the source code.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: October 28, 2014
    Assignee: International Business Machines Corporation
    Inventor: Atsushi Yokoi
  • Patent number: 8868989
    Abstract: A system for testing an error detection circuit includes a fault injection unit for operating the error detection circuit in a fault injection mode. A fault is inserted in either of a primary or a redundant processor. Output signals generated by the primary and redundant processors are compared and checked for a mismatch and the error detection circuit outputs a test signal based on the comparison result.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: October 21, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Amit Jindal, Nitin Singh
  • Patent number: 8844023
    Abstract: A semiconductor memory may be provided with a built-in test mode that is accessible through a password protection scheme. This enables access to a built-in test mode after manufacturing, if desired. At the same time, the password protection prevents use of the built-in test mode to bypass security features of the memory.
    Type: Grant
    Filed: December 2, 2008
    Date of Patent: September 23, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Antonino La Malfa, Marco Messina
  • Publication number: 20140281762
    Abstract: A random noise generation module for generating noisy LLRs for testing an error correction circuit of a nonvolatile memory storage module. The random noise generation module includes a coefficient generator for generating one or a plurality of coefficients, each of the plurality of coefficients associated with one region of a plurality of regions defining a linear space proportionately divided according to an area under a probability distribution curve for a nonvolatile memory storage module. The random noise generation module further includes a linear random number generator for generating a linear random number and a comparator for comparing the linear random number to one or more of the plurality of coefficients to identify the region of the plurality of regions of the probability distribution curve in which the linear random number belongs to generate a noisy LLR for testing an error correction circuit of a nonvolatile memory storage module.
    Type: Application
    Filed: January 30, 2014
    Publication date: September 18, 2014
    Applicant: PMC-SIERRA US, INC.
    Inventor: Christopher I. W. Norrie
  • Publication number: 20140250340
    Abstract: Exemplary embodiments of the present invention disclose a method and system for monitoring a first Error Correcting Code (ECC) device for failure and replacing the first ECC device with a second ECC device if the first ECC device begins to fail or fails. In a step, an exemplary embodiment detects that a specified number of correctable errors is exceeded. In another step, an exemplary embodiment detects the occurrence of an uncorrectable error. In another step, an exemplary embodiment performs a loopback test on an ECC device if a specified number of correctable errors is exceeded or if an uncorrectable error occurs. In another step, an exemplary embodiment replaces an ECC device that fails the loopback test with an ECC device that passes a loopback test.
    Type: Application
    Filed: March 1, 2013
    Publication date: September 4, 2014
    Inventors: Edgar R. Cordero, Timothy J. Dell, Joab D. Henderson, Jeffrey A. Sabrowski, Anuwat Saetow, Saravanan Sethuraman
  • Publication number: 20140245086
    Abstract: A method for estimating error rates in low-density parity check codes includes calibrating an encoder according to specific channel parameters and according to dominant error events in the low-density parity-check code. Dominant codewords are classified based on characteristics of each codeword that are likely to produce similar error rates at similar noise levels; codeword classes that produce the highest error rate are then tested. Error boundary distance is estimated using multiple binary searches on segments. Segments are defined based on codeword, trapping set and biasing noise components of the channel. To improve calculation speed the most significant subclasses of codewords, trapping sets and noise signals are used.
    Type: Application
    Filed: September 16, 2013
    Publication date: August 28, 2014
    Applicant: LSI Corporation
    Inventors: Denis Vladimirovich Zaytsev, Ivan Leonidovich Mazurenko, Alexander Alexandrovich Petyushko, Aleksey Alexandrovich Letunovskiy, Pavel Aleksandrovich Aliseitchik, Dmitry Nicolaevich Babin
  • Patent number: 8819331
    Abstract: A memory system according to the embodiment comprises a memory device including a plurality of memory cells operative to store storage data, the storage containing input data from external to which parity information is added; and a memory controller operative to convert between the input data and the storage data, the storage data containing information data corresponding to the input data, and a relationship between the information data and the input data being nonlinearly.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: August 26, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Haruki Toda
  • Publication number: 20140115409
    Abstract: Providing for testing of digital sequencing components of an integrated chip is described herein. By way of example, self-test procedures are provided for unidirectional integrated chips that have different sequence generation (e.g., transmission) and sequence monitoring (e.g., receiving) frequencies. A test logic component(s) can be added to an integrated chip to match the sequence generation frequency to the sequence monitoring frequency. This can facilitate self-testing of unidirectional sequence generating components, by modifying a generated sequence at a first datarate to be receivable at a second datarate, and directing the modified sequence to sequence monitoring components of the integrated chip configured to operate at the second datarate.
    Type: Application
    Filed: October 18, 2012
    Publication date: April 24, 2014
    Inventor: Glen Miller