Abstract: The invention relates to a protective system for an installation, in particular for a gas-turbine installation, in which all the fail-safe protective circuits with reaction time requirements of greater than 50 milliseconds are routed via a more fail-safe programmable logic automation system. For all the other protective circuits with reaction time requirements of less than 50 milliseconds, fail-safe control relays are connected in a configuration which is tolerant to single faults, in which the automation system can check the operation of the control relay circuit cyclically during operation of the installation.

Abstract: In an embodiment, a method provides an input and an expected test output for a unit test. The unit test is executed using a module under test and the input, thereby generating an actual test output. The actual and expected test outputs are serialized into XML, so that comparison and extraction of differences between actual and expected test outputs can be performed using methods for comparisons and extraction of differences between XML documents, such as XML change detection or calculation of checksums.

Abstract: In an embodiment, a node comprises a packet scheduler configured to schedule packets to be transmitted on a link and an interface circuit coupled to the packet scheduler and configured to transmit the packets on the link. The interface circuit is configured to generate error detection data covering the packets, wherein the error detection data is transmitted between packets on the link. The interface circuit is configured to cover up to N packets with one transmission of error detection data, where N is an integer >=2. The number of packets covered with one transmission of error detection data is determined by the interface circuit dependent on an availability of packets to transmit. In another embodiment, the interface circuit is configured to dynamically vary a frequency of transmission of the error detection data on the link based on an amount of bandwidth being consumed on the link.

Abstract: Elements of a coding table which are error-free are found at S2. At S3, corresponding elements in an erasure information table are completed, indicating that the elements in the coding array are correct. A counter is initialized at Nmax, which is the maximum number of errors that can be corrected, at S4. At S5, the row of the erasure information table is scanned beginning from the first parity column for empty elements. Each empty parity date element of the erasure information table row is marked as incorrect at S7 For each such element, the counter is decremented at S8. At S9, the elements of the erasure information table are scanned from the first column of the application data and zero padding section for empty elements. At step S11, an empty element is marked as incorrect. At step S12, the counter is then decremented. It is determined at step S13 whether or not the counter is equal to zero.

Abstract: A process for monitoring a machine, within the framework of a FMEA process for at least one component of the machine for at least one predetermined fault which can be diagnosed by means of a diagnosis diagram and a diagnosis system with sensors for detecting physical parameters of the machine, a diagnosis priority number being determined which is the product of the following index quantities: severity of the effect of occurrence of the fault with respect to the serviceability of the machine; expected machine-specific consequential costs when a fault occurs, and the possibility of correction of the fault. The diagnosis priority number is used in the evaluation of the diagnosis diagram, the diagnosis system, the current machine state, the necessary maintenance measures and/or the failure risk of the machine.

Abstract: Systems, methods, and computer-readable media provide for updating a firmware image during a debugging sequence using a firmware debugger application without re-flashing each updated firmware image on a non-volatile memory device. Embodiments include a debugger application operating on a host computer system and a debugger driver located within a firmware image undergoing the debugging sequence on a target computer system. The debugger application and debugger driver may communicate and transfer data between one another. Upon detecting an error in a firmware image, the debugger driver notifies the debugger application. The debugger application sends an updated firmware image to the debugger driver on the target computer system. The debugger driver loads the updated firmware image and passes control to an entry point of the updated firmware image for continued debugging from the new entry point.

Abstract: A method and a device are provided for performing switching and data comparison in a computer system having at least two processing units which each process data at a specified clock pulse, in which a switchover arrangement is provided and switching takes place between at least two operating modes, and a comparison unit is provided. A first operating mode corresponding to a compare mode is provided, and a second operating mode corresponding to a performance mode is provided. A synchronization arrangement is provided which assigns to the specifiable data a clock pulse information as a function of a processing unit, and at least the comparison unit takes into consideration this clock pulse information in the corresponding data.

Abstract: A unit and method for clock changeover in a system having at least two processing units, in which switchover device(s) are provided by which a switchover between at least two operating modes of the system is able to be implemented in which a clock pulse changeover is carried out in at least one processing unit in a switching of the operating mode.

Abstract: A method of transmitting data through a link comprises encoding digital data into encoded digital data in a transition minimized differential signaling encoder, serializing the encoded digital data into encoded and serial digital data in a serializer, generating test data in a pseudo-random binary sequence generator circuit, transmitting the encoded and serial digital data through a multiplexer to a transmission medium in a normal mode of operation, and transmitting the test data through the multiplexer to the transmission medium in a test mode of operation. The encoder, the serializer, the sequence generator circuit, and the multiplexer are fabricated in a single integrated chip. The test data includes data to generate colors in a visual image, and the encoded and serial digital data is received, deserialized, decoded, and displayed in a display unit.

Abstract: Fault injection in dynamic random access memory (‘DRAM’) modules for performing built-in self-tests (‘BISTs’) including establishing, in the mode registers of the DRAM modules by the memory controller through the shared address bus, an injection of a fault into one or more signal lines of a DRAM module, the fault characterized by a fault type; writing data by the memory controller through a data bus to the DRAM modules, the data identifying a particular DRAM module; and responsive to receiving the data, injecting, by the particular DRAM module, the fault characterized by the fault type into the one or more signal lines of the particular DRAM module.

Abstract: Consensus testing of electronic system. A tester (112) for testing an electronic system (100) includes: a traffic interface (114) to receive traffic (102) from a test of an electronic system (100); an element comparator (118) to extract a value from an element of the traffic (102) and to compare the extracted element value with an element value (110) obtained from another test of another electronic system (104, 106, 108); and a test result generator (122) to generate consensus information (124) on the interoperability of the electronic system (100), based on comparing (120) the extracted element values of the electronic system (100) with the element values obtained from the other test of the other electronic system (104, 106, 108).

Abstract: A chip testing device having a plurality of testing units is provided. Each testing unit comprises a selector, a flip-flop unit, a first buffer and a second buffer. The selector is controlled by a control signal and has a first input terminal, a feedback input terminal, and a first output terminal. The flip-flop unit has a second input terminal coupled to the first output terminal, a clock signal input terminal for receiving a reference clock signal, and a second output terminal outputting an output data. The first buffer is coupled to the flip-flop unit to convert the output data to a high voltage data, and outputs the high voltage data. The second buffer is coupled to the first buffer to convert high voltage data to low voltage data and transmit the low voltage data to the feedback input terminal.

Abstract: Provided is a method and system for diagnosing a test system to determine whether a condition of the test system contributed to an undesirable measurement result. The method includes interrogating a device under test comprising at least one of transmitting an electric signal to energize a device under test by the test system and conducting a passive measurement that does not require the device under test to be energized to be performed to determine if the device under test satisfies a design parameter. The method further includes processing an output signal including at least one of a responsive electric signal transmitted from the device under test in response to being energized and a passive signal corresponding to the passive measurement, and comparing a value of a property of the output signal to a reference value. Responsive to the comparing, the method determines whether the value of the output signal is within an acceptable tolerance of the reference value.

Abstract: A method and system for performing diagnosing in an automatic test environment. The method begins by determining a fail condition during a test of a device under test (DUT). A diagnostic suite is determined for testing the fail condition. The diagnostic suite is generated if the diagnostic suite is not available for access.

Abstract: A logic circuit comprises a logic module comprising a functional logic block supplying a functional result, and a functional flip-flop receiving the functional result and supplying a synchronous result. A module for checking the functional logic block comprises a checking logic block executing the same logic function as the functional logic block and supplying a checking result, checking synchronous flip-flops for applying data present at the input of the functional logic block to the input of the checking logic block, and means for comparing the functional result and the checking result and for supplying a first error signal.

Abstract: A built-in, at-speed BERT is provided that may be part of high-speed serial interface circuitry implemented on an integrated circuit. The built-in, at-speed BERT takes advantage of an existing clock data recovery (CDR) dual-loop architecture and built-in self test (BIST) circuitry. The built-in, at-speed BERT provides a low-cost solution for production testing of high-speed serial links, facilitating jitter analysis and evaluation of pre-emphasis and equalization performance. This further allows adaptation of pre-emphasis and equalization.

Abstract: A method of verifying whether a recording and/or reproducing apparatus that records and/or reproduces a disc having temporary defect management area (TDMA) information properly produces the TDMA information, the method including producing TDMA information produced by performing a recording test according to a series of recording operations based on a scenario using a blank test disc as test information; and providing a result of the recording test by confirming the test information using reference test information for the recording test.

Abstract: There is provided a test apparatus for testing a device under test.

Abstract: A high volume testing/formatting process is provided for Universal Serial Bus-based (USB-based) electronic data flash cards (USB devices) that meets the increasing demand for USB electronic data flash cards (USB devices). A test host is simultaneously coupled to the multiple USB devices (e.g., using a multi-port card reader or a probe fixture), a controller endpoint value is read from each of the USB devices and verified with a known good value, and then testing/formatting is performed on each of the USB devices by writing predetermined data into each USB device in a pipelined manner, then reading out and testing the predetermined data. In one embodiment, the test host implements a special a USB driver that blocks standard USB registration procedures upon detecting the plurality of USB devices. Control and/or boot code data are written onto the flash memory device (i.e., instead of being provided on a controller ROM).

Abstract: A method and system for testing a semiconductor device is disclosed. The method provides an integrated test program defined by a plurality of test items, and a test program defined by a sub-set of the test items. Test data is derived by batch sample testing of the semiconductor device, and an error rate for a test item is computed and then compared to a reference data value. On the basis of the comparison between the error rate and the reference data value, the test program may be modified in real-time.

Abstract: A method of verifying the accuracy of blocks of data. In one embodiment, a method of verifying the accuracy of data in a message that includes a checking mechanism with hidden data is provided. The method comprises observing two or more initial messages. Comparing the residual error of each of the observed initial messages. If the residual errors of at least two of the initial messages match each other, storing the matched residual error. For subsequent messages, comparing residual errors of the subsequent messages with the stored matched residual error.

Abstract: An apparatus for verifying a custom IC including a test pattern generating unit for generating a test pattern for verifying a function of the custom IC. The test pattern is output to a master IC and a test IC. The apparatus further includes a comparing unit connected to receive operation signals output from the master IC and the test IC for comparing the operation signals to see if the operation signals are agreed with each other and for generating a comparison signal based on a comparison result, a judging unit connected to receive the comparison signal for judging if there is any abnormality in the test IC and for outputting a judged signal based on a judged result, and a computer connected to receive the judged signal for displaying the judged result of the test IC.

Abstract: A timing generator that needs no analog circuit for adding jitters and allows the circuit scale and power consumption to be reduced.

Abstract: A method, apparatus, and computer program product are disclosed for testing a data processing system's ability to recover from cache directory errors. A directory entry is stored into a cache directory. The directory entry includes an address tag and directory parity that is associated with that address tag. A cache entry is stored into a cache that is accessed using the cache directory. The cache entry includes information and cache parity that is associated with that information. The directory parity is altered to imply bad parity. The bad parity implies that the address tag that is associated with this parity is invalid. The information included in the cache entry is altered to be incorrect information. However, although the information is now incorrect, the cache parity continues to imply good parity which implies that the data is good. This good parity implies that the information that is associated with the parity is valid, even though it is not.

Abstract: A test circuit in an integrated circuit and method of testing therewith are described. A test pattern generator provides a test pattern. A reference circuit includes a first sequential circuit coupled in series with a second sequential circuit. A circuit under test is coupled between a source sequential circuit and a destination sequential circuit to form a series. The source sequential circuit and the first sequential circuit are coupled to the test pattern generator to receive the test pattern. A comparison circuit is coupled to receive a first output from the destination sequential circuit and a second output from the second sequential circuit. The comparison circuit is configured to compare the first output with the second output to provide a signature output.

Abstract: An automatic CRC format detection and selection device observes FCS errors during an interval, incrementing counts thereof. When a determination is made that an error count threshold has been met, the CRC format may be automatically changed in order to enable CRC format detection and switching without requiring a user to have knowledge of the format or how to accomplish its change.

Abstract: A method for verifying whether a recording/reproducing apparatus properly produces disc management information and records the disc management information on a disc includes preparing a test disc; issuing reading commands to a recording/reproducing apparatus to be tested on which the test disc is loaded and verifying the disc in order to verify the reading operation; and issuing recording commands to the recording/reproducing apparatus to be tested on which the test disc is loaded and checking whether a temporary disc management area (TDMA) structure is properly updated on the disc in order to verify the modification operation.

Abstract: This invention relates to fault detection in electrical circuits. The invention provides a method and apparatus for testing an input circuit by generating a periodic test signal having a predetermined phase and a predetermined amplitude; summing the test signal and an input signal to provide a summed signal; processing the summed signal to provide an output signal; generating an extracted test signal from the output signal; comparing the extracted test signal with a reference signal representing said periodic test signal; generating an error signal in dependence upon the result of said comparing step. The invention also provides a method and apparatus for testing a plurality of adjacent input circuits.

Abstract: A memory device capable of detecting its failure, the memory device includes a data input section for receiving data applied from an external part of the memory device; a latch section for receiving and storing therein the data which have passed through the data input section; memory cell arrays for storing therein the data which have passed through the data input section; and a data compressor for determining whether or not the data stored in the latch section and the data stored in the memory cell arrays are identical to each other.

Abstract: The generic device emulator provides an operational emulation of the behavior of any desired device within a device connectivity or other communications protocol as specified in a description of the respective device. This facilitates development and implementation of devices within a device connectivity architecture based on the protocol, since the user has only to define the description of the device. The generic device emulator provides default behaviors for a set of capabilities defined in the description for the device, which can be over-ridden or augmented by user-provided implementation of specific behavior for a capability. The generic device emulator also permits the user to inject defect behaviors, such as to introduce defects in the device's implementation of the protocol.

Abstract: A communications network tap, comprises a first terminal and a second terminal adapted to couple the tap in-line in the network and communicate data packets with network devices. A heartbeat generator is configured to generate a heartbeat signal, and a heartbeat insert circuit coupled to the first terminal and the heartbeat generator and configured to insert the heartbeat signal into data packets. A third terminal is coupled to the heartbeat insert circuit and adapted to couple the tap to a network monitor and communicate data packets with network monitor. A heartbeat remove circuit is coupled to the third terminal and configured to receive data packets from a network monitor and remove the heartbeat signal from the data packets. A heartbeat detector coupled to the heartbeat remove circuit and configured to detect whether the data packets include the heartbeat signal, and if not, to generate an alarm signal. A switch is coupled to the second terminal and configured to transmit data packets onto the network.

Abstract: An input circuit of a semiconductor memory device includes a data input circuit and a data pattern setting circuit. The data input circuit receives first data, and generates second data by buffering the first data, sampling buffered first data responsive to a write data strobe (WDQS) signal, and parallelizing sampled data. The data pattern setting circuit sets a pattern of the second data responsive to a test mode signal and a data pattern select signal to generate third data. Accordingly, the semiconductor memory device including the input circuit may generate data of various patterns in a test mode, and may perform a high-speed test using a low-speed tester.

Abstract: A main controller sends a “rewrite mode” command to an engine controller. Receiving the command, the engine controller 12 sends a “roger” status. This switches the mode from a print mode to a rewrite mode. In the rewrite mode, the engine controller 12 serves as a master and the main controller 11 serves as a slave, a communication which is necessary for rewriting of firmware takes place between the two, and the firmware is rewritten.

Abstract: Memory devices and methods of operating memory devices provide for using differing potentials during erase verify operations facilitate normal erase operations and subsequent erase check operations. Such apparatus and methods facilitate subsequent checks for data gain of erased memory cells using abbreviated procedures compared to normal erase operations.

Abstract: A method for recording analog signals and digitally encoded information associated with primary and secondary devices of an electric power system includes: receiving a plurality of analog output signals and a plurality of ON/OFF status signals from the electric power system; receiving a time-synchronization analog signal and/or a time-synchronization data packet from a time synchronization source; maintaining an internal clock synchronized with the synchronization source; sampling and digitizing the plurality of analog output signals; monitoring a status and/or a change of status of the plurality of ON/OFF status signals; receiving digitally encoded information signals as incoming data packets; decoding and analyzing the incoming data packets; analyzing the plurality of analog output signals and digitally encoded information signals using a triggering algorithm; and storing digitized analog output signals and digitally encoded information signals together with corresponding timing information in a record as f

Abstract: Methods and apparatuses for entering at least one memory into a test mode are provided. At least one test MRS bit may be stored in a first register for controlling the memory. At least one test MRS code may be programmed into a second register. Each of the at least one bits stored in the first register may correspond one of the at least one test MRS codes stored in the second register.

Abstract: A test circuit tester includes a scan-chain input-output information generator that generates information for an input and an output of the scan chain that is scan-chain input-output information, based on input information for the scan chain; a test-circuit input-output information generator that generates information for an input and an output of the test circuit that is test-circuit input-output information, based on the scan-chain input-output information; an output unit that outputs the test-circuit input-output information generated; and a verifying unit that verifies the test circuit based on an output pattern output from the test circuit through the scan chains in response to input of the information for the input of the test circuit output to the test circuit, and the information for the output from the test circuit.

Abstract: A method for determining a fault tolerance of an erasure code comprises deriving base erasure patterns from a generator matrix of an erasure code, determining which of the base erasure patterns are adjacent to one another and XORing the adjacent base erasure patterns with one another to produce child erasure patterns of the erasure code. The method further comprises combining the base erasure patterns and the child erasure patterns to form a minimal erasures list (MEL) for the erasure code, whereby the MEL corresponds to the fault tolerance of the erasure code. Also provided are methods for communicating and storing data by using the fault tolerance of erasure codes.

Abstract: Methods and apparatus for enabling the framework and the application code associated with an application programming interface (API) to be efficiently and comprehensively tested are disclosed. According to one aspect of the present invention, a structure that defines an API test in declarative metadata includes an entity to be tested, a first metadata arrangement, and a second metadata arrangement. The first metadata arrangement includes any data to be used when the entity is tested, and the second metadata arrangement includes any expected outputs associated with testing the entity.

Abstract: A transmitting device generates a data block including a first field having a first plurality of bits that includes an error detection portion and a second field having a second plurality of bits; selects an error injection mask based on the second plurality of bits; modifies the first plurality of bits with the error injection mask to generate a modified first plurality of bits; and transmits the data block to a receiving device. The receiving device decodes the second plurality of bits to generate decoding results; selects an error injection mask based on the decoding results; modifies the first plurality of bits using the error injection mask to generate a modified first plurality of bits that includes a resultant error detection value indicated in the error detection portion; and detects whether the decoding results for the second field are correct based on the resultant error detection value.

Abstract: A test system and methods using the test system correlate measurements of a device under test (DUT) regardless of which test fixture is used for in-fixture testing of the DUT. The test system includes test equipment, a test fixture that interfaces the DUT to the test equipment, a computer and a computer program executed by the computer. The computer program includes instructions that implement determining a port-specific difference array for test fixtures used with the test system. The difference array describes a difference between the test fixtures at a corresponding test port thereof. The method includes determining the difference array, measuring a performance of the DUT in a second test fixture, and applying the difference array such that the measured performance approximates a hypothetical DUT performance for the DUT as if mounted in a first test fixture.

Abstract: A method of performing cell delineation in a communications network is described. The method includes providing a data cell defined based on a communications protocol. The data cell forms at least a portion of a data stream. The method further includes mapping the data cell into frames defined based on a network protocol, where adjacent frames are separated by a frame boundary. The data cell and frames have a common fundamental base structure represented by a data unit The data cell includes a boundary data unit defining a cell boundary The boundary data unit includes validation information for an associated segment of data units in the data cell. The method also includes analyzing a set of the data units independent of the frame boundary to determine potential validation information. The method includes comparing the potential validation information with content of at least one of the data units to identify the boundary data unit and the frame boundary.

Abstract: The present invention provides an apparatus and a computer program product for applying external clock and data patterns for TTP-LBIST. A simulation model for the logic under test is set up in a simulator. Next, a user sets up an external LBIST block, which comprises pre-verified internal clock and data pattern logic, and connects this block to the logic in the simulation model. The internal clock and data pattern logic provides the input patterns used in OPCG modes of LBIST. This internal clock and data pattern logic is already verified through the design effort. Therefore, the internal pattern generators become the external pattern generators in the simulation model. The external LBIST block applies the external clock and data patterns, and subsequently, the user receives and processes these output patterns to determine if the logic operates correctly.

Abstract: A system and method are disclosed for determining the minimum required processing speed for a quadrature decoder using measurements of encoder performance, and to assess the safety factor of a particular decoder processing speed. The system and method may also be used to indicate proper adjustment direction by displaying real-time error measurements during encoder alignment. The system measures a logic state width error and calculates alignment parameters, processing speed and a safety factor. The method allows a measured logic state width error to be used to calculate a minimum required processing speed and safety factor.

Abstract: A closed system such as a TET system in which self-testing of all components of the implantable medical device whose malfunction could negatively impact on the proper operation of the closed system is automatically and periodically performed without triggering from an external device. In addition, a closed system including automatic, periodic self-testing of the implantable medical device in which, whenever practical, testing of the components is synchronized with telemetric communication of the external device whereby an external RF field generated by the external device is used to supply necessary power to perform self-testing.

Abstract: There is provided a test apparatus that tests a device under test.

Abstract: Monitoring of the state vector of a test access port (TAP) permits isolation of the root cause of improper transitions of the state vector due to various factors, including electrical noise. The test access port includes TCK, TMS, TDI, and TDO. A circuit for monitoring the state vector includes a TAP controller, a storage circuit, and a sampling circuit. The TAP controller updates the state vector for each transition of TCK. The storage circuit stores a value of the state vector responsive to transitions of TCK while a write enable is enabled. To permit generating the write enable without additional pins and without violating a protocol for the test access port, the write enable may be generated in response to a plurality of transitions of TDI of the test access port during an interval in which TMS and TCK of the test access port have no transitions.

Abstract: A method, apparatus, and computer program product are disclosed for testing a data processing system's ability to recover from cache directory errors. A directory entry is stored into a cache directory. The directory entry includes an address tag and directory parity that is associated with that address tag. A cache entry is stored into a cache that is accessed using the cache directory. The cache entry includes information and cache parity that is associated with that information. The directory parity is altered to imply bad parity. The bad parity implies that the address tag that is associated with this parity is invalid. The information included in the cache entry is altered to be incorrect information. However, although the information is now incorrect, the cache parity continues to imply good parity which implies that the data is good. This good parity implies that the information that is associated with the parity is valid, even though it is not.

Abstract: A method for configuring a testing system that includes a step of connecting a commercially available computer (CACMP) for directly controlling transmission of a plurality of test vectors to a test head. The method further includes a step of connecting a test vector memory between the CACMP and the formatter unit (FTM) with response unit (RP) for providing a required data width for storing the test vectors therein.

Abstract: A method and device are provided that use a sequencer in the device to control interactions on an interface bus. The sequencer is programmed to interrupt a co-processor before execution of a command. Based on the interrupt signal and a stored error mode page, a false error condition is initiated by further programming the sequencer to operate abnormally. After recovery from the error condition, the sequencer is reprogrammed to operate normally.