Abstract: A LAN connector 30 inserted between a high level equipment 11 and low level equipment 21, and incorporating only protocols for the first layer or up to the second layer for OSI to enable the transmission of communication data between the high level equipment and the low level equipment, comprises a ROM 65 to store disorder notification patterns correspondent with possible disorders, and a disorder notification control portion 51 which monitors an upside-originated idle signal from the high level equipment 11, or a downside-originated idle signal from low level equipment 21 using the protocol for the first layer; detects a disorder involving a component of the network as well as a disorder involving the LAN connector itself based on the monitoring result of the upside- or downside-originated idle signal; reads out from ROM a disorder notification pattern correspondent with the disorder thus detected; and transmits the pattern to the high level equipment 11 via an optical cable 70.

Abstract: The appliance comprises an audio port, which is usable as an interface for testing of the appliance. In a preferred embodiment, the appliance comprises stereo output ports, one port for a reception of digital test signals from a control computer and the other port for a transmission of digital signals from the appliance to the control computer. For the separation of the test signals and the audio signals a test adapter is used which is coupled between the appliance, the control computer and an amplifier for the audio signals. The test signals are modulated onto a carrier signal having a frequency of above 20 kHz, for example a frequency within the frequency range of 1-10 MHz. This allows a serial connection, which is compatible with the widely used RS232 link for set-top boxes.

Abstract: Digital signals are sent in a predetermined sequence from one end of a bus wire and are received at the other end. Each of the digital signals of the received sequence is compared with a corresponding predetermined signal of the predetermined sequence to determine whether an error has occurred. Data obtained concerning bus errors may be used to handle bus errors during runtime.

Abstract: A method for checking an error control unit in a circuit, wherein the error control unit generates an error signal, when operating properly, if the digital circuit is in an error state. The method includes the following steps: invoking the state indicating the error, monitoring the error signal, and generating an alarm signal when the error signal does not appear or appears incorrectly. A device for checking an error control unit of a circuit, wherein the error control unit generates an error signal when it is operating properly if the circuit is in or outputs a state indicating an error, has a device for inducing the state indicating the error, and a device for monitoring the error signal and generating an alarm signal when the error signal does not appear or appears incorrectly after the state indicating the error was induced.

Abstract: A method and system for updating software in a network element of a telecommunication network the units of which are divided into an original side and testing side. The system includes a network element, having units that are logically divided into an original side and testing side, an original software for performing traffic transmitting tasks, and a new piece of software to be tested and/or introduced. At least one test connections is directed into the units of testing side loaded with the new piece of software, in order to be able to test the new piece of software.

Abstract: A method of and system for awarding customers for staying in a store is provided. The method includes the steps of communicating between a store and a mobile device to determine whether the mobile device is within a predetermined locale; and crediting the mobile device to reward the user of the mobile device for presence within that locale. Various security features are included to prevent fraud, such as constantly transmitting random sequences to the mobile device along with the times of entry and exit. The store also periodically records the number of customers staying in the store within any one time.

Abstract: A method and apparatus for use with a computer system are disclosed. A packet is received that includes a header. The header indicates at least one characteristic that is associated with a layer of a protocol stack. The packet is parsed in hardware to extract the characteristic(s), and the packet is processed based on the parsing. Hardware may construct subsequent headers and update fields of the transport, network and data link layers.

Abstract: A test environment includes a test packet generator, a system under test, and a test device. The test packet generator generates test packets each containing a check value. The system under test performs a known transform of at least a portion of each test packet, and generates a new check value based on the transformed packet. The test device receives the transformed packets from the system under test and performs an error check based on the check value and also compares the check value with an expected check value to validate the content of each received packet. Each test packet contains a splice or signature value so that the new check value calculated by the system under test is equal to the expected check value if the system under test is functioning properly.

Abstract: A method and apparatus for initiating and analyzing an error recovery procedure in a data storage device is disclosed. Error recovery procedures are initiated by the simulation of an injected error event onto a particular location of the storage device. The simulation is implemented by corrupting the differential read signal of the storage device prior to error detection and decoding by the storage device. The operation and control of the software error recovery analysis tool is administered through a software application offering a graphical and interactive environment for measurement and automation. The application, corruption device, and a circuit designed to operate the timing and control of the tool are linked such that communication between the components defines the invention as a whole. During the signal corruption, the application allows the monitoring of any responses to the simulated error events by the data storage device.

Abstract: An N2 algorithm for optimizing correlated events, applicable to the optimization of the detection of redundant tests and inefficient tests (RIT's), is disclosed. This algorithm represents a set of N tests with L defects as N L-dimensional correlation vectors. The N2 algorithm optimizes in terms of the minimum set of vectors, and the set of vectors that take the minimum time to detect the L defects. The minimum set optimization determines a set of vectors (tests) that contains the minimum number of vectors (tests) by analyzing the correlation among the N vectors. This minimum set optimization provides the minimum test set containing all defects in an algorithm that takes O(N2) operations. The minimum time optimization determines a sequence of vectors (tests) that will detect the defects in a minimum amount of time.

Abstract: A system for controllable run-time verification of operations in a logic structure of a digital system. The system comprises a controllable bit stream generator which produces a controlled bit stream output. The controlled bit stream output corresponds to a bit sequence which instantiates a verification of operations within the logic structure. The system also comprises means for coupling the controlled bit stream output to the logic structure to verify the operations of the logic structure.

Abstract: In a computer network system that includes a multiplicity of nodes interconnected by a network of switches, wherein data are normally conveyed in the network according to predetermined conventions, a method for simulation testing of the system. One of the nodes is selected to serve as an error injector and injects data into the network in a manner that violates the predetermined conventions, so as to simulate an error condition in the system. Operation of the system is observed following the injection of the data so as to evaluate a response of the system to the error condition.

Abstract: A technique is used in a data terminal (110, 160) that encodes and decodes a data packet that is transmitted in a link of a frequency hopping system. During encoding, an information portion of the data packet is determined for transmission, a transmit redundancy check code is generated over the information portion and an identifier using a predetermined redundancy check code generator, and the data packet is generated to include the transmit redundancy check code and the information portion, but exclude the identifier. During decoding, the information portion and a received redundancy check code of the received data packet are determined, a calculated redundancy check code is generated over the information portion and the identifier, using the predetermined redundancy check code generator, and the information portion is rejected when the received redundancy check code does not match the calculated redundancy check code.

Abstract: A method evaluates and optimizes an error-correcting code to be transmitted through a noisy channel and to be decoded by an iterative message-passing decoder. The error-correcting code is represented by a parity check matrix which is modeled as a bipartite graph having variable nodes and check nodes. A set of message passing rules is provided for the decoder. The decoder is analyzed to obtain a set of density evolution rules including operators and operands which are then transformed to projective operators and projected operands to generate a set of projective message passing rules. The projective message passing rules are applied iteratively to the error-correcting code modeled by the bipartite graph until a termination condition is reached. Error rates of selected bits of the error-correcting code are then determined by evaluating the corresponding operands. The error rates can be passed to an optimizer to optimize the error-correcting code.

Abstract: A content-addressable memory (CAM) has a memory array for storing data, the memory array having E entries each having N data bits and a valid bit. The functionality of the CAM is tested by testing the memory array for read/write functionality. The functionality of a matching function, a priority encoding function, a match flag function, and a multiple match flag function of the CAM is tested. The functionality of an invalidate data function and a valid data restricted search function is also tested.

Abstract: A computer system for detecting alteration of programs in which a plurality of check program portions are read from a storage medium which carries computer programs including the check program portions. Each check program portion is executed to detect alteration of at least one other check program portion.

Abstract: Disclosed is a device and method for testing of a program or a design of an electronic device comprising digital logic circuitry. The method comprises testing the design of software or an electronic device and injecting, after initiation of the testing step, a predetermined error pattern into a value operated upon by the design of the digital logic circuitry. In a preferred embodiment, the software is a simulation of the design of a processor having a cache with error detection and/or correction circuitry. A triggering condition is preferably a cache hit, in response to which a detectable error is injected into the cache. The simulated operations of the model are observed to determine whether the injected error is detected, as should happen if the processor's error detection circuitry has been designed properly. In another respect, the invention is an apparatus, or computer software embedded on a computer readable medium, for testing a program comprising an error detector.

Abstract: The present invention provides an access control device and a testing method that can simplify the software operations in an access control operation such as a JTAG control operation, and enable the hardware to perform a high-speed control operation. The access control device conducts a test or diagnosis on an object by accessing a serial interface based on a command and data that specify a testing or diagnosing route. Under the control of a processor, a control circuit in the access control device executes an access sequence in accordance with a command string and an input data string stored in a memory, and stores the data outputted from the object to be tested or diagnosed in the memory as an output data string. The control circuit sets a state transition route for each objective state in advance, so that a transition route can be readily determined for an objective state specified by the command string.

Abstract: A decoding apparatus and decoding method for performing iteration decoding the suitable number of iterations, and thereby securing the desired transmission quality while decreasing the processing delay. Turbo decoder 301 iterates error correcting decoding on input coded sequences. Error checker 302 decodes an error detecting code contained in a decoded result of the error correcting decoding, and checks whether or not an error remains in the decoded result in turbo decoder 301. Iteration controller 303 instructs turbo decoder 301 to continue the iteration decoding until the number of iterations in the iteration decoding is more than or equal to the constraint number of iterations and error checker 302 determines no error in the decoded result.

Abstract: A method and an apparatus provides for calibrating a test system for an integrated semiconductor circuit, a pattern generator of the test system generating a test signal in the form of a pattern of successive rising and falling edges, which is composed of superposed sub-patterns formed via different internal paths of the pattern generator. The pattern generator provides an information signal for a measuring device of the test system, which identifies the edges of at least one sub-pattern of the test signal with regard to their origin from one of the internal paths. The calibration is carried out for the internal path separately using the information signal.

Abstract: An error correction method and a transmission apparatus used in a transmission using a frame including a header and a payload are provided. In the error correction method and the transmission apparatus, a pseudo error is inserted in check bits of the frame to be transmitted. Thus, an error-correcting function of a transmitter and a receiver can be easily tested. A mismatch of a state of validation or invalidation of the error-correcting function between the transmitter and the receiver can be avoided without affecting a main signal by inserting information on whether or not an error correction is performed in an unused area of the header in the transmitter.

Abstract: A communications network test system facilitates autonomous or attendant-free interaction between the administrative interfaces of multiple network devices under test. The test system includes device-specific communication interface packages that map generic commands to device-specific commands. A generic package includes generic procedures that access the device-specific packages to perform common functions, such as startup and cleanup. Test cases can thus be written using the generic commands without requiring the tester to have knowledge of device-specific demands. In addition, multiple devices can be simultaneously tested and monitored using a single test platform.

Abstract: A method of testing error correction/detection logic may involve providing each of a set of n data bit combinations to the error correction/detection logic. Each data bit combination has n bits, and the n data bit combinations may be created by creating an initial data bit combination whose data bits have the same logical value and then shifting a bit having the opposite value across the initial data bit combination. In response to being provided with the n data bit combinations, the error correction/detection logic generates a set of check bits for each of the n data bit combinations. The set of check bits generated by the error correction/detection logic for each of the n data bit combinations may then be verified.

Abstract: A system for run-time verification of operations within a logic structure of a digital system. The system comprises of a controllable bit stream generator for simulating an occurrence of a data travelling through said logic structure at a desired time. It also comprises of means for selecting a characteristic of the data where the characteristic includes how to verify the logic structure, and means for verifying the logic structure utilizing a combination of a controlled bit stream output of the controllable bit stream generator and the characteristic of the data.

Abstract: A radio paging receiver including a data memory (1) for memorizing message data and error indication data to overwrite the message data, a control unit (2) for overwriting the message data with the error indication data when the message data contains an error and transmitting for message display the message data overwritten with the error indication data, a display unit (5) for displaying the message data (including the error indication data in presence of the error), a code programmer (4) for setting a program for entering the error indication data in correspondence to code identification in response to an indication request, and an error identification memory (3) for rewritably memorizing the error indication data in correspondence to the code identification.

Abstract: System and method for testing the error detection and correction (“ECC”) capabilities of an ECC memory controller are disclosed. The system uses the natural state of the bus to induce one- or two-bit memory errors by disabling the ECC capabilities of the controller and then writing a test data pattern that is one or two bits different than a data pattern that would result in an ECC code equal to the natural state of the bus and an ECC code equal to the natural state of the bus to a selected memory location. At that point, the ECC capabilities of the memory controller are reenabled and the memory location to which the test data pattern was previously written is read and its ECC code generated. A determination is then made whether the memory controller detected and/or corrected the induced error.

Abstract: A terminator for an ULTRA-2-SCSI bus has an indicator to indicate an operating mode of the bus, a connector, a terminating unit connecting data lines of the ULTRA-2-SCSI bus to terminating resistors through the connector, a mode detector detecting an operating mode of the bus according to a voltage in a differential voltage detecting line of the bus, LEDs (212, 213) and LED drivers (215, 216) driving the LED's according to the output of the mode detector. These elements are arranged in a casing consisting of upper and lower covers (201, 202). The upper cover has LED lenses (205, 206) through which light from the LEDs passes and which indicates an operating mode of the bus.

Abstract: When there is an error in setting of a companding law of an encoder or a decoder, there is a problem of an error in judgment although it should be originally judged that the continuity of the testing channel does not exist.

Abstract: A method for evaluating the robustness of a logic circuit to soft errors involves injecting a current pulse into a node of the logic circuit. The current pulse is shaped to be representative of a high-energy particle strike, and may have an amplitude that is sufficient to momentarily discharge an output node of the logic circuit. The output node of the logic circuit is electrically monitored to determine whether a transition occurs from a first logic state to a second logic state in response to the injected current pulse. In the case where the state of the output node does flip in response to the injected current pulse, a waveform of the injected current pulse is integrated over time to compute a critical charge level (QCRIT). Where the amplitude is insufficient to cause the output node to flip, the amplitude of the injected current pulse is incremented and the above steps are repeated using the incremented amplitude until a logic state transition does occur at the output node.

Abstract: A method of validating an error correction code engine of a disc drive includes choosing a physical sector to use for running a validation test for validating the error correction code engine, determining if the physical sector is good, and performing the validation test using the physical sector if the physical sector is good. Another method of validating an error correction code engine in a disc drive includes receiving a first command from a host connected to the disc drive, determining whether to disable one or more of the plurality of error correction code functions in response to the command, disabling the one or more error correction code functions if the command indicates to disable the one or more error correction code functions and executing the command so that the host can validate the error correction code engine.

Abstract: Apparatus selects a state machine bit group from a plurality of state machine bit groups of a digital system for debugging the state machine connected to the selected bit group. The apparatus is adapted to output the bits of the selected bit group using existing output pins of the digital system, and includes a first multiplexer which is adapted to be connected to the plurality of state machine bit groups for outputting the selected state machine bit group. A second multiplexer is adapted to be connected to system signals and the selected state machine bit group from the first multiplexer, and outputs one of the system signals and the selected state machine bit group via the output pins of the system. A control circuit supplies a first select signal to the first multiplexer for selecting the selected state machine bit group output by the first multiplexer, and supplies a second select signal to the second multiplexer for selecting one of the selected bit group and the system signals.

Abstract:

Abstract: An ECC verification circuit including a first biasing circuit that is configured to output a predetermined logical signal. The verification circuit further includes a switch connected between the first biasing circuit and a first data bit line of a memory data bus of a computer system. The memory data bus includes a plurality of data bit lines and a plurality of check bit lines and the computer system includes error correction circuitry that is coupled to the memory data bus. The verification circuit is configured to activate the switch during a verification cycle of the computer system. In this manner, the predetermined logical signal is applied to the first data bit line during the verification cycle. The verification circuit is designed to apply a test state to the data bit lines and check bits lines of the memory data bus.

Abstract: A device for detecting errors with an integrated self-check, on an integrated circuit comprising a serial link control function for constituting an input-output port (109) between a parallel bus (L2CB, C2LB) and a serial link. The integrated circuit comprises a serializer circuit (109T) on output and a deserializer circuit (109R) on input. An insertion buffer I-sb has each of its outputs connected to one input of an exclusive OR operation with two inputs. The second input of the exclusive OR operation receives a piece of information (o-s) to be transmitted in order to constitute, with the insertion information issuing from the insertion buffer, a piece of substitute information. An additional buffer (I-tb) makes it possible to compare the sequence supplied as output from the exclusive OR with a sequence stored in the additional buffer (I-tb) in order to validate the transmission of the substitute sequence.

Abstract: To decrease the number of read errors of a storage device due to bus noise when data is transferred between a host apparatus and the storage device. When a read error due to bus noise is detected, transfer of data to a host apparatus is temporarily stopped when executing rereading to eliminate bus noise which is a cause of the read error. In a preferred embodiment bus noise errors are distinguished by looking at the frequency of errors and the retry count for the previous error. The error is detected as a bus noise error if the frequency is above a threshold and the retry count is below a threshold. Data transfer can be restarted when a buffer becomes full or when the reading of the data is successfully completed.

Abstract: In a method of checking an apparatus, failure time intervals of sections of an apparatus are divided into a plurality of failure time interval groups, each of which is indicated by a specific failure time interval. A plurality of check programs are classified into a plurality of groups corresponding to the plurality of failure time interval groups based on the failure time interval of the section corresponding to each of the plurality of check programs. A group execution time interval of each of the plurality of groups is determined based on the specific failure time interval. Then, each of the plurality of groups is executed based on the group execution time interval.

Abstract: One embodiment of the present invention includes an apparatus for inserting an error signal onto a bidirectional signal line. The apparatus includes a first switch for decoupling a first terminal of the bidirectional signal line from a second terminal of the bidirectional signal line, a second switch for coupling the error signal to the first terminal, and a third switch for coupling the error signal to the second terminal. The apparatus also includes a control unit for generating a switch enable signal. When the switch enable signal is deasserted, the first switch closes and the second and third switches open, such that the first terminal is coupled to the second terminal. When the switch enable signal is asserted, the first switch opens and the second and third switches close, such that the error signal is coupled to the first and second terminals.

Abstract: Given a target frequency (F.sub.VE), a reference frequency (F.sub.R), an error limit (E.sub.L), and a first divider range (150), a first (R) and a second (N) integer divider value are computed. First, an initial first divider (R) is selected (152). Then, a second divider (N) is computed as equal to the target frequency (F.sub.VE) divided by the reference frequency (F.sub.R) multiplied times the selected first divider (154). Then an error term (E) is computed to quantify the error introduced by using integers as dividers (156). The divider terms are accepted (166) if the error term is less than the error limit (158). Otherwise, a new first integer divider (R) is selected (160), repeating the computation of the second (N) divider (154), the computation of the error (E) term (156), and the test of the error term (E) against a limit as a loop (158). This loop is repeated until either the error term (E) is less than the error (E.sub.

Abstract: Concurrent Fault Detector Circuits (CFDCs) are test components of a main system, e.g. an Application Specific Integrated Circuit, and provide the results of the tests in parallel to at least one Error Source Register (ESR). Instead of reading out the ESR in parallel, its contents are copied to a serial shadow register so the contents can be read out in series to an error correcting application, thus reducing the number of output pins and the burden on resources of the main system. The ESR's receipt and transfer of information is under the control of a Boundary Scan Interface. In one embodiment, the test results are prioritized and compared to data in a mask register so that only important errors create a system interrupt which causes the read out of data from the shadow register.

Abstract: The invention discloses techniques for providing automatic retransmission query (ARQ) functions in a communication system. A transmitter in the system applies an input data packet to a first convolutional encoder operating at a first rate to generate an inner code including multiple encoded packets. The encoded packets are interleaved and applied to a second convolutional encoder operating at a second rate which generates an outer code including a transmit packet generated from each of the encoded packets. A first transmit packet is sent to a receiver, which decodes the transmit packet in a Viterbi decoder operating at the second rate to generate a decoded version of the first transmit packet. The decoded version is inverted to provide a first provisional decoding of the input packet. If a cyclic redundancy code (CRC) check of the first provisional decoding is passed, the receiver sends an ACK signal to the transmitter and no retransmission is required.

Abstract: A processor-to-memory interface (PMI) for a multiprocessor computer system and a computer testing method are disclosed. The multi-processor computer system provides a processor-to-memory-bus interface for each microprocessor. Each processor-to-memory-bus interface translates between microprocessor and bus protocols and manages respective level-2 (L2) caches. In addition, each interface includes test-event hardware that, when enabled causes test events to be generated with a predetermined repetition rate. The test events are selected for having a non-zero probability of causing system events that are complex, rare and non-fatal. These include assertions of "busy" and "wait" conditions and corrections of single-bit cache errors. The test-event hardware includes a timing generator that determines when test events are to be generated, an event-flag register that determines which events are to be generated, and a test-event generator that generates test-events at the times determined by the timing generator.