Abstract: An integrated circuit and method of designing an integrated circuit including an error detection and correction circuit is described. The integrated circuit includes a data-path being arranged between an output of a first register and second register clocked by a system clock. The integrated circuit includes a timing error detection and correction circuit (EDAC) which has a clock unit configured to receive a reference clock and to provide a delayed reference clock. The EDAC includes a plurality of transition detectors coupled to a respective node on the data-path and an error detection circuit coupled to each transition detector. The error detection circuit flags an error if a transition occurs during a time period between a transition of the reference clock and a corresponding transition of the delayed reference clock. A timing correction circuit coupled to the error detection circuit outputs the system clock derived from the delayed reference clock.

Abstract: Various implementations described herein are directed to device. The device may include a first tier having a processor and a first cache memory that are coupled together via control logic to operate as a computing architecture. The device may include a second tier having a second cache memory that is coupled to the first cache memory. Also, the first tier and the second tier may be integrated together with the computing architecture to operate as a stackable cache memory architecture.

Abstract: Provided are a method and a system for transmitting multiple data, in which the method includes receiving a plurality of transmission files for transmission from a transmission device of the first network to a reception device of the second network, and temporarily storing the received files, generating flexible packets by dividing each of the plurality of transmission files by a flexible packet length determined according to size of the files, in which a transmission file in a size smaller than the flexible packet length among the plurality of transmission files is generated as one flexible packet without being divided, loading the flexible packets into a plurality of flexible frames based on a corresponding transmission file priority according to a maximum data transmission size, and transmitting the plurality of flexible frames to the second network.

Abstract: Embodiments of the present disclosure relate to an UFS device and an operating method thereof. According to the embodiments of the present disclosure, the UFS device may collect status information of the UFS device, create an Acknowledgement and Flow Control (AFC) frame including the collected status information, and transmit the AFC frame to a host performing communication with the UFS device.

Abstract: A communication system includes a first information processing apparatus and a second information processing apparatus. The first information processing apparatus controls to determine an information amount to be used for a receipt acknowledgment response to packets to be transmitted to a second information processing apparatus on the basis of information relating to the packets and notifies the second information processing apparatus of that determined information amount. The second information processing apparatus controls to return the receipt acknowledgment response to the packets transmitted from the first information processing apparatus to the first information processing apparatus on the basis of the information amount notified from the first information processing apparatus.

Abstract: A radio reception apparatus and the like capable of eliminating a pseudo reception error while minimizing a change in a frame format are provided. A radio reception apparatus 30 according to the present disclosure includes: a receiving unit 301 configured to receive a frame from a radio transmission apparatus 20; a determination unit 302 configured to determine, using the frame received from the radio transmission apparatus 20, whether or not transmission of a preceding frame that has been received from the radio transmission apparatus 20 before receiving of the frame has been interrupted; and an error processing unit 306 configured to eliminate a reception error regarding the preceding frame in accordance with a determination that the transmission of the preceding frame has been interrupted.

Abstract: A BER corresponding to a group of memory cells programmed via a programing signal having one or more program step characteristics is determined. The determined BER and a target BER is compared. In response to the determined BER being different than the target BER, one or more program step characteristics are adjusted to adjust the determined BER to the target BER.

Abstract: A data structure is stored that includes a slope value corresponding to each die temperature of a set of die temperatures, where the slope value represents a change of a read voltage level as a function of a delay time of a memory sub-system. Using the data structure, a stored slope value corresponding to a measured die temperature is identified. An adjusted read voltage level is determined based at least in part on the stored slope value. The read command is executed using the adjusted read voltage level.

Abstract: A set of memory cells in a data block of a memory component is sampled. A distribution statistic is generated for the data block based on a reliability statistic for each of the set of sampled memory cells. A determination is made based on the distribution statistic of whether the read disturb stress is uniformly or non-uniformly distributed across the data block. In response to a determination that the read disturb stress is non-uniformly distributed across the data block, a first subset of the data block is relocated to another data block of the memory component. The first subset of the data block is associated with a higher concentration of read disturb stress than other subsets of the data block.

Abstract: Methods and circuits for storing column redundancy data are provided herein. A circuit may comprise a column redundancy data array, which may store an address and a plurality of match bits. A first portion of bits of the address may reference a range of columns of a memory array and a second portion of bits of the address may reference a division of the memory array in which a column of the range of columns is located. Each of the match bits may indicate whether one of the columns of the range of columns is defective.

Abstract: In general, embodiments of the technology relate to a method for characterizing persistent storage. The method includes selecting a sample set of physical addresses in a solid state memory module, where the sample set of physical addresses is associated with a region in the solid state memory module (SSMM). The method further includes issuing a write request to the sample set of physical addresses, after issuing the write request, issuing a request read to the sample set of physical addresses to obtain a copy of the data stored in the sample set of physical addresses, obtaining an error parameter for the copy of the data, determining a calculated P/E cycle value for the SSMM using at least the error parameter; and storing the calculated P/E cycle value in the SSMM.

Abstract: A data integrity check is performed on a data block of the memory component to obtain a reliability statistic for each of a set of sampled memory cells in the data block. A distribution statistic is determined based on the reliability statistic for each of the set of sampled memory cells. A subset of the data block is identified to be relocated to another data block of the memory component based on the distribution statistic. Data of the subset of the data block is relocated to the other data block.

Abstract: A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.

Abstract: A magnetic disk device includes a magnetic disk, which includes, in a track, a plurality of first sectors each recording user data and a second sector recording parity data for restoring the user data recorded in the first sectors, and a disk controller configured to read data from a plurality of sectors including the first sectors and the second sector based on an instruction from a host, and to detect whether there is an error in each of the first sectors when the user data is read from the first sectors. The disk controller continues reading the data recorded in the plurality of sectors even when an error is detected in one of the first sectors by the disk controller.

Abstract: A method is provided that includes performing a post-write read operation on a block of memory cells that includes a select gate transistor, and based on results of the post-write read operation selectively performing a select gate maintenance operation on the select gate transistor.

Abstract: A device can comprise a peaked integrator circuit that generates an output signal from a continuous time signal based on a sub rate clock timing cycle. The device can further comprise a track and hold circuit coupled to the output of the peaked integrator that generates a held discrete time signal from the output of the peaked integrator based on a second sub rate clock timing cycle that is offset in time from the sub rate clock timing cycle by a single time unit interval. The device can further comprise an integrator circuit coupled to an output of the track and hold circuit that integrates the held discrete time signal, based on the second sub rate clock timing cycle that is offset in time from the sub rate clock timing cycle by a single time unit interval.

Abstract: A method for optimizing a read threshold voltage shift value in a NAND flash memory may be provided. The method comprises selecting a group of memory pages, determining a current threshold voltage shift (TVS) value, and determining a negative and a positive threshold voltage shift offset value. Then, the method comprises repeating a loop process comprising reading all memory pages with different read TVS values, determining maximum raw bit error rates for the group of memory pages, determining a direction of change for the current TVS value, determining a new current TVS value by applying a function to the current TVS value using as parameters the current threshold voltage, the direction of change and the positive and the negative TVS value, until a stop condition is fulfilled such that a lowest possible number of read errors per group of memory pages is reached.

Abstract: A memory module includes a memory array, an interface and a controller. The memory array includes an array of memory cells and is configured as a dual in-line memory module (DIMM). The DIMM includes a plurality of connections that have been repurposed from a standard DIMM pin out configuration to interface operational status of the memory device to a host device. The interface is coupled to the memory array and the plurality of connections of the DIMM to interface the memory array to the host device. The controller is coupled to the memory array and the interface and controls at least one of a refresh operation of the memory array, control an error-correction operation of the memory array, control a memory scrubbing operation of the memory array, and control a wear-level control operation of the array, and the controller to interface with the host device.

Abstract: A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.

Abstract: A first data stored at a first portion of a memory cell and a second data stored at a second portion of the memory cell are identified. A first error rate associated with first data stored at the first portion of the memory cell is determined. The first error rate is adjusted to exceed a second error rate associated with the second data stored at the second portion of the memory cell. A determination is made as to whether the first error rate exceeds a threshold. The second data stored at the second portion of the memory cell is provided for use in an error correction operation in response to determining that the first error rate exceeds the threshold.

Abstract: The present disclosure includes apparatuses and methods related to a memory protocol. An example apparatus can perform operations on a number of block buffers of the memory device based on commands received from a host using a block configuration register, wherein the operations can read data from the number of block buffers and write data to the number of block buffers on the memory device.

Abstract: The present application relates to a baseband processor, comprising a receiver circuit configured to receive a downlink carrier aggregation transmission, wherein the baseband processor further comprises an encoder configured to generate a Cyclic Redundancy Check (CRC) code word based on at least one Hybrid Automatic Repeat Request-Acknowledgment (HARQ-ACK) feedback bit in response to the downlink carrier aggregation transmission, jointly encode at least one radio network parameter (P) of a user device with the CRC code word, and generate an uplink control information message (M) comprising the at least one HARQ-ACK feedback bit and the jointly encoded radio network parameter and CRC code word. Furthermore, the present application also relates to corresponding methods, a wireless communication system, a computer program, and a computer program product.

Abstract: A memory quality engine can improve the operation of a memory system by setting more effective operating parameters, disabling or removing memory devices unable to meet performance requirements, and providing evaluations between memory populations. These improvements can be accomplished by converting quality measurements of a memory population into CDF-based data, formulating comparisons of the CDF-based data to metrics for quality analysis, and applying the quality analysis. In some implementations, the metrics for quality analysis can use one or more thresholds, such as a system trigger threshold or an uncorrectable error correction condition threshold, which are set based on the error correction capabilities of a memory system. Formulating the comparison to these metrics can include determining an intersection between the CDF-based data and one of the thresholds.

Abstract: Technologies for endpoint congestion avoidance are disclosed. In order to avoid congestion caused by a network fabric that can transport data to a compute device faster than the compute device can store the data in a particular type of memory, the compute device may in the illustrative embodiment determine a suitable data transfer rate and communicate an indication of the data transfer rate to the remote compute device which is sending the data. The remote compute device may then send the data at the indicated data transfer rate, thus avoiding congestion.

Abstract: A method includes, in at least one aspect, designating a first region of a memory device for storing data of a first type and first error correcting code (ECC) data; designating a second region for storing data of a second type and second ECC data; receiving the data of the first type; generating the first ECC data for the data of the first type using a first ECC associated with a first ECC protection level; storing the data of the first type and the first ECC data in adjacent locations of the first region; receiving the data of the second type; generating the second ECC data for the data of the second type using a second ECC associated with a second ECC protection level; and storing the data of the second type and the second ECC data in the second region.

Abstract: Systems and methods are disclosed to perform out of order LBA processing at a data storage device. A data storage device may be configured to receive a read command including a sequential LBA range, read data for the LBA range in non-sequential order and store the data to a buffer, and return the data to the host in sequential LBA order. The storage device may begin a read operation at a sector in the middle of the LBA range, and read the beginning of the LBA range on a next rotation of the media. The storage device may note the location of read errors without interrupting a read operation. Successfully read data may be buffered, while rereads and error recovery may be performed only on LBAs at which errors were encountered. Once the data from the LBA range has been acquired, the data may be organized into sequential order.

Abstract: A system for providing underwater communication using orbital angular momentum (OAM) includes a transmitter that processes input data to be transmitted using pre-coding information based on current transmission channel conditions to maximize data rate based on channel conditions. A receiver receives a transmitted multiplexed OAM optical signal and analyzes the received signal for channel state information. The channel state information is used to determine a set of pre-coding values that allow the transmitter to pre-code the input data to maximize the data rate based on current channel conditions. The pre-coding values are mapped to a codebook entry which identifies the pre-coding values. The codebook entry is transmitted from the receiver to the transmitter. The transmitter uses the received codebook entry to identify pre-coding values used to process subsequent input data to be transmitted in order to enhance data rate across the transmit channel.

Abstract: In a packet transfer system, a transmission-side relay device extracts and integrates data included in a packet transmitted from a transmission device to obtain a packet data stream, extracts data from the packet data stream to obtain a data block, encodes the data block with an error correction code to generate redundant data as a redundant block, generates an error correction data stream obtained by integrating the data block and the redundant block, and packetizes the error correction data stream and transmits the packetized error correction data stream. A reception-side relay device restores missing data using redundant data included in the received data in a case in which there is missing data. The system enables packet transmission and reception to be efficiently performed even in a high loss rate environment.

Abstract: A semiconductor communication device includes a CRC calculation portion retrieving data pieces and CRC data piece as a retrieved data piece from a data signal, and performing a cyclic redundancy check calculation to obtain a CRC calculation value according to the retrieved data piece each time when the CRC calculation portion retrieves the retrieved data piece; a comparing portion generating an end detection signal indicating that the comparing portion detects a data end portion of the data signal when the CRC calculation value matches a value indicated with a subsequently retrieved data piece subsequently retrieved after the retrieved data piece is retrieved; and a communication responding portion determining whether the command is a non-corresponding command, and transmitting a command error signal when the communication responding portion determines that the command is the non-corresponding command.

Abstract: In an example, there is disclosed an apparatus, having: a first network interface, having a first clock and a local communication driver to communicatively couple the first network interface to a second network interface having a second clock; and one or more logic elements, including at least one hardware logic element, providing a synchronization engine to: send a first plurality of data words from the first wireless interface to the second wireless interface via the local communication driver; receive back from the second wireless interface a second plurality of data words; assign a plurality of error rates to the data words of the second plurality of data words, the plurality of error rates indicating match or mismatch; identify a range of least error values within the plurality of error rates; and select an agreed baud rate from within the range.

Abstract: A fiber optic tap system includes a first receiver module having an input port configured to receive an optical fiber. The first receiver module is operable to convert a received optical signal to an electrical signal. A first transmitter module is coupled to receive the electrical signal from the first receiver module and convert the received electrical signal to an optical signal. The first transmitter module has an output port for outputting the optical signal. A first tap module is coupled to receive the electrical signal from the first receiver module.

Abstract: The technology described in this document can be embodied in a computer-implemented method that includes receiving, at a first acoustic device, a representation of an audio signal, and amplifying the representation of the audio signal by a first gain factor to generate an amplified input signal. The method also includes processing the amplified input signal by an audio codec that includes one or more processors to generate a processed signal that represents a portion of the audio signal to be output by a second acoustic device. The processed signal includes noise originating at the audio codec. The method further includes transmitting the processed signal to the second acoustic device.

Abstract: An optical multi carrier signal has a modulation format and has many individual carrier signals. Parameters of the signal are controlled by receiving an indication of individual carrier transmission performance of the individual carrier signals, and selecting parameter values for the individual carrier signals, the parameter values comprising both a carrier FEC overhead and a carrier bandwidth for the modulation format. Selection is made according to the indicated individual carrier transmission performance and according to an overall spectral efficiency of the multi carrier signal. The selected parameter values are output for control of the optical multi carrier signal. By selecting values for both parameters rather than either one, better optimization can be obtained since they are interdependent. The control can have better granularity than changing modulation format, and can make better use of bandwidth or improve the overall capacity.

Abstract: A nonvolatile memory system, a nonvolatile memory controller and a method for reducing latency of a memory controller are disclosed. The nonvolatile memory controller includes a storage module configured to store data indicating threshold voltage shift read parameters and corresponding index values. The nonvolatile memory controller includes a status circuit configured to determine at least one usage characteristic of a nonvolatile memory device, and a read circuit configured to determine whether a usage characteristic meets a usage characteristic threshold. When a usage characteristic is determined to meet the usage characteristic threshold, the read circuit is configured to perform all subsequent reads of the nonvolatile memory device using a threshold voltage shift read instruction identified using one or more of the threshold voltage shift read parameters.

Abstract: A method begins by a processing module receiving a random order of encoded data slices and interpreting slice names to de-randomize the encoded data slices into of sets of transmit encoded data slices. The method continues with the processing module determining whether a decode threshold number of encoded data slices of a set of transmit encoded data slices have been received. When not received, the method continues with the processing module determining whether a sufficient number of encoded data slices of the set of transmit encoded data slices are still to be received and waiting until the decode threshold number of encoded data slices are received when encoded data slices are still to be received. When the decode threshold number of encoded data slices are received, the method continues with the processing module decoding the decode threshold number of encoded data slices to recapture a corresponding data segment.

Abstract: The various implementations described herein include systems, methods and/or devices for modifying an error correction format of a respective memory portion of non-volatile memory in a storage device. In one aspect, the method includes, for respective memory portions of the non-volatile memory, obtaining a performance metric of the respective memory portion, and modifying a current error correction format in accordance with the measured performance metric, the current error correction format corresponding to a code rate, codeword structure, and error correction type. Furthermore, data is stored, and errors are detected and corrected, in the respective memory portion in accordance with the modified error correction format. The current and modified error correction formats are distinct, and comprise two of a sequence of predefined error correction formats, wherein a plurality of the sequence of predefined error correction formats have a same number of error correction bits and different numbers of data bits.

Abstract: One or more values associated with a first configuration setting for a first circuit may be stored in a first set of one or more registers when an operation of the first circuit is based at least in part on one or more values associated with a second configuration setting stored in a second set of one or more registers. In response to receiving an indication of a change in an operating frequency or voltage of the first circuit, the one or more values stored in the second set of one or more registers may be changed by loading the one or more values associated with the first configuration setting stored in the first set of one or more registers into the second set of one or more registers in a parallel fashion.

Abstract: A method begins by a processing module receiving a random order of encoded data slices and interpreting slice names to de-randomize the encoded data slices into of sets of transmit encoded data slices. The method continues with the processing module determining whether a decode threshold number of encoded data slices of a set of transmit encoded data slices have been received. When not received, the method continues with the processing module determining whether a sufficient number of encoded data slices of the set of transmit encoded data slices are still to be received and waiting until the decode threshold number of encoded data slices are received when encoded data slices are still to be received. When the decode threshold number of encoded data slices are received, the method continues with the processing module decoding the decode threshold number of encoded data slices to recapture a corresponding data segment.

Abstract: Device for selecting a level for at least one read voltage for reading data stored in a multi-level memory device. The multi-level memory device includes a plurality of memory blocks, in which each of the memory blocks includes a plurality of word lines, each of the word lines being allocated to a plurality of memory pages and being indexed by a word line index. The device includes a first mapping unit for mapping each of the word line indices to one bin label, in which the number of bin labels is smaller than the number of word lines, and a second mapping unit for mapping each of the bin labels to a voltage information being indicative for at least one read voltage, in which the level for the at least one read voltage for reading data is selectable for each word line based on the respective word line index.

Abstract: Analyzing data is disclosed. Error events are tracked. The error events are classified based on a number of errors included in each event. A desired level of error event to be able to be corrected in order to maintain an acceptable rate of uncorrected errors is determined. A redundancy level is selected so that new error events corresponding to the desired level of error event or a lower level of error event are corrected.

Abstract: Systems and methods presented herein enhance WiFi communications in a RF band where conflicting LTE signaling exists. In one embodiment, a system includes a processor operable to detect the WiFi communications between a UE and a wireless access point of a WiFi network, to identify errors in the WiFi communications, and to determine a periodicity of the errors based on the LTE signaling structure. The system also includes an encoder communicatively coupled to the processor and operable to encode the WiFi communications with error correction, and to change the error correction based on the periodicity of the errors in the WiFi communications.

Abstract: Methods, systems, and devices are described for power conservation in a wireless communications system through efficient transmissions and acknowledgements of information between an AP and a station. The time between a determination by a station to enter a power saving mode and entering network sleep mode by the station may be reduced through a transmission, by an AP, of an MPDU to the station successive to an SIFS after transmission of an acknowledgement to the station of a PS-Poll frame from the station. The time to enter a power saving mode by a station may also be reduced through transmission of A-MPDUs in which a last MPDU of the A-MPDU has an indicator bit cleared to indicate no additional data is to be transmitted. An AP may prevent a retransmission of an MPDU to the station in the absence of an acknowledgement from the station, to further enhance efficiency.

Abstract: A semiconductor device disclosed in this disclosure includes a first terminal formed above a first surface of a semiconductor substrate, a second terminal formed above a second surface of the semiconductor substrate opposite to the first surface, a first through substrate via (TSV) penetrating the semiconductor substrate, and a first-in first-out (FIFO) circuit, wherein the first TSV and the FIFO circuit are coupled in series between the first terminal and the second terminal.

Abstract: A radio wave receiver includes a receiver controller that performs a signal capturing action in regular or irregular intervals to capture data transmitted on radio waves from a remote terminal in synchronization with the signal capturing action. The receiver controller includes a correctness determination unit and a capturing frequency setting unit. The correctness determination unit calculates an error rate or a correctness rate of the data captured by the receiver controller to determine the correctness of the captured data. The capturing frequency setting unit sets a capturing frequency indicating the number of times the signal capturing action is performed during a certain period in accordance with the correctness of the captured data.

Abstract: A page buffer suitable for continuous page read may be implemented with a partitioned data register, a partitioned cache register, and a suitable ECC circuit. The partitioned data register, partitioned cache register, and associated ECC circuit may also be used to realize a substantial improvement in the page read operation by using a modified Page Data Read instruction and/or a Buffer Read instruction, including in some implementations the use of a partition busy bit.

Abstract: A data access method for a rewritable non-volatile memory module is provided. The method includes: filling dummy data to first data in order to generate second data, and writing the second data and an error checking and correcting code (ECC code) corresponding to the second data into a first physical programming unit. The method also includes: reading data stream from the first physical programming unit, wherein the data stream includes third data and the ECC code. The method further includes: adjusting the third data according to a pattern of the dummy data in order to generate fourth data when the third data cannot be corrected by using the ECC code, and using the ECC code to correct the fourth data in order to obtain corrected data, wherein the corrected data is identical to the second data.

Abstract: A non-volatile (“NV”) memory device is able to enhance data integrity using threshold voltage (“Vt”) recalibration based on a selected scheme. Upon receiving a command for reading a data page, the process, in one embodiment, identifies a reference page which is located at a predefined location in a block of the NV memory. After reading the first reference data from the reference page by a reader in response to a first or current Vt, a first bit error rate (“BER”) is generated based on the comparison between the first reference data and the predefined known data pattern. If the first BER is greater than a predefined BER target, a second Vt is subsequently calculated in accordance with the first Vt. When the second BER is equal to or less than the predefined BER target, an optimal Vt is set to the second Vt. There are also two other methods using DC balance coding scheme and counting the number of 1's in the selected data page can be used in recalibrating the threshold voltage.

Abstract: A node for a communications network has a converter for digitizing at a receiver clock rate a received optical signal received over an optical link from an optical transmitter at a source node, a framer for detecting frames and a forward error correction part for correcting errors in the payload of the frame. An error rate in the received payload part is monitored and a processor sends, according to the monitored error rate, a request to the optical transmitter to adapt a length of the transmitted forward error correction part and to adapt a clock rate of the transmission of the frame if FEC length is reduced or FEC is disabled. This can enable power saving, when less FEC information is being sent.

Abstract: A method for an adaptive forward error correction (FEC) in a passive optical network. The method comprises selecting an initial downstream FEC code to be applied on downstream data transmitted from an optical line terminal (OLT) to a plurality of optical network units (ONUs) of the PON; communicating the selected downstream FEC code to the plurality of ONUs; receiving at least one downstream bit error ratio (BER) value from at least one ONU of the plurality of ONUs, wherein the downstream BER value is measured respective to downstream data received at the at least one ONU; changing the selected downstream FEC code to a new downstream FEC code based on a plurality of downstream BER values measured by the at least one ONU; and communicating the new downstream FEC code to the plurality of ONUs.

Abstract: A data transmission method, device and system to improve reliability of a data link. When the sender side detects erroneous data, the erroneous data is discarded and a data retransmission request is sent to the sender side to ensure correctness of received data and improve reliability of the data link; and, when the sender side detects the erroneous data and a bit error rate is greater than a preset bit error rate threshold, the data link gets into auto recovery, and data transmission is resumed after the recovery succeeds, thereby avoiding an excessively high bit error rate, preventing an excessively high probability of omitted checks (the higher the bit error rate is, the higher probability of omitted checks is), and further improving reliability of the data link.